x393_parallel.timing_summary_impl

Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
| Date         : Mon Mar 22 12:57:42 2021
| Host         : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS
| Command      : report_timing_summary -file vivado_build/x393_parallel.timing_summary_impl
| Design       : x393
| Device       : 7z030-fbg484
| Speed File   : -1  PRODUCTION 1.11 2014-09-11
--------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  false

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        



check_timing report

Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops

1. checking no_clock
--------------------
 There are 16 register/latch pins with no clock driven by root clock pin: DQSL (HIGH)

 There are 16 register/latch pins with no clock driven by root clock pin: DQSU (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: ffclk1p (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: memclk (HIGH)


2. checking constant_clock
--------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock
-----------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints
--------------------------------------------
 There are 20 pins that are not constrained for maximum delay. (HIGH)

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay
--------------------------
 There are 98 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay
---------------------------
 There are 87 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock
--------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks
----------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops
-----------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay
--------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay
---------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops
------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.047        0.000                      0               150196        0.025        0.000                      0               150196        0.264        0.000                       0                 61202  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock           Waveform(ns)         Period(ns)      Frequency(MHz)
-----           ------------         ----------      --------------
axi_aclk        {0.000 10.000}       20.000          50.000          
  axihp_clk     {0.000 3.333}        6.667           150.000         
  clk_fb        {0.000 10.000}       20.000          50.000          
  ddr3_clk      {0.000 1.250}        2.500           400.000         
  ddr3_clk_div  {0.000 2.500}        5.000           200.000         
  ddr3_clk_ref  {0.000 2.500}        5.000           200.000         
  ddr3_mclk     {1.250 3.750}        5.000           200.000         
  ddr3_sdclk    {0.000 1.250}        2.500           400.000         
  multi_clkfb   {0.000 10.000}       20.000          50.000          
  sclk          {0.000 5.000}        10.000          100.000         
  xclk          {0.000 2.083}        4.167           240.000         
ffclk0          {0.000 20.833}       41.667          24.000          
  clkfb         {0.000 20.833}       41.667          24.000          
  pclk          {0.000 5.208}        10.417          95.999          
    clk_fb_1    {0.000 5.208}        10.417          95.999          
    clk_fb_2    {0.000 5.208}        10.417          95.999          
    clk_fb_3    {0.000 5.208}        10.417          95.999          
    clk_fb_4    {0.000 5.208}        10.417          95.999          
    iclk0       {0.000 5.208}        10.417          95.999          
    iclk1       {0.000 5.208}        10.417          95.999          
    iclk2       {0.000 5.208}        10.417          95.999          
    iclk2x0     {0.000 2.604}        5.208           191.998         
    iclk2x1     {0.000 2.604}        5.208           191.998         
    iclk2x2     {0.000 2.604}        5.208           191.998         
    iclk2x3     {0.000 2.604}        5.208           191.998         
    iclk3       {0.000 5.208}        10.417          95.999          
gtrefclk        {0.000 3.333}        6.666           150.015         
rx_clk          {0.000 3.333}        6.666           150.015         
txoutclk        {0.000 3.333}        6.666           150.015         
usrclk2         {0.000 6.666}        13.333          75.002          


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock               WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----               -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
axi_aclk             13.986        0.000                      0                 2685        0.030        0.000                      0                 2685        7.000        0.000                       0                   737  
  axihp_clk           0.458        0.000                      0                10209        0.044        0.000                      0                10209        0.267        0.000                       0                  3863  
  clk_fb                                                                                                                                                         18.751        0.000                       0                     2  
  ddr3_clk                                                                                                                                                        0.279        0.000                       0                    45  
  ddr3_clk_div        0.181        0.000                      0                 2158        0.119        0.000                      0                 2158        1.389        0.000                       0                   755  
  ddr3_clk_ref                                                                                                                                                    0.264        0.000                       0                     5  
  ddr3_mclk           0.285        0.000                      0                82594        0.031        0.000                      0                82594        1.389        0.000                       0                 33324  
  ddr3_sdclk                                                                                                                                                      1.092        0.000                       0                     3  
  multi_clkfb                                                                                                                                                    18.751        0.000                       0                     2  
  sclk                4.027        0.000                      0                 2907        0.044        0.000                      0                 2907        4.090        0.000                       0                  1445  
  xclk                0.052        0.000                      0                33109        0.025        0.000                      0                33109        0.875        0.000                       0                 13494  
ffclk0               40.274        0.000                      0                    1        0.576        0.000                      0                    1       10.833        0.000                       0                     2  
  clkfb                                                                                                                                                          10.966        0.000                       0                     2  
  pclk                0.814        0.000                      0                 8199        0.037        0.000                      0                 8199        2.208        0.000                       0                  4171  
    clk_fb_1                                                                                                                                                      9.168        0.000                       0                     2  
    clk_fb_2                                                                                                                                                      9.168        0.000                       0                     2  
    clk_fb_3                                                                                                                                                      9.168        0.000                       0                     2  
    clk_fb_4                                                                                                                                                      9.168        0.000                       0                     2  
    iclk0             7.148        0.000                      0                  425        0.093        0.000                      0                  425        4.298        0.000                       0                   177  
    iclk1             7.332        0.000                      0                  425        0.125        0.000                      0                  425        4.298        0.000                       0                   177  
    iclk2             7.270        0.000                      0                  425        0.112        0.000                      0                  425        4.298        0.000                       0                   177  
    iclk2x0                                                                                                                                                       3.801        0.000                       0                    30  
    iclk2x1                                                                                                                                                       3.608        0.000                       0                    30  
    iclk2x2                                                                                                                                                       3.801        0.000                       0                    30  
    iclk2x3                                                                                                                                                       3.608        0.000                       0                    30  
    iclk3             6.145        0.000                      0                  425        0.069        0.000                      0                  425        4.298        0.000                       0                   177  
gtrefclk              4.481        0.000                      0                   45        0.218        0.000                      0                   45        2.553        0.000                       0                    25  
rx_clk                0.855        0.000                      0                  917        0.066        0.000                      0                  917        2.423        0.000                       0                   329  
txoutclk              2.026        0.000                      0                  232        0.127        0.000                      0                  232        2.666        0.000                       0                   138  
usrclk2               4.435        0.000                      0                 4577        0.070        0.000                      0                 4577        5.756        0.000                       0                  2024  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
ddr3_clk_div  ddr3_clk            0.196        0.000                      0                   23        0.213        0.000                      0                   23  
ddr3_mclk     ddr3_clk_div        0.047        0.000                      0                  146        1.423        0.000                      0                  146  
ddr3_clk_div  ddr3_mclk           2.762        0.000                      0                   76        0.533        0.000                      0                   76  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group         From Clock         To Clock               WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------         ----------         --------               -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
**async_default**  axihp_clk          axihp_clk                1.916        0.000                      0                   23        0.605        0.000                      0                   23  
**async_default**  ddr3_mclk          ddr3_mclk                0.808        0.000                      0                  457        0.269        0.000                      0                  457  
**async_default**  iclk0              iclk0                    7.983        0.000                      0                    6        0.598        0.000                      0                    6  
**async_default**  iclk1              iclk1                    7.597        0.000                      0                    6        0.610        0.000                      0                    6  
**async_default**  iclk2              iclk2                    8.829        0.000                      0                    6        0.353        0.000                      0                    6  
**async_default**  iclk3              iclk3                    6.939        0.000                      0                    6        0.575        0.000                      0                    6  
**async_default**  pclk               pclk                     5.578        0.000                      0                   20        0.433        0.000                      0                   20  
**async_default**  sclk               sclk                     5.107        0.000                      0                   16        0.367        0.000                      0                   16  
**async_default**  usrclk2            usrclk2                  6.352        0.000                      0                    7        0.984        0.000                      0                    7  
**async_default**  xclk               xclk                     0.616        0.000                      0                   72        0.498        0.000                      0                   72  


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  axi_aclk
  To Clock:  axi_aclk

Setup :            0  Failing Endpoints,  Worst Slack       13.986ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.030ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        7.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             13.986ns  (required time - arrival time)
  Source:                 axibram_write_i/dev_ready_r_reg/C
                            (rising edge-triggered cell FDRE clocked by axi_aclk  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            mcntrl393_i/buf3wr_we_reg/R
                            (rising edge-triggered cell FDRE clocked by axi_aclk  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             axi_aclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            20.000ns  (axi_aclk rise@20.000ns - axi_aclk rise@0.000ns)
  Data Path Delay:        5.223ns  (logic 0.554ns (10.608%)  route 4.669ns (89.392%))
  Logic Levels:           2  (LUT1=1 LUT3=1)
  Clock Path Skew:        -0.272ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.291ns = ( 21.291 - 20.000 ) 
    Source Clock Delay      (SCD):    1.573ns
    Clock Pessimism Removal (CPR):    0.010ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock axi_aclk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.573     1.573    axibram_write_i/axi_clk
    SLICE_X32Y150        FDRE                                         r  axibram_write_i/dev_ready_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y150        FDRE (Prop_fdre_C_Q)         0.308     1.881 f  axibram_write_i/dev_ready_r_reg/Q
                         net (fo=8, routed)           0.835     2.716    axibram_write_i/wdata_i/dev_ready_r
    SLICE_X31Y153        LUT3 (Prop_lut3_I2_O)        0.065     2.781 f  axibram_write_i/wdata_i/buf_waddr[9]_i_1/O
                         net (fo=48, routed)          2.869     5.650    axibram_write_i/wdata_i/buf_wdata_reg[0]
    SLICE_X33Y133        LUT1 (Prop_lut1_I0_O)        0.181     5.831 r  axibram_write_i/wdata_i/buf0wr_we_i_1/O
                         net (fo=4, routed)           0.964     6.796    mcntrl393_i/write_in_progress_reg
    SLICE_X27Y127        FDRE                                         r  mcntrl393_i/buf3wr_we_reg/R
  -------------------------------------------------------------------    -------------------

                         (clock axi_aclk rise edge)
                                                     20.000    20.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000    20.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.291    21.291    mcntrl393_i/axi_clk
    SLICE_X27Y127        FDRE                                         r  mcntrl393_i/buf3wr_we_reg/C
                         clock pessimism              0.010    21.301    
                         clock uncertainty           -0.035    21.266    
    SLICE_X27Y127        FDRE (Setup_fdre_C_R)       -0.484    20.782    mcntrl393_i/buf3wr_we_reg
  -------------------------------------------------------------------
                         required time                         20.782    
                         arrival time                          -6.796    
  -------------------------------------------------------------------
                         slack                                 13.986    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.030ns  (arrival time - required time)
  Source:                 axibram_write_i/waddr_i/wa_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by axi_aclk  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            axibram_write_i/waddr_i/ram_reg_0_15_12_17/RAMA/WADR2
                            (rising edge-triggered cell RAMD32 clocked by axi_aclk  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             axi_aclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (axi_aclk rise@0.000ns - axi_aclk rise@0.000ns)
  Data Path Delay:        0.351ns  (logic 0.091ns (25.917%)  route 0.260ns (74.083%))
  Logic Levels:           0  
  Clock Path Skew:        0.118ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.739ns
    Source Clock Delay      (SCD):    0.613ns
    Clock Pessimism Removal (CPR):    0.008ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock axi_aclk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.613     0.613    axibram_write_i/waddr_i/axi_clk
    SLICE_X33Y150        FDRE                                         r  axibram_write_i/waddr_i/wa_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y150        FDRE (Prop_fdre_C_Q)         0.091     0.704 r  axibram_write_i/waddr_i/wa_reg[2]/Q
                         net (fo=36, routed)          0.260     0.964    axibram_write_i/waddr_i/ram_reg_0_15_12_17/ADDRD2
    SLICE_X32Y149        RAMD32                                       r  axibram_write_i/waddr_i/ram_reg_0_15_12_17/RAMA/WADR2
  -------------------------------------------------------------------    -------------------

                         (clock axi_aclk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.739     0.739    axibram_write_i/waddr_i/ram_reg_0_15_12_17/WCLK
    SLICE_X32Y149        RAMD32                                       r  axibram_write_i/waddr_i/ram_reg_0_15_12_17/RAMA/CLK
                         clock pessimism             -0.008     0.731    
    SLICE_X32Y149        RAMD32 (Hold_ramd32_CLK_WADR2)
                                                      0.203     0.934    axibram_write_i/waddr_i/ram_reg_0_15_12_17/RAMA
  -------------------------------------------------------------------
                         required time                         -0.934    
                         arrival time                           0.964    
  -------------------------------------------------------------------
                         slack                                  0.030    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         axi_aclk
Waveform(ns):       { 0.000 10.000 }
Period(ns):         20.000
Sources:            { clocks393_i/bufg_axi_aclk_i/O }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     RAMB36E1/CLKBWRCLK  n/a            2.183         20.000      17.817     RAMB36_X3Y32    cmd_readback_i/ram_reg_0/CLKBWRCLK
Max Period        n/a     PLLE2_ADV/CLKIN1    n/a            52.633        20.000      32.633     PLLE2_ADV_X1Y3  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKIN1
Low Pulse Width   Slow    PLLE2_ADV/CLKIN1    n/a            3.000         10.000      7.000      PLLE2_ADV_X1Y3  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKIN1
High Pulse Width  Slow    PLLE2_ADV/CLKIN1    n/a            3.000         10.000      7.000      PLLE2_ADV_X1Y3  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKIN1



---------------------------------------------------------------------------------------------------
From Clock:  axihp_clk
  To Clock:  axihp_clk

Setup :            0  Failing Endpoints,  Worst Slack        0.458ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.044ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.267ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.458ns  (required time - arrival time)
  Source:                 sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wdata_i/outreg_reg[36]/C
                            (rising edge-triggered cell FDRE clocked by axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            sata_top/ahci_top_i/axi_ahci_regs_i/hba_reset_cntr_reg[0]/CE
                            (rising edge-triggered cell FDRE clocked by axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             axihp_clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (axihp_clk rise@6.667ns - axihp_clk rise@0.000ns)
  Data Path Delay:        5.750ns  (logic 0.941ns (16.364%)  route 4.809ns (83.636%))
  Logic Levels:           8  (LUT3=1 LUT4=2 LUT5=4 LUT6=1)
  Clock Path Skew:        -0.028ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.944ns = ( 11.611 - 6.667 ) 
    Source Clock Delay      (SCD):    5.428ns
    Clock Pessimism Removal (CPR):    0.456ns
  Clock Uncertainty:      0.071ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.124ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock axihp_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.784     1.784    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X1Y3       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.088     1.872 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.868     3.740    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.120     3.860 r  clocks393_i/hclk_i/clk1x_i/O
                         net (fo=3868, routed)        1.568     5.428    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wdata_i/hclk
    SLICE_X32Y162        FDRE                                         r  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wdata_i/outreg_reg[36]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y162        FDRE (Prop_fdre_C_Q)         0.282     5.710 f  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wdata_i/outreg_reg[36]/Q
                         net (fo=2, routed)           0.695     6.405    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wdata_i/wlast_out
    SLICE_X36Y161        LUT5 (Prop_lut5_I0_O)        0.153     6.558 f  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wdata_i/write_in_progress_i_2/O
                         net (fo=3, routed)           0.436     6.994    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wdata_i/write_in_progress_i_2_n_0
    SLICE_X36Y158        LUT5 (Prop_lut5_I0_O)        0.053     7.047 f  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wdata_i/wburst[1]_i_1/O
                         net (fo=31, routed)          0.500     7.547    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/write_in_progress_reg[0]
    SLICE_X36Y158        LUT4 (Prop_lut4_I3_O)        0.053     7.600 r  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/RAMB36E1_i_i_1__41/O
                         net (fo=55, routed)          0.394     7.994    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/bram_ren_0
    SLICE_X38Y156        LUT5 (Prop_lut5_I1_O)        0.053     8.047 f  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/RAMB36E1_i_i_5__4/O
                         net (fo=4, routed)           0.853     8.900    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/data_in[8]
    SLICE_X37Y144        LUT4 (Prop_lut4_I2_O)        0.053     8.953 f  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/pgm_ad[17]_i_3/O
                         net (fo=2, routed)           0.441     9.394    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/pgm_ad[17]_i_3_n_0
    SLICE_X37Y144        LUT3 (Prop_lut3_I0_O)        0.067     9.461 f  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/hba_reset_cntr[8]_i_5/O
                         net (fo=2, routed)           0.278     9.739    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/hba_reset_cntr[8]_i_5_n_0
    SLICE_X38Y145        LUT6 (Prop_lut6_I0_O)        0.170     9.909 r  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/hba_reset_cntr[8]_i_4/O
                         net (fo=12, routed)          0.770    10.679    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/set_hba_rst
    SLICE_X44Y156        LUT5 (Prop_lut5_I4_O)        0.057    10.736 r  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/hba_reset_cntr[8]_i_1/O
                         net (fo=9, routed)           0.442    11.178    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i_n_92
    SLICE_X44Y156        FDRE                                         r  sata_top/ahci_top_i/axi_ahci_regs_i/hba_reset_cntr_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock axihp_clk rise edge)
                                                      6.667     6.667 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     6.667 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.593     8.260    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X1Y3       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.083     8.343 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.754    10.097    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.113    10.210 r  clocks393_i/hclk_i/clk1x_i/O
                         net (fo=3868, routed)        1.401    11.611    sata_top/ahci_top_i/axi_ahci_regs_i/hclk
    SLICE_X44Y156        FDRE                                         r  sata_top/ahci_top_i/axi_ahci_regs_i/hba_reset_cntr_reg[0]/C
                         clock pessimism              0.456    12.067    
                         clock uncertainty           -0.071    11.995    
    SLICE_X44Y156        FDRE (Setup_fdre_C_CE)      -0.359    11.636    sata_top/ahci_top_i/axi_ahci_regs_i/hba_reset_cntr_reg[0]
  -------------------------------------------------------------------
                         required time                         11.636    
                         arrival time                         -11.178    
  -------------------------------------------------------------------
                         slack                                  0.458    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.044ns  (arrival time - required time)
  Source:                 sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wresp_i/inreg_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wresp_i/ram_reg_0_15_0_5/RAMC/I
                            (rising edge-triggered cell RAMD32 clocked by axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             axihp_clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (axihp_clk rise@0.000ns - axihp_clk rise@0.000ns)
  Data Path Delay:        0.146ns  (logic 0.091ns (62.374%)  route 0.055ns (37.626%))
  Logic Levels:           0  
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.681ns
    Source Clock Delay      (SCD):    2.144ns
    Clock Pessimism Removal (CPR):    0.526ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock axihp_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.666     0.666    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X1Y3       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.050     0.716 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.774     1.490    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.026     1.516 r  clocks393_i/hclk_i/clk1x_i/O
                         net (fo=3868, routed)        0.628     2.144    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wresp_i/hclk
    SLICE_X31Y163        FDRE                                         r  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wresp_i/inreg_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X31Y163        FDRE (Prop_fdre_C_Q)         0.091     2.235 r  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wresp_i/inreg_reg[4]/Q
                         net (fo=1, routed)           0.055     2.290    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wresp_i/ram_reg_0_15_0_5/DIC0
    SLICE_X30Y163        RAMD32                                       r  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wresp_i/ram_reg_0_15_0_5/RAMC/I
  -------------------------------------------------------------------    -------------------

                         (clock axihp_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.903     0.903    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X1Y3       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.053     0.956 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.843     1.799    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.030     1.829 r  clocks393_i/hclk_i/clk1x_i/O
                         net (fo=3868, routed)        0.852     2.681    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wresp_i/ram_reg_0_15_0_5/WCLK
    SLICE_X30Y163        RAMD32                                       r  sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wresp_i/ram_reg_0_15_0_5/RAMC/CLK
                         clock pessimism             -0.526     2.155    
    SLICE_X30Y163        RAMD32 (Hold_ramd32_CLK_I)
                                                      0.091     2.246    sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wresp_i/ram_reg_0_15_0_5/RAMC
  -------------------------------------------------------------------
                         required time                         -2.246    
                         arrival time                           2.290    
  -------------------------------------------------------------------
                         slack                                  0.044    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         axihp_clk
Waveform(ns):       { 0.000 3.333 }
Period(ns):         6.667
Sources:            { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 }

Check Type        Corner  Lib Pin               Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location            Pin
Min Period        n/a     GTXE2_CHANNEL/DRPCLK  n/a            6.400         6.667       0.267      GTXE2_CHANNEL_X0Y0  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/DRPCLK
Max Period        n/a     PLLE2_ADV/CLKOUT0     n/a            160.000       6.667       153.333    PLLE2_ADV_X1Y3      clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
Low Pulse Width   Slow    RAMD32/CLK            n/a            0.910         3.333       2.423      SLICE_X26Y139       sata_top/ahci_top_i/ahci_dma_i/axi_hp_abort_i/aw_lengths_ram_reg_0_31_0_3/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK            n/a            0.910         3.333       2.423      SLICE_X38Y128       sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/fifo_ram_reg_0_7_24_29/RAMA/CLK



---------------------------------------------------------------------------------------------------
From Clock:  clk_fb
  To Clock:  clk_fb

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack       18.751ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_fb
Waveform(ns):       { 0.000 10.000 }
Period(ns):         20.000
Sources:            { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT }

Check Type  Corner  Lib Pin              Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            1.249         20.000      18.751     MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT
Max Period  n/a     MMCME2_ADV/CLKFBIN   n/a            100.000       20.000      80.000     MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBIN



---------------------------------------------------------------------------------------------------
From Clock:  ddr3_clk
  To Clock:  ddr3_clk

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.279ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ddr3_clk
Waveform(ns):       { 0.000 1.250 }
Period(ns):         2.500
Sources:            { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1 }

Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     BUFR/I              n/a            2.221         2.500       0.279      BUFR_X1Y8        mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_bufr_i/I
Max Period  n/a     MMCME2_ADV/CLKOUT1  n/a            213.360       2.500       210.860    MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1



---------------------------------------------------------------------------------------------------
From Clock:  ddr3_clk_div
  To Clock:  ddr3_clk_div

Setup :            0  Failing Endpoints,  Worst Slack        0.181ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.119ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        1.389ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.181ns  (required time - arrival time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/rst_reg/C
                            (rising edge-triggered cell FDRE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_ba2_i/oserdes_i/oserdes_i/RST
                            (rising edge-triggered cell OSERDESE2 clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             ddr3_clk_div
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (ddr3_clk_div rise@5.000ns - ddr3_clk_div rise@0.000ns)
  Data Path Delay:        3.954ns  (logic 0.269ns (6.802%)  route 3.685ns (93.198%))
  Logic Levels:           0  
  Clock Path Skew:        -0.034ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.645ns = ( 8.645 - 5.000 ) 
    Source Clock Delay      (SCD):    3.935ns
    Clock Pessimism Removal (CPR):    0.256ns
  Clock Uncertainty:      0.085ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_clk_div rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     1.575    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.088     1.663 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           1.106     2.769    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.377     3.146 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.789     3.935    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/CLK
    SLICE_X68Y108        FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/rst_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X68Y108        FDRE (Prop_fdre_C_Q)         0.269     4.204 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/rst_reg/Q
                         net (fo=786, routed)         3.685     7.889    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_ba2_i/oserdes_i/tin
    OLOGIC_X1Y102        OSERDESE2                                    r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_ba2_i/oserdes_i/oserdes_i/RST
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_clk_div rise edge)
                                                      5.000     5.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     5.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     6.437    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.083     6.520 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           1.016     7.536    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.370     7.906 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.739     8.645    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_ba2_i/oserdes_i/psincdec_reg
    OLOGIC_X1Y102        OSERDESE2                                    r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_ba2_i/oserdes_i/oserdes_i/CLKDIV
                         clock pessimism              0.256     8.901    
                         clock uncertainty           -0.085     8.816    
    OLOGIC_X1Y102        OSERDESE2 (Setup_oserdese2_CLKDIV_RST)
                                                     -0.745     8.071    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_ba2_i/oserdes_i/oserdes_i
  -------------------------------------------------------------------
                         required time                          8.071    
                         arrival time                          -7.889    
  -------------------------------------------------------------------
                         slack                                  0.181    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.119ns  (arrival time - required time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[5].dq_i/dq_out_dly_i/fdly_pre_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[5].dq_i/dq_out_dly_i/fdly_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             ddr3_clk_div
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (ddr3_clk_div rise@0.000ns - ddr3_clk_div rise@0.000ns)
  Data Path Delay:        0.163ns  (logic 0.100ns (61.424%)  route 0.063ns (38.576%))
  Logic Levels:           0  
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.739ns
    Source Clock Delay      (SCD):    1.424ns
    Clock Pessimism Removal (CPR):    0.304ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_clk_div rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.580     0.580    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.050     0.630 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           0.433     1.063    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.090     1.153 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.271     1.424    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[5].dq_i/dq_out_dly_i/psincdec_reg
    SLICE_X116Y115       FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[5].dq_i/dq_out_dly_i/fdly_pre_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X116Y115       FDRE (Prop_fdre_C_Q)         0.100     1.524 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[5].dq_i/dq_out_dly_i/fdly_pre_reg[0]/Q
                         net (fo=2, routed)           0.063     1.587    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[5].dq_i/dq_out_dly_i/fdly_pre[0]
    SLICE_X117Y115       FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[5].dq_i/dq_out_dly_i/fdly_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_clk_div rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.796     0.796    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.053     0.849 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           0.490     1.339    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.093     1.432 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.307     1.739    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[5].dq_i/dq_out_dly_i/psincdec_reg
    SLICE_X117Y115       FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[5].dq_i/dq_out_dly_i/fdly_reg[0]/C
                         clock pessimism             -0.304     1.435    
    SLICE_X117Y115       FDRE (Hold_fdre_C_D)         0.033     1.468    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dq_block[5].dq_i/dq_out_dly_i/fdly_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.468    
                         arrival time                           1.587    
  -------------------------------------------------------------------
                         slack                                  0.119    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ddr3_clk_div
Waveform(ns):       { 0.000 2.500 }
Period(ns):         5.000
Sources:            { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     BUFR/I              n/a            2.221         5.000       2.779      BUFR_X1Y9        mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/I
Max Period        n/a     MMCME2_ADV/CLKOUT2  n/a            213.360       5.000       208.360    MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
Low Pulse Width   Slow    MMCME2_ADV/PSCLK    n/a            1.111         2.500       1.389      MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/PSCLK
High Pulse Width  Slow    MMCME2_ADV/PSCLK    n/a            1.111         2.500       1.389      MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/PSCLK



---------------------------------------------------------------------------------------------------
From Clock:  ddr3_clk_ref
  To Clock:  ddr3_clk_ref

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.264ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ddr3_clk_ref
Waveform(ns):       { 0.000 2.500 }
Period(ns):         5.000
Sources:            { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT5 }

Check Type  Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     IDELAYCTRL/REFCLK  n/a            3.225         5.000       1.775      IDELAYCTRL_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/idelay_ctrl_i/idelay_ctrl_i/REFCLK
Max Period  n/a     IDELAYCTRL/REFCLK  n/a            5.264         5.000       0.264      IDELAYCTRL_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/idelay_ctrl_i/idelay_ctrl_i/REFCLK



---------------------------------------------------------------------------------------------------
From Clock:  ddr3_mclk
  To Clock:  ddr3_mclk

Setup :            0  Failing Endpoints,  Worst Slack        0.285ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.031ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        1.389ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.285ns  (required time - arrival time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i/CLKARDCLK
                            (rising edge-triggered cell RAMB36E1 clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i/ENARDEN
                            (rising edge-triggered cell RAMB36E1 clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Path Group:             ddr3_mclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (ddr3_mclk rise@6.250ns - ddr3_mclk rise@1.250ns)
  Data Path Delay:        4.224ns  (logic 1.013ns (23.982%)  route 3.211ns (76.018%))
  Logic Levels:           5  (LUT4=1 LUT5=2 LUT6=2)
  Clock Path Skew:        -0.031ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.527ns = ( 10.777 - 6.250 ) 
    Source Clock Delay      (SCD):    4.887ns = ( 6.137 - 1.250 ) 
    Clock Pessimism Removal (CPR):    0.329ns
  Clock Uncertainty:      0.085ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     2.825    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.088     2.913 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.628     4.541    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.120     4.661 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=33322, routed)       1.476     6.137    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/CLK
    RAMB36_X6Y23         RAMB36E1                                     r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X6Y23         RAMB36E1 (Prop_ramb36e1_CLKARDCLK_DOADO[22])
                                                      0.748     6.885 f  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i/DOADO[22]
                         net (fo=1, routed)           0.750     7.635    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/phy_cmd0_word[22]
    SLICE_X102Y111       LUT4 (Prop_lut4_I0_O)        0.053     7.688 f  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/phy_addr_prev[5]_i_1/O
                         net (fo=3, routed)           0.418     8.106    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/phy_addr_prev_reg[14][17]
    SLICE_X103Y113       LUT5 (Prop_lut5_I4_O)        0.053     8.159 f  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/pause_cntr[5]_i_2/O
                         net (fo=2, routed)           0.710     8.868    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/pause_len[5]
    SLICE_X97Y113        LUT6 (Prop_lut6_I5_O)        0.053     8.921 f  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i_i_4/O
                         net (fo=2, routed)           0.314     9.235    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i_i_4_n_0
    SLICE_X98Y113        LUT6 (Prop_lut6_I1_O)        0.053     9.288 f  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i_i_2/O
                         net (fo=3, routed)           0.295     9.583    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i_i_2_n_0
    SLICE_X99Y113        LUT5 (Prop_lut5_I1_O)        0.053     9.636 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i_i_1__0/O
                         net (fo=2, routed)           0.724    10.360    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/ren1
    RAMB36_X6Y24         RAMB36E1                                     r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i/ENARDEN
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_mclk rise edge)
                                                      6.250     6.250 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     6.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     7.687    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.083     7.770 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.544     9.314    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.113     9.427 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=33322, routed)       1.350    10.777    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/CLK
    RAMB36_X6Y24         RAMB36E1                                     r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i/CLKARDCLK
                         clock pessimism              0.329    11.106    
                         clock uncertainty           -0.085    11.020    
    RAMB36_X6Y24         RAMB36E1 (Setup_ramb36e1_CLKARDCLK_ENARDEN)
                                                     -0.375    10.645    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i
  -------------------------------------------------------------------
                         required time                         10.645    
                         arrival time                         -10.360    
  -------------------------------------------------------------------
                         slack                                  0.285    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.031ns  (arrival time - required time)
  Source:                 mcntrl393_i/sens_comp_block[3].mcntrl_linear_wr_sensor_i/frame_x_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Destination:            mcntrl393_i/sens_comp_block[3].mcntrl_linear_wr_sensor_i/mem_page_left_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Path Group:             ddr3_mclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (ddr3_mclk rise@1.250ns - ddr3_mclk rise@1.250ns)
  Data Path Delay:        0.311ns  (logic 0.178ns (57.154%)  route 0.133ns (42.846%))
  Logic Levels:           2  (CARRY4=1 LUT2=1)
  Clock Path Skew:        0.188ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.238ns = ( 3.488 - 1.250 ) 
    Source Clock Delay      (SCD):    1.763ns = ( 3.013 - 1.250 ) 
    Clock Pessimism Removal (CPR):    0.287ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.580     1.830    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.050     1.880 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.559     2.439    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.465 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=33322, routed)       0.548     3.013    mcntrl393_i/sens_comp_block[3].mcntrl_linear_wr_sensor_i/clk
    SLICE_X69Y99         FDRE                                         r  mcntrl393_i/sens_comp_block[3].mcntrl_linear_wr_sensor_i/frame_x_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y99         FDRE (Prop_fdre_C_Q)         0.100     3.113 r  mcntrl393_i/sens_comp_block[3].mcntrl_linear_wr_sensor_i/frame_x_reg[4]/Q
                         net (fo=2, routed)           0.133     3.246    mcntrl393_i/sens_comp_block[3].mcntrl_linear_wr_sensor_i/frame_x[4]
    SLICE_X66Y100        LUT2 (Prop_lut2_I1_O)        0.028     3.274 r  mcntrl393_i/sens_comp_block[3].mcntrl_linear_wr_sensor_i/mem_page_left[7]_i_4__2/O
                         net (fo=1, routed)           0.000     3.274    mcntrl393_i/sens_comp_block[3].mcntrl_linear_wr_sensor_i/mem_page_left[7]_i_4__2_n_0
    SLICE_X66Y100        CARRY4 (Prop_carry4_S[0]_O[0])
                                                      0.050     3.324 r  mcntrl393_i/sens_comp_block[3].mcntrl_linear_wr_sensor_i/mem_page_left_reg[7]_i_1__2/O[0]
                         net (fo=1, routed)           0.000     3.324    mcntrl393_i/sens_comp_block[3].mcntrl_linear_wr_sensor_i/mem_page_left0[4]
    SLICE_X66Y100        FDRE                                         r  mcntrl393_i/sens_comp_block[3].mcntrl_linear_wr_sensor_i/mem_page_left_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.796     2.046    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.053     2.099 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.623     2.722    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.030     2.752 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=33322, routed)       0.736     3.488    mcntrl393_i/sens_comp_block[3].mcntrl_linear_wr_sensor_i/clk
    SLICE_X66Y100        FDRE                                         r  mcntrl393_i/sens_comp_block[3].mcntrl_linear_wr_sensor_i/mem_page_left_reg[4]/C
                         clock pessimism             -0.287     3.201    
    SLICE_X66Y100        FDRE (Hold_fdre_C_D)         0.092     3.293    mcntrl393_i/sens_comp_block[3].mcntrl_linear_wr_sensor_i/mem_page_left_reg[4]
  -------------------------------------------------------------------
                         required time                         -3.293    
                         arrival time                           3.324    
  -------------------------------------------------------------------
                         slack                                  0.031    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ddr3_mclk
Waveform(ns):       { 1.250 3.750 }
Period(ns):         5.000
Sources:            { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     RAMB36E1/CLKBWRCLK  n/a            2.495         5.000       2.505      RAMB36_X1Y9      sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/sens_hist_ram_snglclk_32_i/ramt_var_w_var_r_even_i/RAMB36E1_i/CLKBWRCLK
Max Period        n/a     MMCME2_ADV/CLKOUT3  n/a            213.360       5.000       208.360    MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
Low Pulse Width   Slow    MMCME2_ADV/PSCLK    n/a            1.111         2.500       1.389      MMCME2_ADV_X1Y3  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/PSCLK
High Pulse Width  Slow    MMCME2_ADV/PSCLK    n/a            1.111         2.500       1.389      MMCME2_ADV_X0Y1  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/PSCLK



---------------------------------------------------------------------------------------------------
From Clock:  ddr3_sdclk
  To Clock:  ddr3_sdclk

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        1.092ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ddr3_sdclk
Waveform(ns):       { 0.000 1.250 }
Period(ns):         2.500
Sources:            { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0 }

Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     BUFIO/I             n/a            1.408         2.500       1.092      BUFIO_X1Y9       mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/iclk_bufio_i/I
Max Period  n/a     MMCME2_ADV/CLKOUT0  n/a            213.360       2.500       210.860    MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0



---------------------------------------------------------------------------------------------------
From Clock:  multi_clkfb
  To Clock:  multi_clkfb

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack       18.751ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         multi_clkfb
Waveform(ns):       { 0.000 10.000 }
Period(ns):         20.000
Sources:            { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT }

Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period  n/a     PLLE2_ADV/CLKFBOUT  n/a            1.249         20.000      18.751     PLLE2_ADV_X1Y3  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT
Max Period  n/a     PLLE2_ADV/CLKFBIN   n/a            52.633        20.000      32.633     PLLE2_ADV_X1Y3  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKFBIN



---------------------------------------------------------------------------------------------------
From Clock:  sclk
  To Clock:  sclk

Setup :            0  Failing Endpoints,  Worst Slack        4.027ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.044ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        4.090ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             4.027ns  (required time - arrival time)
  Source:                 event_logger_i/i_imu_spi/sngl_wire_stb_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            event_logger_i/i_imu_spi/sngl_wire_r_reg[1]/D
                            (falling edge-triggered cell FDRE clocked by sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             sclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (sclk fall@5.000ns - sclk rise@0.000ns)
  Data Path Delay:        0.834ns  (logic 0.269ns (32.242%)  route 0.565ns (67.758%))
  Logic Levels:           0  
  Clock Path Skew:        -0.031ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.008ns = ( 10.008 - 5.000 ) 
    Source Clock Delay      (SCD):    5.495ns
    Clock Pessimism Removal (CPR):    0.456ns
  Clock Uncertainty:      0.075ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.133ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.784     1.784    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X1Y3       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.088     1.872 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.868     3.740    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y22       BUFG (Prop_bufg_I_O)         0.120     3.860 r  clocks393_i/sync_clk_i/clk1x_i/O
                         net (fo=1443, routed)        1.635     5.495    event_logger_i/i_imu_spi/camsync_clk
    SLICE_X103Y153       FDRE                                         r  event_logger_i/i_imu_spi/sngl_wire_stb_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y153       FDRE (Prop_fdre_C_Q)         0.269     5.764 r  event_logger_i/i_imu_spi/sngl_wire_stb_reg[0]/Q
                         net (fo=2, routed)           0.565     6.329    event_logger_i/i_imu_spi/sngl_wire_stb_reg_n_0_[0]
    SLICE_X101Y156       FDRE                                         r  event_logger_i/i_imu_spi/sngl_wire_r_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock sclk fall edge)       5.000     5.000 f  
    BUFGCTRL_X0Y23       BUFG                         0.000     5.000 f  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.593     6.593    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X1Y3       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.083     6.676 f  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.754     8.430    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y22       BUFG (Prop_bufg_I_O)         0.113     8.543 f  clocks393_i/sync_clk_i/clk1x_i/O
                         net (fo=1443, routed)        1.465    10.008    event_logger_i/i_imu_spi/camsync_clk
    SLICE_X101Y156       FDRE                                         r  event_logger_i/i_imu_spi/sngl_wire_r_reg[1]/C  (IS_INVERTED)
                         clock pessimism              0.456    10.464    
                         clock uncertainty           -0.075    10.389    
    SLICE_X101Y156       FDRE (Setup_fdre_C_D)       -0.032    10.357    event_logger_i/i_imu_spi/sngl_wire_r_reg[1]
  -------------------------------------------------------------------
                         required time                         10.357    
                         arrival time                          -6.329    
  -------------------------------------------------------------------
                         slack                                  4.027    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.044ns  (arrival time - required time)
  Source:                 event_logger_i/i_imu_timestamps/ts_data_r_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            event_logger_i/i_imu_timestamps/ts_ram_reg_0_15_0_5/RAMC/I
                            (rising edge-triggered cell RAMD32 clocked by sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             sclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sclk rise@0.000ns - sclk rise@0.000ns)
  Data Path Delay:        0.146ns  (logic 0.091ns (62.374%)  route 0.055ns (37.626%))
  Logic Levels:           0  
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.673ns
    Source Clock Delay      (SCD):    2.134ns
    Clock Pessimism Removal (CPR):    0.528ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.666     0.666    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X1Y3       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.050     0.716 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.774     1.490    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y22       BUFG (Prop_bufg_I_O)         0.026     1.516 r  clocks393_i/sync_clk_i/clk1x_i/O
                         net (fo=1443, routed)        0.618     2.134    event_logger_i/i_imu_timestamps/camsync_clk
    SLICE_X87Y152        FDRE                                         r  event_logger_i/i_imu_timestamps/ts_data_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y152        FDRE (Prop_fdre_C_Q)         0.091     2.225 r  event_logger_i/i_imu_timestamps/ts_data_r_reg[4]/Q
                         net (fo=1, routed)           0.055     2.280    event_logger_i/i_imu_timestamps/ts_ram_reg_0_15_0_5/DIC0
    SLICE_X86Y152        RAMD32                                       r  event_logger_i/i_imu_timestamps/ts_ram_reg_0_15_0_5/RAMC/I
  -------------------------------------------------------------------    -------------------

                         (clock sclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.903     0.903    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X1Y3       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.053     0.956 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.843     1.799    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y22       BUFG (Prop_bufg_I_O)         0.030     1.829 r  clocks393_i/sync_clk_i/clk1x_i/O
                         net (fo=1443, routed)        0.844     2.673    event_logger_i/i_imu_timestamps/ts_ram_reg_0_15_0_5/WCLK
    SLICE_X86Y152        RAMD32                                       r  event_logger_i/i_imu_timestamps/ts_ram_reg_0_15_0_5/RAMC/CLK
                         clock pessimism             -0.528     2.145    
    SLICE_X86Y152        RAMD32 (Hold_ramd32_CLK_I)
                                                      0.091     2.236    event_logger_i/i_imu_timestamps/ts_ram_reg_0_15_0_5/RAMC
  -------------------------------------------------------------------
                         required time                         -2.236    
                         arrival time                           2.280    
  -------------------------------------------------------------------
                         slack                                  0.044    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         sclk
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3 }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     BUFG/I             n/a            1.600         10.000      8.400      BUFGCTRL_X0Y22  clocks393_i/sync_clk_i/clk1x_i/I
Max Period        n/a     PLLE2_ADV/CLKOUT3  n/a            160.000       10.000      150.000    PLLE2_ADV_X1Y3  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
Low Pulse Width   Slow    RAMD32/CLK         n/a            0.910         5.000       4.090      SLICE_X86Y153   event_logger_i/i_imu_timestamps/ts_ram_reg_0_15_6_11/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK         n/a            0.910         5.000       4.090      SLICE_X84Y162   event_logger_i/i_buf_xclk_mclk16/fifo_4x16_ram_reg_0_3_0_5/RAMA/CLK



---------------------------------------------------------------------------------------------------
From Clock:  xclk
  To Clock:  xclk

Setup :            0  Failing Endpoints,  Worst Slack        0.052ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.025ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.875ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.052ns  (required time - arrival time)
  Source:                 compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[1].fifo_same_clock_i/outreg_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/d_out_reg[29]/R
                            (rising edge-triggered cell FDRE clocked by xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             xclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.167ns  (xclk rise@4.167ns - xclk rise@0.000ns)
  Data Path Delay:        3.577ns  (logic 0.651ns (18.200%)  route 2.926ns (81.800%))
  Logic Levels:           5  (LUT2=1 LUT6=4)
  Clock Path Skew:        -0.103ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.009ns = ( 9.176 - 4.167 ) 
    Source Clock Delay      (SCD):    5.441ns
    Clock Pessimism Removal (CPR):    0.329ns
  Clock Uncertainty:      0.067ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.114ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock xclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.784     1.784    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X1Y3       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.088     1.872 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           1.868     3.740    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.120     3.860 r  clocks393_i/xclk_i/clk1x_i/O
                         net (fo=13492, routed)       1.581     5.441    compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[1].fifo_same_clock_i/xclk
    SLICE_X58Y31         FDRE                                         r  compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[1].fifo_same_clock_i/outreg_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y31         FDRE (Prop_fdre_C_Q)         0.282     5.723 r  compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[1].fifo_same_clock_i/outreg_reg[8]/Q
                         net (fo=4, routed)           0.590     6.313    compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[0].fifo_same_clock_i/outreg_reg[8]_4[8]
    SLICE_X59Y33         LUT6 (Prop_lut6_I1_O)        0.157     6.470 r  compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[0].fifo_same_clock_i/i___287_i_1/O
                         net (fo=19, routed)          0.706     7.175    compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[2].fifo_same_clock_i/outreg_reg[8]_1
    SLICE_X56Y34         LUT6 (Prop_lut6_I2_O)        0.053     7.228 r  compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[2].fifo_same_clock_i/outreg[8]_i_4__3/O
                         net (fo=2, routed)           0.467     7.695    compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[3].fifo_same_clock_i/cry_ff_reg_4
    SLICE_X56Y34         LUT6 (Prop_lut6_I1_O)        0.053     7.748 r  compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[3].fifo_same_clock_i/outreg[8]_i_2__8/O
                         net (fo=9, routed)           0.427     8.175    compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[3].fifo_same_clock_i/bytes_out0
    SLICE_X57Y34         LUT6 (Prop_lut6_I0_O)        0.053     8.228 r  compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[3].fifo_same_clock_i/d_out[23]_i_1/O
                         net (fo=35, routed)          0.237     8.465    compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/E[0]
    SLICE_X57Y34         LUT2 (Prop_lut2_I1_O)        0.053     8.518 r  compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/d_out[31]_i_1/O
                         net (fo=8, routed)           0.500     9.018    compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/d_out[31]_i_1_n_0
    SLICE_X56Y34         FDRE                                         r  compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/d_out_reg[29]/R
  -------------------------------------------------------------------    -------------------

                         (clock xclk rise edge)       4.167     4.167 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     4.167 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.593     5.760    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X1Y3       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.083     5.843 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           1.754     7.597    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.113     7.710 r  clocks393_i/xclk_i/clk1x_i/O
                         net (fo=13492, routed)       1.466     9.176    compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/xclk
    SLICE_X56Y34         FDRE                                         r  compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/d_out_reg[29]/C
                         clock pessimism              0.329     9.505    
                         clock uncertainty           -0.067     9.437    
    SLICE_X56Y34         FDRE (Setup_fdre_C_R)       -0.367     9.070    compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/d_out_reg[29]
  -------------------------------------------------------------------
                         required time                          9.070    
                         arrival time                          -9.018    
  -------------------------------------------------------------------
                         slack                                  0.052    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.025ns  (arrival time - required time)
  Source:                 compressor393_i/cmprs_channel_block[1].jp_channel_i/encoderDCAC393_i/dc_diff0_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            compressor393_i/cmprs_channel_block[1].jp_channel_i/encoderDCAC393_i/dc_diff_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             xclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (xclk rise@0.000ns - xclk rise@0.000ns)
  Data Path Delay:        0.361ns  (logic 0.195ns (53.985%)  route 0.166ns (46.015%))
  Logic Levels:           2  (CARRY4=1 LUT2=1)
  Clock Path Skew:        0.265ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.685ns
    Source Clock Delay      (SCD):    2.099ns
    Clock Pessimism Removal (CPR):    0.321ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock xclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.666     0.666    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X1Y3       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.050     0.716 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           0.774     1.490    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     1.516 r  clocks393_i/xclk_i/clk1x_i/O
                         net (fo=13492, routed)       0.583     2.099    compressor393_i/cmprs_channel_block[1].jp_channel_i/encoderDCAC393_i/xclk
    SLICE_X96Y50         FDRE                                         r  compressor393_i/cmprs_channel_block[1].jp_channel_i/encoderDCAC393_i/dc_diff0_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y50         FDRE (Prop_fdre_C_Q)         0.118     2.217 r  compressor393_i/cmprs_channel_block[1].jp_channel_i/encoderDCAC393_i/dc_diff0_reg[1]/Q
                         net (fo=3, routed)           0.166     2.383    compressor393_i/cmprs_channel_block[1].jp_channel_i/encoderDCAC393_i/dc_diff0[1]
    SLICE_X97Y49         LUT2 (Prop_lut2_I1_O)        0.028     2.411 r  compressor393_i/cmprs_channel_block[1].jp_channel_i/encoderDCAC393_i/dc_diff[3]_i_4/O
                         net (fo=1, routed)           0.000     2.411    compressor393_i/cmprs_channel_block[1].jp_channel_i/encoderDCAC393_i/dc_diff[3]_i_4_n_0
    SLICE_X97Y49         CARRY4 (Prop_carry4_S[1]_O[1])
                                                      0.049     2.460 r  compressor393_i/cmprs_channel_block[1].jp_channel_i/encoderDCAC393_i/dc_diff_reg[3]_i_1__0/O[1]
                         net (fo=1, routed)           0.000     2.460    compressor393_i/cmprs_channel_block[1].jp_channel_i/encoderDCAC393_i/dc_diff00_out[1]
    SLICE_X97Y49         FDRE                                         r  compressor393_i/cmprs_channel_block[1].jp_channel_i/encoderDCAC393_i/dc_diff_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock xclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.903     0.903    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X1Y3       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.053     0.956 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           0.843     1.799    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.030     1.829 r  clocks393_i/xclk_i/clk1x_i/O
                         net (fo=13492, routed)       0.856     2.685    compressor393_i/cmprs_channel_block[1].jp_channel_i/encoderDCAC393_i/xclk
    SLICE_X97Y49         FDRE                                         r  compressor393_i/cmprs_channel_block[1].jp_channel_i/encoderDCAC393_i/dc_diff_reg[1]/C
                         clock pessimism             -0.321     2.364    
    SLICE_X97Y49         FDRE (Hold_fdre_C_D)         0.071     2.435    compressor393_i/cmprs_channel_block[1].jp_channel_i/encoderDCAC393_i/dc_diff_reg[1]
  -------------------------------------------------------------------
                         required time                         -2.435    
                         arrival time                           2.460    
  -------------------------------------------------------------------
                         slack                                  0.025    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         xclk
Waveform(ns):       { 0.000 2.083 }
Period(ns):         4.167
Sources:            { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1 }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     DSP48E1/CLK        n/a            3.292         4.167       0.875      DSP48_X3Y5      compressor393_i/cmprs_channel_block[0].jp_channel_i/focus_sharp393_i/mult_p_r_reg/CLK
Max Period        n/a     PLLE2_ADV/CLKOUT1  n/a            160.000       4.167       155.833    PLLE2_ADV_X1Y3  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
Low Pulse Width   Slow    RAMD32/CLK         n/a            0.910         2.083       1.173      SLICE_X86Y13    compressor393_i/cmprs_channel_block[2].jp_channel_i/dct2d8x8_chen_i/dct1d_chen_reorder_out_i/reord_buf_ram_reg_0_15_0_5/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK         n/a            0.910         2.083       1.173      SLICE_X66Y23    compressor393_i/cmprs_channel_block[3].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[0].fifo_same_clock_i/ram_reg_0_15_6_8/RAMA/CLK



---------------------------------------------------------------------------------------------------
From Clock:  ffclk0
  To Clock:  ffclk0

Setup :            0  Failing Endpoints,  Worst Slack       40.274ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.576ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack       10.833ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             40.274ns  (required time - arrival time)
  Source:                 clocks393_i/test_clk_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by ffclk0  {rise@0.000ns fall@20.833ns period=41.667ns})
  Destination:            clocks393_i/test_clk_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by ffclk0  {rise@0.000ns fall@20.833ns period=41.667ns})
  Path Group:             ffclk0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            41.667ns  (ffclk0 rise@41.667ns - ffclk0 rise@0.000ns)
  Data Path Delay:        1.393ns  (logic 0.322ns (23.122%)  route 1.071ns (76.878%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.000ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.878ns = ( 45.545 - 41.667 ) 
    Source Clock Delay      (SCD):    4.574ns
    Clock Pessimism Removal (CPR):    0.696ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ffclk0 rise edge)     0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.906     0.906 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           3.668     4.574    clocks393_i/ffclk0
    SLICE_X56Y130        FDCE                                         r  clocks393_i/test_clk_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y130        FDCE (Prop_fdce_C_Q)         0.269     4.843 f  clocks393_i/test_clk_reg[1]/Q
                         net (fo=4, routed)           1.071     5.914    clocks393_i/test_clk_reg
    SLICE_X56Y130        LUT1 (Prop_lut1_I0_O)        0.053     5.967 r  clocks393_i/test_clk[1]_i_1/O
                         net (fo=1, routed)           0.000     5.967    clocks393_i/test_clk[1]_i_1_n_0
    SLICE_X56Y130        FDCE                                         r  clocks393_i/test_clk_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock ffclk0 rise edge)    41.667    41.667 r  
    Y12                                               0.000    41.667 r  ffclk0p (IN)
                         net (fo=0)                   0.000    41.667    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.827    42.494 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           3.051    45.545    clocks393_i/ffclk0
    SLICE_X56Y130        FDCE                                         r  clocks393_i/test_clk_reg[1]/C
                         clock pessimism              0.696    46.241    
                         clock uncertainty           -0.035    46.206    
    SLICE_X56Y130        FDCE (Setup_fdce_C_D)        0.035    46.241    clocks393_i/test_clk_reg[1]
  -------------------------------------------------------------------
                         required time                         46.241    
                         arrival time                          -5.967    
  -------------------------------------------------------------------
                         slack                                 40.274    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.576ns  (arrival time - required time)
  Source:                 clocks393_i/test_clk_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by ffclk0  {rise@0.000ns fall@20.833ns period=41.667ns})
  Destination:            clocks393_i/test_clk_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by ffclk0  {rise@0.000ns fall@20.833ns period=41.667ns})
  Path Group:             ffclk0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (ffclk0 rise@0.000ns - ffclk0 rise@0.000ns)
  Data Path Delay:        0.636ns  (logic 0.128ns (20.139%)  route 0.508ns (79.861%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.552ns
    Source Clock Delay      (SCD):    2.142ns
    Clock Pessimism Removal (CPR):    0.410ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ffclk0 rise edge)     0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.446     0.446 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           1.696     2.142    clocks393_i/ffclk0
    SLICE_X56Y130        FDCE                                         r  clocks393_i/test_clk_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y130        FDCE (Prop_fdce_C_Q)         0.100     2.242 f  clocks393_i/test_clk_reg[1]/Q
                         net (fo=4, routed)           0.508     2.750    clocks393_i/test_clk_reg
    SLICE_X56Y130        LUT1 (Prop_lut1_I0_O)        0.028     2.778 r  clocks393_i/test_clk[1]_i_1/O
                         net (fo=1, routed)           0.000     2.778    clocks393_i/test_clk[1]_i_1_n_0
    SLICE_X56Y130        FDCE                                         r  clocks393_i/test_clk_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock ffclk0 rise edge)     0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.521     0.521 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           2.031     2.552    clocks393_i/ffclk0
    SLICE_X56Y130        FDCE                                         r  clocks393_i/test_clk_reg[1]/C
                         clock pessimism             -0.410     2.142    
    SLICE_X56Y130        FDCE (Hold_fdce_C_D)         0.060     2.202    clocks393_i/test_clk_reg[1]
  -------------------------------------------------------------------
                         required time                         -2.202    
                         arrival time                           2.778    
  -------------------------------------------------------------------
                         slack                                  0.576    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ffclk0
Waveform(ns):       { 0.000 20.833 }
Period(ns):         41.667
Sources:            { ffclk0p }

Check Type        Corner  Lib Pin           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     PLLE2_ADV/CLKIN1  n/a            1.249         41.667      40.418     PLLE2_ADV_X0Y0  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKIN1
Max Period        n/a     PLLE2_ADV/CLKIN1  n/a            52.633        41.667      10.966     PLLE2_ADV_X0Y0  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKIN1
Low Pulse Width   Slow    PLLE2_ADV/CLKIN1  n/a            10.000        20.833      10.833     PLLE2_ADV_X0Y0  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKIN1
High Pulse Width  Slow    PLLE2_ADV/CLKIN1  n/a            10.000        20.833      10.833     PLLE2_ADV_X0Y0  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKIN1



---------------------------------------------------------------------------------------------------
From Clock:  clkfb
  To Clock:  clkfb

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack       10.966ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clkfb
Waveform(ns):       { 0.000 20.833 }
Period(ns):         41.667
Sources:            { clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT }

Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period  n/a     PLLE2_ADV/CLKFBOUT  n/a            1.249         41.667      40.418     PLLE2_ADV_X0Y0  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT
Max Period  n/a     PLLE2_ADV/CLKFBIN   n/a            52.633        41.667      10.966     PLLE2_ADV_X0Y0  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKFBIN



---------------------------------------------------------------------------------------------------
From Clock:  pclk
  To Clock:  pclk

Setup :            0  Failing Endpoints,  Worst Slack        0.814ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.037ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.208ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.814ns  (required time - arrival time)
  Source:                 sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by pclk  {rise@0.000ns fall@5.208ns period=10.417ns})
  Destination:            sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/dclk_i/ODDR_i/R
                            (falling edge-triggered cell ODDR clocked by pclk  {rise@0.000ns fall@5.208ns period=10.417ns})
  Path Group:             pclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.208ns  (pclk fall@5.208ns - pclk rise@0.000ns)
  Data Path Delay:        3.701ns  (logic 0.246ns (6.647%)  route 3.455ns (93.353%))
  Logic Levels:           0  
  Clock Path Skew:        0.230ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.778ns = ( 10.986 - 5.208 ) 
    Source Clock Delay      (SCD):    5.830ns
    Clock Pessimism Removal (CPR):    0.282ns
  Clock Uncertainty:      0.119ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.227ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock pclk rise edge)       0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.906     0.906 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           1.253     2.159    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.088     2.247 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           2.009     4.256    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.120     4.376 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        1.454     5.830    sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/CLK
    SLICE_X28Y98         FDRE                                         r  sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X28Y98         FDRE (Prop_fdre_C_Q)         0.246     6.076 r  sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q
                         net (fo=26, routed)          3.455     9.531    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/dclk_i/rst[0]
    OLOGIC_X0Y4          ODDR                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/dclk_i/ODDR_i/R
  -------------------------------------------------------------------    -------------------

                         (clock pclk fall edge)       5.208     5.208 f  
    Y12                                               0.000     5.208 f  ffclk0p (IN)
                         net (fo=0)                   0.000     5.208    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.827     6.035 f  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           1.170     7.205    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.083     7.288 f  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.911     9.199    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.113     9.312 f  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        1.674    10.986    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/dclk_i/clk1x
    OLOGIC_X0Y4          ODDR                                         f  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/dclk_i/ODDR_i/C
                         clock pessimism              0.282    11.268    
                         clock uncertainty           -0.119    11.149    
    OLOGIC_X0Y4          ODDR (Setup_oddr_C_R)       -0.805    10.344    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/dclk_i/ODDR_i
  -------------------------------------------------------------------
                         required time                         10.344    
                         arrival time                          -9.531    
  -------------------------------------------------------------------
                         slack                                  0.814    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.037ns  (arrival time - required time)
  Source:                 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/r2_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by pclk  {rise@0.000ns fall@5.208ns period=10.417ns})
  Destination:            sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/r3_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by pclk  {rise@0.000ns fall@5.208ns period=10.417ns})
  Path Group:             pclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (pclk rise@0.000ns - pclk rise@0.000ns)
  Data Path Delay:        0.237ns  (logic 0.118ns (49.801%)  route 0.119ns (50.199%))
  Logic Levels:           0  
  Clock Path Skew:        0.141ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.782ns
    Source Clock Delay      (SCD):    2.431ns
    Clock Pessimism Removal (CPR):    0.210ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock pclk rise edge)       0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.446     0.446 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           0.503     0.949    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.050     0.999 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.771     1.770    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.796 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        0.635     2.431    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/clk1x
    SLICE_X20Y49         FDRE                                         r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/r2_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X20Y49         FDRE (Prop_fdre_C_Q)         0.118     2.549 r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/r2_reg[11]/Q
                         net (fo=4, routed)           0.119     2.667    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/r2[11]
    SLICE_X22Y50         FDRE                                         r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/r3_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock pclk rise edge)       0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.521     0.521 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           0.554     1.075    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.128 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.840     1.968    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.030     1.998 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        0.784     2.782    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/clk1x
    SLICE_X22Y50         FDRE                                         r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/r3_reg[11]/C
                         clock pessimism             -0.210     2.572    
    SLICE_X22Y50         FDRE (Hold_fdre_C_D)         0.059     2.631    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/r3_reg[11]
  -------------------------------------------------------------------
                         required time                         -2.631    
                         arrival time                           2.667    
  -------------------------------------------------------------------
                         slack                                  0.037    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pclk
Waveform(ns):       { 0.000 5.208 }
Period(ns):         10.417
Sources:            { clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     DSP48E1/CLK        n/a            3.124         10.417      7.293      DSP48_X0Y5       sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_gamma_i/table_mult/CLK
Max Period        n/a     MMCME2_ADV/CLKIN1  n/a            100.000       10.417      89.583     MMCME2_ADV_X0Y1  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKIN1
Low Pulse Width   Slow    MMCME2_ADV/CLKIN1  n/a            3.000         5.208       2.208      MMCME2_ADV_X1Y3  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKIN1
High Pulse Width  Slow    MMCME2_ADV/CLKIN1  n/a            3.000         5.208       2.208      MMCME2_ADV_X0Y1  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKIN1



---------------------------------------------------------------------------------------------------
From Clock:  clk_fb_1
  To Clock:  clk_fb_1

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        9.168ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_fb_1
Waveform(ns):       { 0.000 5.208 }
Period(ns):         10.417
Sources:            { sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT }

Check Type  Corner  Lib Pin              Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            1.249         10.417      9.168      MMCME2_ADV_X0Y0  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT
Max Period  n/a     MMCME2_ADV/CLKFBIN   n/a            100.000       10.417      89.583     MMCME2_ADV_X0Y0  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBIN



---------------------------------------------------------------------------------------------------
From Clock:  clk_fb_2
  To Clock:  clk_fb_2

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        9.168ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_fb_2
Waveform(ns):       { 0.000 5.208 }
Period(ns):         10.417
Sources:            { sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT }

Check Type  Corner  Lib Pin              Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            1.249         10.417      9.168      MMCME2_ADV_X1Y1  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT
Max Period  n/a     MMCME2_ADV/CLKFBIN   n/a            100.000       10.417      89.583     MMCME2_ADV_X1Y1  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBIN



---------------------------------------------------------------------------------------------------
From Clock:  clk_fb_3
  To Clock:  clk_fb_3

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        9.168ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_fb_3
Waveform(ns):       { 0.000 5.208 }
Period(ns):         10.417
Sources:            { sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT }

Check Type  Corner  Lib Pin              Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            1.249         10.417      9.168      MMCME2_ADV_X0Y1  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT
Max Period  n/a     MMCME2_ADV/CLKFBIN   n/a            100.000       10.417      89.583     MMCME2_ADV_X0Y1  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBIN



---------------------------------------------------------------------------------------------------
From Clock:  clk_fb_4
  To Clock:  clk_fb_4

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        9.168ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_fb_4
Waveform(ns):       { 0.000 5.208 }
Period(ns):         10.417
Sources:            { sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT }

Check Type  Corner  Lib Pin              Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            1.249         10.417      9.168      MMCME2_ADV_X1Y3  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT
Max Period  n/a     MMCME2_ADV/CLKFBIN   n/a            100.000       10.417      89.583     MMCME2_ADV_X1Y3  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBIN



---------------------------------------------------------------------------------------------------
From Clock:  iclk0
  To Clock:  iclk0

Setup :            0  Failing Endpoints,  Worst Slack        7.148ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.093ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        4.298ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             7.148ns  (required time - arrival time)
  Source:                 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/hact_ext_r_reg/C
                            (rising edge-triggered cell FDRE clocked by iclk0  {rise@0.000ns fall@5.208ns period=10.417ns})
  Destination:            sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/hact_cntr_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by iclk0  {rise@0.000ns fall@5.208ns period=10.417ns})
  Path Group:             iclk0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.417ns  (iclk0 rise@10.417ns - iclk0 rise@0.000ns)
  Data Path Delay:        3.228ns  (logic 0.706ns (21.869%)  route 2.522ns (78.131%))
  Logic Levels:           2  (CARRY4=1 LUT4=1)
  Clock Path Skew:        -0.043ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    7.838ns = ( 18.254 - 10.417 ) 
    Source Clock Delay      (SCD):    8.387ns
    Clock Pessimism Removal (CPR):    0.506ns
  Clock Uncertainty:      0.082ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.147ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock iclk0 rise edge)      0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.906     0.906 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           1.253     2.159    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.088     2.247 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           2.009     4.256    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.120     4.376 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        1.778     6.154    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.088     6.242 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.106     7.348    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFR_X0Y1            BUFR (Prop_bufr_I_O)         0.377     7.725 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         0.662     8.387    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/ipclk
    SLICE_X4Y39          FDRE                                         r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/hact_ext_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X4Y39          FDRE (Prop_fdre_C_Q)         0.282     8.669 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/hact_ext_r_reg/Q
                         net (fo=20, routed)          0.664     9.333    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/pxd_hact_i/hact_ext_r
    SLICE_X5Y37          LUT4 (Prop_lut4_I0_O)        0.157     9.490 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/pxd_hact_i/busy_r_i_2/O
                         net (fo=16, routed)          1.858    11.348    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/pxd_hact_i/DI[0]
    SLICE_X2Y40          CARRY4 (Prop_carry4_DI[2]_O[3])
                                                      0.267    11.615 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/pxd_hact_i/hact_cntr_reg[12]_i_1/O[3]
                         net (fo=1, routed)           0.000    11.615    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/pxd_hact_i_n_18
    SLICE_X2Y40          FDRE                                         r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/hact_cntr_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock iclk0 rise edge)     10.417    10.417 r  
    Y12                                               0.000    10.417 r  ffclk0p (IN)
                         net (fo=0)                   0.000    10.417    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.827    11.243 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           1.170    12.413    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.083    12.496 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.911    14.407    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.113    14.520 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        1.646    16.166    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.083    16.249 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.016    17.265    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFR_X0Y1            BUFR (Prop_bufr_I_O)         0.370    17.635 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         0.619    18.254    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/ipclk
    SLICE_X2Y40          FDRE                                         r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/hact_cntr_reg[15]/C
                         clock pessimism              0.506    18.760    
                         clock uncertainty           -0.082    18.679    
    SLICE_X2Y40          FDRE (Setup_fdre_C_D)        0.084    18.763    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/hact_cntr_reg[15]
  -------------------------------------------------------------------
                         required time                         18.763    
                         arrival time                         -11.615    
  -------------------------------------------------------------------
                         slack                                  7.148    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.093ns  (arrival time - required time)
  Source:                 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/pxd_out_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by iclk0  {rise@0.000ns fall@5.208ns period=10.417ns})
  Destination:            sensors393_i/sensor_channel_block[0].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_0_5/RAMA/I
                            (rising edge-triggered cell RAMD32 clocked by iclk0  {rise@0.000ns fall@5.208ns period=10.417ns})
  Path Group:             iclk0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (iclk0 rise@0.000ns - iclk0 rise@0.000ns)
  Data Path Delay:        0.263ns  (logic 0.100ns (37.952%)  route 0.163ns (62.048%))
  Logic Levels:           0  
  Clock Path Skew:        0.039ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.845ns
    Source Clock Delay      (SCD):    3.310ns
    Clock Pessimism Removal (CPR):    0.496ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock iclk0 rise edge)      0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.446     0.446 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           0.503     0.949    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.050     0.999 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.771     1.770    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.796 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        0.649     2.445    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     2.495 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.433     2.928    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFR_X0Y1            BUFR (Prop_bufr_I_O)         0.090     3.018 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         0.292     3.310    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/ipclk
    SLICE_X9Y28          FDRE                                         r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/pxd_out_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y28          FDRE (Prop_fdre_C_Q)         0.100     3.410 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/pxd_out_reg[0]/Q
                         net (fo=2, routed)           0.163     3.573    sensors393_i/sensor_channel_block[0].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_0_5/DIA0
    SLICE_X10Y28         RAMD32                                       r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_0_5/RAMA/I
  -------------------------------------------------------------------    -------------------

                         (clock iclk0 rise edge)      0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.521     0.521 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           0.554     1.075    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.128 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.840     1.968    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.030     1.998 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        0.880     2.878    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.053     2.931 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.490     3.421    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFR_X0Y1            BUFR (Prop_bufr_I_O)         0.093     3.514 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         0.331     3.845    sensors393_i/sensor_channel_block[0].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_0_5/WCLK
    SLICE_X10Y28         RAMD32                                       r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_0_5/RAMA/CLK
                         clock pessimism             -0.496     3.349    
    SLICE_X10Y28         RAMD32 (Hold_ramd32_CLK_I)
                                                      0.131     3.480    sensors393_i/sensor_channel_block[0].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_0_5/RAMA
  -------------------------------------------------------------------
                         required time                         -3.480    
                         arrival time                           3.573    
  -------------------------------------------------------------------
                         slack                                  0.093    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         iclk0
Waveform(ns):       { 0.000 5.208 }
Period(ns):         10.417
Sources:            { sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     BUFR/I              n/a            2.221         10.417      8.196      BUFR_X0Y1        sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/clk1x_i/I
Max Period        n/a     MMCME2_ADV/CLKOUT0  n/a            213.360       10.417      202.943    MMCME2_ADV_X0Y0  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.910         5.208       4.298      SLICE_X12Y28     sensors393_i/sensor_channel_block[0].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_12_14/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.910         5.208       4.298      SLICE_X10Y28     sensors393_i/sensor_channel_block[0].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_0_5/RAMA/CLK



---------------------------------------------------------------------------------------------------
From Clock:  iclk1
  To Clock:  iclk1

Setup :            0  Failing Endpoints,  Worst Slack        7.332ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.125ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        4.298ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             7.332ns  (required time - arrival time)
  Source:                 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by iclk1  {rise@0.000ns fall@5.208ns period=10.417ns})
  Destination:            sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/hact_cntr_reg[0]/R
                            (rising edge-triggered cell FDRE clocked by iclk1  {rise@0.000ns fall@5.208ns period=10.417ns})
  Path Group:             iclk1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.417ns  (iclk1 rise@10.417ns - iclk1 rise@0.000ns)
  Data Path Delay:        2.629ns  (logic 0.269ns (10.233%)  route 2.360ns (89.767%))
  Logic Levels:           0  
  Clock Path Skew:        -0.030ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    8.887ns = ( 19.303 - 10.417 ) 
    Source Clock Delay      (SCD):    9.505ns
    Clock Pessimism Removal (CPR):    0.588ns
  Clock Uncertainty:      0.082ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.147ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock iclk1 rise edge)      0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.906     0.906 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           1.253     2.159    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.088     2.247 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           2.009     4.256    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.120     4.376 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        1.581     5.957    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.088     6.045 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.628     7.673    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.120     7.793 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         1.712     9.505    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/ipclk
    SLICE_X1Y12          FDRE                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X1Y12          FDRE (Prop_fdre_C_Q)         0.269     9.774 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/Q
                         net (fo=99, routed)          2.360    12.134    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/Q[0]
    SLICE_X2Y22          FDRE                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/hact_cntr_reg[0]/R
  -------------------------------------------------------------------    -------------------

                         (clock iclk1 rise edge)     10.417    10.417 r  
    Y12                                               0.000    10.417 r  ffclk0p (IN)
                         net (fo=0)                   0.000    10.417    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.827    11.243 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           1.170    12.413    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.083    12.496 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.911    14.407    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.113    14.520 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        1.450    15.970    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.083    16.053 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.544    17.597    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.113    17.710 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         1.593    19.303    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/ipclk
    SLICE_X2Y22          FDRE                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/hact_cntr_reg[0]/C
                         clock pessimism              0.588    19.892    
                         clock uncertainty           -0.082    19.810    
    SLICE_X2Y22          FDRE (Setup_fdre_C_R)       -0.344    19.466    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/hact_cntr_reg[0]
  -------------------------------------------------------------------
                         required time                         19.466    
                         arrival time                         -12.134    
  -------------------------------------------------------------------
                         slack                                  7.332    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.125ns  (arrival time - required time)
  Source:                 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/line_width_m1_ipclk_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by iclk1  {rise@0.000ns fall@5.208ns period=10.417ns})
  Destination:            sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/hact_cntr_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by iclk1  {rise@0.000ns fall@5.208ns period=10.417ns})
  Path Group:             iclk1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (iclk1 rise@0.000ns - iclk1 rise@0.000ns)
  Data Path Delay:        0.228ns  (logic 0.174ns (76.222%)  route 0.054ns (23.779%))
  Logic Levels:           2  (CARRY4=1 LUT6=1)
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.385ns
    Source Clock Delay      (SCD):    3.682ns
    Clock Pessimism Removal (CPR):    0.692ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock iclk1 rise edge)      0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.446     0.446 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           0.503     0.949    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.050     0.999 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.771     1.770    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.796 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        0.596     2.392    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     2.442 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.559     3.001    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.026     3.027 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         0.655     3.682    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/ipclk
    SLICE_X3Y24          FDRE                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/line_width_m1_ipclk_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X3Y24          FDRE (Prop_fdre_C_Q)         0.100     3.782 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/line_width_m1_ipclk_reg[11]/Q
                         net (fo=1, routed)           0.054     3.836    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/pxd_hact_i/line_width_m1_ipclk_reg[15][11]
    SLICE_X2Y24          LUT6 (Prop_lut6_I0_O)        0.028     3.864 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/pxd_hact_i/hact_cntr[8]_i_2__0/O
                         net (fo=1, routed)           0.000     3.864    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/pxd_hact_i/hact_cntr[8]_i_2__0_n_0
    SLICE_X2Y24          CARRY4 (Prop_carry4_S[3]_O[3])
                                                      0.046     3.910 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/pxd_hact_i/hact_cntr_reg[8]_i_1__1/O[3]
                         net (fo=1, routed)           0.000     3.910    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/pxd_hact_i_n_14
    SLICE_X2Y24          FDRE                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/hact_cntr_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock iclk1 rise edge)      0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.521     0.521 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           0.554     1.075    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.128 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.840     1.968    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.030     1.998 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        0.807     2.805    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.053     2.858 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.623     3.481    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.030     3.511 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         0.874     4.385    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/ipclk
    SLICE_X2Y24          FDRE                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/hact_cntr_reg[11]/C
                         clock pessimism             -0.692     3.693    
    SLICE_X2Y24          FDRE (Hold_fdre_C_D)         0.092     3.785    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/hact_cntr_reg[11]
  -------------------------------------------------------------------
                         required time                         -3.785    
                         arrival time                           3.910    
  -------------------------------------------------------------------
                         slack                                  0.125    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         iclk1
Waveform(ns):       { 0.000 5.208 }
Period(ns):         10.417
Sources:            { sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     BUFG/I              n/a            1.600         10.417      8.817      BUFGCTRL_X0Y2    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/clk1x_i/I
Max Period        n/a     MMCME2_ADV/CLKOUT0  n/a            213.360       10.417      202.943    MMCME2_ADV_X1Y1  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.910         5.208       4.298      SLICE_X6Y8       sensors393_i/sensor_channel_block[1].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_0_5/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.910         5.208       4.298      SLICE_X10Y7      sensors393_i/sensor_channel_block[1].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_12_14/RAMA/CLK



---------------------------------------------------------------------------------------------------
From Clock:  iclk2
  To Clock:  iclk2

Setup :            0  Failing Endpoints,  Worst Slack        7.270ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.112ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        4.298ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             7.270ns  (required time - arrival time)
  Source:                 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/hact_r_reg/C
                            (rising edge-triggered cell FDRE clocked by iclk2  {rise@0.000ns fall@5.208ns period=10.417ns})
  Destination:            sensors393_i/sensor_channel_block[2].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_0_5/RAMA/WE
                            (rising edge-triggered cell RAMD32 clocked by iclk2  {rise@0.000ns fall@5.208ns period=10.417ns})
  Path Group:             iclk2
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.417ns  (iclk2 rise@10.417ns - iclk2 rise@0.000ns)
  Data Path Delay:        2.655ns  (logic 0.361ns (13.596%)  route 2.294ns (86.404%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.041ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    7.639ns = ( 18.055 - 10.417 ) 
    Source Clock Delay      (SCD):    8.184ns
    Clock Pessimism Removal (CPR):    0.504ns
  Clock Uncertainty:      0.082ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.147ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock iclk2 rise edge)      0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.906     0.906 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           1.253     2.159    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.088     2.247 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           2.009     4.256    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.120     4.376 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        1.582     5.958    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.088     6.046 r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.106     7.152    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFR_X0Y5            BUFR (Prop_bufr_I_O)         0.377     7.529 r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         0.655     8.184    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/ipclk
    SLICE_X6Y82          FDRE                                         r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/hact_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X6Y82          FDRE (Prop_fdre_C_Q)         0.308     8.492 r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/hact_r_reg/Q
                         net (fo=10, routed)          1.562    10.053    sensors393_i/sensor_channel_block[2].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/data_in[12]
    SLICE_X4Y67          LUT4 (Prop_lut4_I3_O)        0.053    10.106 r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_0_5_i_1__27/O
                         net (fo=24, routed)          0.732    10.839    sensors393_i/sensor_channel_block[2].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_0_5/WE
    SLICE_X6Y66          RAMD32                                       r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_0_5/RAMA/WE
  -------------------------------------------------------------------    -------------------

                         (clock iclk2 rise edge)     10.417    10.417 r  
    Y12                                               0.000    10.417 r  ffclk0p (IN)
                         net (fo=0)                   0.000    10.417    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.827    11.243 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           1.170    12.413    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.083    12.496 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.911    14.407    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.113    14.520 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        1.452    15.972    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.083    16.055 r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.016    17.071    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFR_X0Y5            BUFR (Prop_bufr_I_O)         0.370    17.441 r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         0.614    18.055    sensors393_i/sensor_channel_block[2].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_0_5/WCLK
    SLICE_X6Y66          RAMD32                                       r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_0_5/RAMA/CLK
                         clock pessimism              0.504    18.559    
                         clock uncertainty           -0.082    18.478    
    SLICE_X6Y66          RAMD32 (Setup_ramd32_CLK_WE)
                                                     -0.369    18.109    sensors393_i/sensor_channel_block[2].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_0_5/RAMA
  -------------------------------------------------------------------
                         required time                         18.109    
                         arrival time                         -10.839    
  -------------------------------------------------------------------
                         slack                                  7.270    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.112ns  (arrival time - required time)
  Source:                 sensors393_i/sensor_channel_block[2].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/waddr_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by iclk2  {rise@0.000ns fall@5.208ns period=10.417ns})
  Destination:            sensors393_i/sensor_channel_block[2].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_12_14/RAMA/WADR2
                            (rising edge-triggered cell RAMD32 clocked by iclk2  {rise@0.000ns fall@5.208ns period=10.417ns})
  Path Group:             iclk2
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (iclk2 rise@0.000ns - iclk2 rise@0.000ns)
  Data Path Delay:        0.367ns  (logic 0.100ns (27.260%)  route 0.267ns (72.740%))
  Logic Levels:           0  
  Clock Path Skew:        0.014ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.748ns
    Source Clock Delay      (SCD):    3.235ns
    Clock Pessimism Removal (CPR):    0.499ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock iclk2 rise edge)      0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.446     0.446 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           0.503     0.949    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.050     0.999 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.771     1.770    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.796 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        0.597     2.393    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     2.443 r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.433     2.876    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFR_X0Y5            BUFR (Prop_bufr_I_O)         0.090     2.966 r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         0.269     3.235    sensors393_i/sensor_channel_block[2].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ipclk
    SLICE_X5Y68          FDRE                                         r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/waddr_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y68          FDRE (Prop_fdre_C_Q)         0.100     3.335 r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/waddr_reg[2]/Q
                         net (fo=29, routed)          0.267     3.601    sensors393_i/sensor_channel_block[2].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_12_14/ADDRD2
    SLICE_X4Y66          RAMD32                                       r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_12_14/RAMA/WADR2
  -------------------------------------------------------------------    -------------------

                         (clock iclk2 rise edge)      0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.521     0.521 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           0.554     1.075    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.128 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.840     1.968    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.030     1.998 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        0.808     2.806    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.053     2.859 r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.490     3.349    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFR_X0Y5            BUFR (Prop_bufr_I_O)         0.093     3.442 r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         0.306     3.748    sensors393_i/sensor_channel_block[2].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_12_14/WCLK
    SLICE_X4Y66          RAMD32                                       r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_12_14/RAMA/CLK
                         clock pessimism             -0.499     3.249    
    SLICE_X4Y66          RAMD32 (Hold_ramd32_CLK_WADR2)
                                                      0.241     3.490    sensors393_i/sensor_channel_block[2].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_12_14/RAMA
  -------------------------------------------------------------------
                         required time                         -3.490    
                         arrival time                           3.601    
  -------------------------------------------------------------------
                         slack                                  0.112    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         iclk2
Waveform(ns):       { 0.000 5.208 }
Period(ns):         10.417
Sources:            { sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     BUFR/I              n/a            2.221         10.417      8.196      BUFR_X0Y5        sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/clk1x_i/I
Max Period        n/a     MMCME2_ADV/CLKOUT0  n/a            213.360       10.417      202.943    MMCME2_ADV_X0Y1  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.910         5.208       4.298      SLICE_X6Y67      sensors393_i/sensor_channel_block[2].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_6_11/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.910         5.208       4.298      SLICE_X6Y66      sensors393_i/sensor_channel_block[2].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_0_5/RAMA/CLK



---------------------------------------------------------------------------------------------------
From Clock:  iclk2x0
  To Clock:  iclk2x0

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        3.801ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         iclk2x0
Waveform(ns):       { 0.000 2.604 }
Period(ns):         5.208
Sources:            { sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1 }

Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     BUFIO/I             n/a            1.408         5.208       3.801      BUFIO_X0Y1       sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/clk2x_i/I
Max Period  n/a     MMCME2_ADV/CLKOUT1  n/a            213.360       5.208       208.152    MMCME2_ADV_X0Y0  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1



---------------------------------------------------------------------------------------------------
From Clock:  iclk2x1
  To Clock:  iclk2x1

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        3.608ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         iclk2x1
Waveform(ns):       { 0.000 2.604 }
Period(ns):         5.208
Sources:            { sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1 }

Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     BUFG/I              n/a            1.600         5.208       3.608      BUFGCTRL_X0Y4    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/clk2x_i/I
Max Period  n/a     MMCME2_ADV/CLKOUT1  n/a            213.360       5.208       208.152    MMCME2_ADV_X1Y1  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1



---------------------------------------------------------------------------------------------------
From Clock:  iclk2x2
  To Clock:  iclk2x2

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        3.801ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         iclk2x2
Waveform(ns):       { 0.000 2.604 }
Period(ns):         5.208
Sources:            { sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1 }

Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     BUFIO/I             n/a            1.408         5.208       3.801      BUFIO_X0Y5       sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/clk2x_i/I
Max Period  n/a     MMCME2_ADV/CLKOUT1  n/a            213.360       5.208       208.152    MMCME2_ADV_X0Y1  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1



---------------------------------------------------------------------------------------------------
From Clock:  iclk2x3
  To Clock:  iclk2x3

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        3.608ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         iclk2x3
Waveform(ns):       { 0.000 2.604 }
Period(ns):         5.208
Sources:            { sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1 }

Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     BUFG/I              n/a            1.600         5.208       3.608      BUFGCTRL_X0Y19   sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/clk2x_i/I
Max Period  n/a     MMCME2_ADV/CLKOUT1  n/a            213.360       5.208       208.152    MMCME2_ADV_X1Y3  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1



---------------------------------------------------------------------------------------------------
From Clock:  iclk3
  To Clock:  iclk3

Setup :            0  Failing Endpoints,  Worst Slack        6.145ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.069ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        4.298ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             6.145ns  (required time - arrival time)
  Source:                 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by iclk3  {rise@0.000ns fall@5.208ns period=10.417ns})
  Destination:            sensors393_i/sensor_channel_block[3].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/waddr_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by iclk3  {rise@0.000ns fall@5.208ns period=10.417ns})
  Path Group:             iclk3
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.417ns  (iclk3 rise@10.417ns - iclk3 rise@0.000ns)
  Data Path Delay:        3.933ns  (logic 0.492ns (12.511%)  route 3.441ns (87.489%))
  Logic Levels:           2  (LUT5=2)
  Clock Path Skew:        -0.149ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    8.917ns = ( 19.333 - 10.417 ) 
    Source Clock Delay      (SCD):    9.735ns
    Clock Pessimism Removal (CPR):    0.669ns
  Clock Uncertainty:      0.082ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.147ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock iclk3 rise edge)      0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.906     0.906 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           1.253     2.159    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.088     2.247 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           2.009     4.256    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.120     4.376 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        1.759     6.135    sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X1Y3      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.088     6.223 r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.875     8.098    sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.120     8.218 r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         1.517     9.735    sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/ipclk
    SLICE_X6Y62          FDRE                                         r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X6Y62          FDRE (Prop_fdre_C_Q)         0.282    10.017 r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/Q
                         net (fo=99, routed)          2.810    12.827    sensors393_i/sensor_channel_block[3].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/Q[0]
    SLICE_X36Y57         LUT5 (Prop_lut5_I0_O)        0.155    12.982 r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/waddr_gray[0]_i_1__2/O
                         net (fo=7, routed)           0.243    13.225    sensors393_i/sensor_channel_block[3].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/waddr_gray[0]_i_1__2_n_0
    SLICE_X36Y57         LUT5 (Prop_lut5_I3_O)        0.055    13.280 r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/waddr[2]_i_1__2/O
                         net (fo=1, routed)           0.387    13.667    sensors393_i/sensor_channel_block[3].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/waddr[2]_i_1__2_n_0
    SLICE_X36Y57         FDRE                                         r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/waddr_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock iclk3 rise edge)     10.417    10.417 r  
    Y12                                               0.000    10.417 r  ffclk0p (IN)
                         net (fo=0)                   0.000    10.417    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.827    11.243 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           1.170    12.413    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.083    12.496 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.911    14.407    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.113    14.520 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        1.571    16.091    sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X1Y3      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.083    16.174 r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.760    17.934    sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.113    18.047 r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         1.286    19.333    sensors393_i/sensor_channel_block[3].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ipclk
    SLICE_X36Y57         FDRE                                         r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/waddr_reg[2]/C
                         clock pessimism              0.669    20.003    
                         clock uncertainty           -0.082    19.921    
    SLICE_X36Y57         FDRE (Setup_fdre_C_D)       -0.109    19.812    sensors393_i/sensor_channel_block[3].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/waddr_reg[2]
  -------------------------------------------------------------------
                         required time                         19.812    
                         arrival time                         -13.667    
  -------------------------------------------------------------------
                         slack                                  6.145    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.069ns  (arrival time - required time)
  Source:                 sensors393_i/sensor_channel_block[3].sensor_channel_i/sensor_fifo_i/eof_in_reg/C
                            (rising edge-triggered cell FDRE clocked by iclk3  {rise@0.000ns fall@5.208ns period=10.417ns})
  Destination:            sensors393_i/sensor_channel_block[3].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_12_14/RAMB/I
                            (rising edge-triggered cell RAMD32 clocked by iclk3  {rise@0.000ns fall@5.208ns period=10.417ns})
  Path Group:             iclk3
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (iclk3 rise@0.000ns - iclk3 rise@0.000ns)
  Data Path Delay:        0.233ns  (logic 0.100ns (42.896%)  route 0.133ns (57.104%))
  Logic Levels:           0  
  Clock Path Skew:        0.032ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.551ns
    Source Clock Delay      (SCD):    3.839ns
    Clock Pessimism Removal (CPR):    0.680ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock iclk3 rise edge)      0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.446     0.446 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           0.503     0.949    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.050     0.999 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.771     1.770    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.796 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        0.662     2.458    sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X1Y3      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     2.508 r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.756     3.264    sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.026     3.290 r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         0.549     3.839    sensors393_i/sensor_channel_block[3].sensor_channel_i/sensor_fifo_i/ipclk
    SLICE_X35Y58         FDRE                                         r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sensor_fifo_i/eof_in_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y58         FDRE (Prop_fdre_C_Q)         0.100     3.939 r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sensor_fifo_i/eof_in_reg/Q
                         net (fo=4, routed)           0.133     4.072    sensors393_i/sensor_channel_block[3].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_12_14/DIB0
    SLICE_X36Y58         RAMD32                                       r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_12_14/RAMB/I
  -------------------------------------------------------------------    -------------------

                         (clock iclk3 rise edge)      0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.521     0.521 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           0.554     1.075    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.128 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.840     1.968    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.030     1.998 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        0.898     2.896    sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X1Y3      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.053     2.949 r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.823     3.772    sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.030     3.802 r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         0.749     4.551    sensors393_i/sensor_channel_block[3].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_12_14/WCLK
    SLICE_X36Y58         RAMD32                                       r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_12_14/RAMB/CLK
                         clock pessimism             -0.680     3.871    
    SLICE_X36Y58         RAMD32 (Hold_ramd32_CLK_I)
                                                      0.132     4.003    sensors393_i/sensor_channel_block[3].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_12_14/RAMB
  -------------------------------------------------------------------
                         required time                         -4.003    
                         arrival time                           4.072    
  -------------------------------------------------------------------
                         slack                                  0.069    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         iclk3
Waveform(ns):       { 0.000 5.208 }
Period(ns):         10.417
Sources:            { sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     BUFG/I              n/a            1.600         10.417      8.817      BUFGCTRL_X0Y18   sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/clk1x_i/I
Max Period        n/a     MMCME2_ADV/CLKOUT0  n/a            213.360       10.417      202.943    MMCME2_ADV_X1Y3  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.910         5.208       4.298      SLICE_X36Y55     sensors393_i/sensor_channel_block[3].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_0_5/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.910         5.208       4.298      SLICE_X36Y55     sensors393_i/sensor_channel_block[3].sensor_channel_i/sensor_fifo_i/fifo_cross_clocks_i/ram_reg_0_15_0_5/RAMA/CLK



---------------------------------------------------------------------------------------------------
From Clock:  gtrefclk
  To Clock:  gtrefclk

Setup :            0  Failing Endpoints,  Worst Slack        4.481ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.218ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.553ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             4.481ns  (required time - arrival time)
  Source:                 sata_top/ahci_sata_layers_i/phy/rst_timer_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by gtrefclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Destination:            sata_top/ahci_sata_layers_i/phy/rst_timer_reg[0]/CE
                            (rising edge-triggered cell FDRE clocked by gtrefclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Path Group:             gtrefclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (gtrefclk rise@6.666ns - gtrefclk rise@0.000ns)
  Data Path Delay:        1.888ns  (logic 0.375ns (19.867%)  route 1.513ns (80.133%))
  Logic Levels:           2  (LUT3=1 LUT6=1)
  Clock Path Skew:        -0.018ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.441ns = ( 8.107 - 6.666 ) 
    Source Clock Delay      (SCD):    1.565ns
    Clock Pessimism Removal (CPR):    0.106ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock gtrefclk rise edge)
                                                      0.000     0.000 r  
    IBUFDS_GTE2_X0Y0     IBUFDS_GTE2                  0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O
                         net (fo=25, routed)          1.565     1.565    sata_top/ahci_sata_layers_i/phy/gtrefclk
    SLICE_X60Y49         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/rst_timer_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y49         FDRE (Prop_fdre_C_Q)         0.269     1.834 r  sata_top/ahci_sata_layers_i/phy/rst_timer_reg[2]/Q
                         net (fo=5, routed)           0.797     2.632    sata_top/ahci_sata_layers_i/phy/rst_timer_reg__0[2]
    SLICE_X60Y49         LUT6 (Prop_lut6_I1_O)        0.053     2.685 f  sata_top/ahci_sata_layers_i/phy/sata_areset_i_2/O
                         net (fo=4, routed)           0.329     3.014    sata_top/ahci_sata_layers_i/phy/sata_areset_i_2_n_0
    SLICE_X58Y49         LUT3 (Prop_lut3_I2_O)        0.053     3.067 r  sata_top/ahci_sata_layers_i/phy/rst_timer[7]_i_2/O
                         net (fo=8, routed)           0.386     3.453    sata_top/ahci_sata_layers_i/phy/rst_timer[7]_i_2_n_0
    SLICE_X61Y49         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/rst_timer_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock gtrefclk rise edge)
                                                      6.666     6.666 r  
    IBUFDS_GTE2_X0Y0     IBUFDS_GTE2                  0.000     6.666 r  sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O
                         net (fo=25, routed)          1.441     8.107    sata_top/ahci_sata_layers_i/phy/gtrefclk
    SLICE_X61Y49         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/rst_timer_reg[0]/C
                         clock pessimism              0.106     8.213    
                         clock uncertainty           -0.035     8.178    
    SLICE_X61Y49         FDRE (Setup_fdre_C_CE)      -0.244     7.934    sata_top/ahci_sata_layers_i/phy/rst_timer_reg[0]
  -------------------------------------------------------------------
                         required time                          7.934    
                         arrival time                          -3.453    
  -------------------------------------------------------------------
                         slack                                  4.481    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.218ns  (arrival time - required time)
  Source:                 sata_top/ahci_sata_layers_i/phy/cplllock_r_reg/C
                            (rising edge-triggered cell FDRE clocked by gtrefclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Destination:            sata_top/ahci_sata_layers_i/phy/txreset_f_r_reg_srl2/D
                            (rising edge-triggered cell SRL16E clocked by gtrefclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Path Group:             gtrefclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (gtrefclk rise@0.000ns - gtrefclk rise@0.000ns)
  Data Path Delay:        0.331ns  (logic 0.128ns (38.682%)  route 0.203ns (61.318%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.655ns
    Source Clock Delay      (SCD):    0.453ns
    Clock Pessimism Removal (CPR):    0.191ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock gtrefclk rise edge)
                                                      0.000     0.000 r  
    IBUFDS_GTE2_X0Y0     IBUFDS_GTE2                  0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O
                         net (fo=25, routed)          0.453     0.453    sata_top/ahci_sata_layers_i/phy/gtrefclk
    SLICE_X59Y49         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/cplllock_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y49         FDRE (Prop_fdre_C_Q)         0.100     0.553 f  sata_top/ahci_sata_layers_i/phy/cplllock_r_reg/Q
                         net (fo=2, routed)           0.094     0.648    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/cplllock_r
    SLICE_X58Y49         LUT4 (Prop_lut4_I3_O)        0.028     0.676 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/txreset_f_r_reg_srl2_i_1/O
                         net (fo=1, routed)           0.109     0.784    sata_top/ahci_sata_layers_i/phy/p_2_in
    SLICE_X58Y49         SRL16E                                       r  sata_top/ahci_sata_layers_i/phy/txreset_f_r_reg_srl2/D
  -------------------------------------------------------------------    -------------------

                         (clock gtrefclk rise edge)
                                                      0.000     0.000 r  
    IBUFDS_GTE2_X0Y0     IBUFDS_GTE2                  0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O
                         net (fo=25, routed)          0.655     0.655    sata_top/ahci_sata_layers_i/phy/gtrefclk
    SLICE_X58Y49         SRL16E                                       r  sata_top/ahci_sata_layers_i/phy/txreset_f_r_reg_srl2/CLK
                         clock pessimism             -0.191     0.464    
    SLICE_X58Y49         SRL16E (Hold_srl16e_CLK_D)
                                                      0.102     0.566    sata_top/ahci_sata_layers_i/phy/txreset_f_r_reg_srl2
  -------------------------------------------------------------------
                         required time                         -0.566    
                         arrival time                           0.784    
  -------------------------------------------------------------------
                         slack                                  0.218    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         gtrefclk
Waveform(ns):       { 0.000 3.333 }
Period(ns):         6.666
Sources:            { sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O }

Check Type        Corner  Lib Pin                  Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location            Pin
Min Period        n/a     GTXE2_CHANNEL/GTREFCLK0  n/a            1.538         6.666       5.128      GTXE2_CHANNEL_X0Y0  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/GTREFCLK0
Low Pulse Width   Slow    SRL16E/CLK               n/a            0.780         3.333       2.553      SLICE_X62Y48        sata_top/ahci_sata_layers_i/phy/rxreset_f_r_reg_srl2/CLK
High Pulse Width  Slow    SRL16E/CLK               n/a            0.780         3.333       2.553      SLICE_X58Y49        sata_top/ahci_sata_layers_i/phy/txreset_f_r_reg_srl2/CLK



---------------------------------------------------------------------------------------------------
From Clock:  rx_clk
  To Clock:  rx_clk

Setup :            0  Failing Endpoints,  Worst Slack        0.855ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.066ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.423ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.855ns  (required time - arrival time)
  Source:                 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/RAMB36E1_i/CLKARDCLK
                            (rising edge-triggered cell RAMB36E1 clocked by rx_clk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Destination:            sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/wen_reg[0]/CE
                            (rising edge-triggered cell FDRE clocked by rx_clk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Path Group:             rx_clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (rx_clk rise@6.666ns - rx_clk rise@0.000ns)
  Data Path Delay:        5.550ns  (logic 1.248ns (22.487%)  route 4.302ns (77.513%))
  Logic Levels:           7  (LUT3=4 LUT6=3)
  Clock Path Skew:        -0.007ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.815ns = ( 9.481 - 6.666 ) 
    Source Clock Delay      (SCD):    2.888ns
    Clock Pessimism Removal (CPR):    0.066ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock rx_clk rise edge)     0.000     0.000 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK
                         net (fo=1, routed)           1.349     1.349    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/xclk_gtx
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.120     1.469 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/clk1x_i/O
                         net (fo=327, routed)         1.419     2.888    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/CLK
    RAMB36_X3Y27         RAMB36E1                                     r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/RAMB36E1_i/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X3Y27         RAMB36E1 (Prop_ramb36e1_CLKARDCLK_DOADO[8])
                                                      0.748     3.636 f  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/RAMB36E1_i/DOADO[8]
                         net (fo=5, routed)           1.074     4.709    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/p_1_in[2]
    SLICE_X59Y150        LUT6 (Prop_lut6_I3_O)        0.053     4.762 f  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/is_prim_r[15]_i_8/O
                         net (fo=2, routed)           0.138     4.900    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/is_prim_r[15]_i_8_n_0
    SLICE_X59Y150        LUT6 (Prop_lut6_I4_O)        0.053     4.953 f  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/is_prim_r[15]_i_5/O
                         net (fo=7, routed)           0.556     5.509    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/data_in_r_reg[2]
    SLICE_X56Y149        LUT3 (Prop_lut3_I1_O)        0.065     5.574 f  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/is_prim_r[11]_i_3/O
                         net (fo=2, routed)           0.432     6.006    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/RAMB36E1_i_0
    SLICE_X59Y149        LUT6 (Prop_lut6_I5_O)        0.170     6.176 f  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/is_prim_r[16]_i_2/O
                         net (fo=4, routed)           0.521     6.696    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/is_prim_r_reg[16]
    SLICE_X59Y150        LUT3 (Prop_lut3_I2_O)        0.053     6.749 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/prealign_ram_reg_0_15_0_0_i_10/O
                         net (fo=9, routed)           0.475     7.224    sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/RAMB36E1_i_0
    SLICE_X60Y152        LUT3 (Prop_lut3_I1_O)        0.053     7.277 f  sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/msb_in_r_i_1/O
                         net (fo=2, routed)           0.964     8.241    sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/msb_in_r_i_1_n_0
    SLICE_X46Y160        LUT3 (Prop_lut3_I0_O)        0.053     8.294 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/xlnx_opt_LUT_wen_reg[0]_CE_cooolgate_en_gate_1261/O
                         net (fo=6, routed)           0.143     8.437    sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/wen_reg[0]_CE_cooolgate_en_sig_208
    SLICE_X46Y160        FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/wen_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock rx_clk rise edge)     6.666     6.666 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     6.666 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK
                         net (fo=1, routed)           1.300     7.966    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/xclk_gtx
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.113     8.079 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/clk1x_i/O
                         net (fo=327, routed)         1.402     9.481    sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/CLK
    SLICE_X46Y160        FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/wen_reg[0]/C
                         clock pessimism              0.066     9.547    
                         clock uncertainty           -0.035     9.512    
    SLICE_X46Y160        FDRE (Setup_fdre_C_CE)      -0.219     9.293    sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/wen_reg[0]
  -------------------------------------------------------------------
                         required time                          9.293    
                         arrival time                          -8.437    
  -------------------------------------------------------------------
                         slack                                  0.855    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.066ns  (arrival time - required time)
  Source:                 sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/waddr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by rx_clk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Destination:            sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_18_23/RAMA/WADR3
                            (rising edge-triggered cell RAMD32 clocked by rx_clk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Path Group:             rx_clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (rx_clk rise@0.000ns - rx_clk rise@0.000ns)
  Data Path Delay:        0.305ns  (logic 0.100ns (32.734%)  route 0.205ns (67.266%))
  Logic Levels:           0  
  Clock Path Skew:        0.014ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.429ns
    Source Clock Delay      (SCD):    1.162ns
    Clock Pessimism Removal (CPR):    0.253ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock rx_clk rise edge)     0.000     0.000 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK
                         net (fo=1, routed)           0.526     0.526    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/xclk_gtx
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     0.552 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/clk1x_i/O
                         net (fo=327, routed)         0.610     1.162    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/CLK
    SLICE_X63Y151        FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/waddr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y151        FDRE (Prop_fdre_C_Q)         0.100     1.262 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/waddr_reg[3]/Q
                         net (fo=67, routed)          0.205     1.467    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_18_23/ADDRD3
    SLICE_X62Y150        RAMD32                                       r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_18_23/RAMA/WADR3
  -------------------------------------------------------------------    -------------------

                         (clock rx_clk rise edge)     0.000     0.000 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK
                         net (fo=1, routed)           0.563     0.563    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/xclk_gtx
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.030     0.593 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/clk1x_i/O
                         net (fo=327, routed)         0.836     1.429    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_18_23/WCLK
    SLICE_X62Y150        RAMD32                                       r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_18_23/RAMA/CLK
                         clock pessimism             -0.253     1.176    
    SLICE_X62Y150        RAMD32 (Hold_ramd32_CLK_WADR3)
                                                      0.225     1.401    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_18_23/RAMA
  -------------------------------------------------------------------
                         required time                         -1.401    
                         arrival time                           1.467    
  -------------------------------------------------------------------
                         slack                                  0.066    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         rx_clk
Waveform(ns):       { 0.000 3.333 }
Period(ns):         6.666
Sources:            { sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK }

Check Type        Corner  Lib Pin                 Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location            Pin
Min Period        n/a     GTXE2_CHANNEL/RXUSRCLK  n/a            4.000         6.666       2.666      GTXE2_CHANNEL_X0Y0  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXUSRCLK
Low Pulse Width   Fast    RAMD32/CLK              n/a            0.910         3.333       2.423      SLICE_X58Y152       sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_0_5/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK              n/a            0.910         3.333       2.423      SLICE_X62Y152       sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_12_17/RAMA/CLK



---------------------------------------------------------------------------------------------------
From Clock:  txoutclk
  To Clock:  txoutclk

Setup :            0  Failing Endpoints,  Worst Slack        2.026ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.127ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.666ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             2.026ns  (required time - arrival time)
  Source:                 sata_top/ahci_sata_layers_i/phy/gtx_wrap/txcharisk_enc_in_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by txoutclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Destination:            sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/RAMB36E1_i/ADDRBWRADDR[13]
                            (rising edge-triggered cell RAMB36E1 clocked by txoutclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Path Group:             txoutclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (txoutclk rise@6.666ns - txoutclk rise@0.000ns)
  Data Path Delay:        4.207ns  (logic 0.246ns (5.848%)  route 3.961ns (94.152%))
  Logic Levels:           0  
  Clock Path Skew:        0.184ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.974ns = ( 9.640 - 6.666 ) 
    Source Clock Delay      (SCD):    2.846ns
    Clock Pessimism Removal (CPR):    0.056ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock txoutclk rise edge)
                                                      0.000     0.000 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK
                         net (fo=1, routed)           1.349     1.349    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/txoutclk_gtx
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.120     1.469 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/clk1x_i/O
                         net (fo=136, routed)         1.377     2.846    sata_top/ahci_sata_layers_i/phy/gtx_wrap/CLK
    SLICE_X55Y131        FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/txcharisk_enc_in_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y131        FDRE (Prop_fdre_C_Q)         0.246     3.092 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/txcharisk_enc_in_r_reg[1]/Q
                         net (fo=1, routed)           3.961     7.053    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/ADDRBWRADDR[8]
    RAMB36_X6Y6          RAMB36E1                                     r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/RAMB36E1_i/ADDRBWRADDR[13]
  -------------------------------------------------------------------    -------------------

                         (clock txoutclk rise edge)
                                                      6.666     6.666 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     6.666 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK
                         net (fo=1, routed)           1.300     7.966    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/txoutclk_gtx
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.113     8.079 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/clk1x_i/O
                         net (fo=136, routed)         1.561     9.640    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/CLK
    RAMB36_X6Y6          RAMB36E1                                     r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/RAMB36E1_i/CLKBWRCLK
                         clock pessimism              0.056     9.696    
                         clock uncertainty           -0.035     9.660    
    RAMB36_X6Y6          RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13])
                                                     -0.582     9.078    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/RAMB36E1_i
  -------------------------------------------------------------------
                         required time                          9.078    
                         arrival time                          -7.053    
  -------------------------------------------------------------------
                         slack                                  2.026    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.127ns  (arrival time - required time)
  Source:                 sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resynchro/data_out_reg[38]/C
                            (rising edge-triggered cell FDPE clocked by txoutclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Destination:            sata_top/ahci_sata_layers_i/phy/gtx_wrap/txelecidle_gtx_f_reg[1]/D
                            (rising edge-triggered cell FDPE clocked by txoutclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Path Group:             txoutclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (txoutclk rise@0.000ns - txoutclk rise@0.000ns)
  Data Path Delay:        0.360ns  (logic 0.100ns (27.779%)  route 0.260ns (72.221%))
  Logic Levels:           0  
  Clock Path Skew:        0.192ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.318ns
    Source Clock Delay      (SCD):    1.077ns
    Clock Pessimism Removal (CPR):    0.049ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock txoutclk rise edge)
                                                      0.000     0.000 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK
                         net (fo=1, routed)           0.526     0.526    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/txoutclk_gtx
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.026     0.552 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/clk1x_i/O
                         net (fo=136, routed)         0.525     1.077    sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resynchro/CLK
    SLICE_X55Y134        FDPE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resynchro/data_out_reg[38]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y134        FDPE (Prop_fdpe_C_Q)         0.100     1.177 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resynchro/data_out_reg[38]/Q
                         net (fo=1, routed)           0.260     1.437    sata_top/ahci_sata_layers_i/phy/gtx_wrap/data_out[38]
    SLICE_X65Y130        FDPE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/txelecidle_gtx_f_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock txoutclk rise edge)
                                                      0.000     0.000 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK
                         net (fo=1, routed)           0.563     0.563    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/txoutclk_gtx
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.030     0.593 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/clk1x_i/O
                         net (fo=136, routed)         0.725     1.318    sata_top/ahci_sata_layers_i/phy/gtx_wrap/CLK
    SLICE_X65Y130        FDPE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/txelecidle_gtx_f_reg[1]/C
                         clock pessimism             -0.049     1.269    
    SLICE_X65Y130        FDPE (Hold_fdpe_C_D)         0.041     1.310    sata_top/ahci_sata_layers_i/phy/gtx_wrap/txelecidle_gtx_f_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.310    
                         arrival time                           1.437    
  -------------------------------------------------------------------
                         slack                                  0.127    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         txoutclk
Waveform(ns):       { 0.000 3.333 }
Period(ns):         6.666
Sources:            { sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK }

Check Type        Corner  Lib Pin                 Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location            Pin
Min Period        n/a     GTXE2_CHANNEL/TXUSRCLK  n/a            4.000         6.666       2.666      GTXE2_CHANNEL_X0Y0  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXUSRCLK
Low Pulse Width   Fast    FDRE/C                  n/a            0.400         3.333       2.933      SLICE_X111Y19       sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/outdata_l_reg[8]/C
High Pulse Width  Slow    FDPE/C                  n/a            0.350         3.333       2.983      SLICE_X54Y131       sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resynchro/rrst_reg[0]/C



---------------------------------------------------------------------------------------------------
From Clock:  usrclk2
  To Clock:  usrclk2

Setup :            0  Failing Endpoints,  Worst Slack        4.435ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.070ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        5.756ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             4.435ns  (required time - arrival time)
  Source:                 sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
  Destination:            sata_top/ahci_sata_layers_i/link/state_rcvr_data_reg/D
                            (rising edge-triggered cell FDRE clocked by usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
  Path Group:             usrclk2
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            13.333ns  (usrclk2 rise@13.333ns - usrclk2 rise@0.000ns)
  Data Path Delay:        8.744ns  (logic 0.481ns (5.501%)  route 8.263ns (94.499%))
  Logic Levels:           4  (LUT3=2 LUT5=1 LUT6=1)
  Clock Path Skew:        -0.189ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.147ns = ( 16.480 - 13.333 ) 
    Source Clock Delay      (SCD):    3.627ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock usrclk2 rise edge)    0.000     0.000 r  
    SLICE_X61Y48         FDRE                         0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           1.917     1.917    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.120     2.037 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        1.590     3.627    sata_top/ahci_sata_layers_i/phy/rxdata_reg[0]__0
    SLICE_X61Y44         FDCE                                         r  sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X61Y44         FDCE (Prop_fdce_C_Q)         0.269     3.896 r  sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[0]/Q
                         net (fo=2, routed)           0.473     4.368    sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg_n_0_[0]
    SLICE_X60Y44         LUT3 (Prop_lut3_I0_O)        0.053     4.421 f  sata_top/ahci_sata_layers_i/phy/was_rst_i_1/O
                         net (fo=278, routed)         6.427    10.849    sata_top/ahci_sata_layers_i/phy/oob_ctrl/sata_reset_done_r_reg[0]
    SLICE_X45Y155        LUT5 (Prop_lut5_I1_O)        0.053    10.902 f  sata_top/ahci_sata_layers_i/phy/oob_ctrl/state_rcvr_eof_i_3/O
                         net (fo=5, routed)           0.937    11.838    sata_top/ahci_sata_layers_i/link/phy_ready_r_reg_1
    SLICE_X52Y155        LUT3 (Prop_lut3_I0_O)        0.053    11.891 f  sata_top/ahci_sata_layers_i/link/state_rcvr_shold_i_2/O
                         net (fo=3, routed)           0.427    12.318    sata_top/ahci_sata_layers_i/link/crc/phy_ready_r_reg_0
    SLICE_X52Y156        LUT6 (Prop_lut6_I3_O)        0.053    12.371 r  sata_top/ahci_sata_layers_i/link/crc/state_rcvr_data_i_1/O
                         net (fo=1, routed)           0.000    12.371    sata_top/ahci_sata_layers_i/link/state_rcvr_data0
    SLICE_X52Y156        FDRE                                         r  sata_top/ahci_sata_layers_i/link/state_rcvr_data_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock usrclk2 rise edge)   13.333    13.333 r  
    SLICE_X61Y48         FDRE                         0.000    13.333 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           1.633    14.966    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.113    15.079 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        1.401    16.480    sata_top/ahci_sata_layers_i/link/usrclk2_r_reg
    SLICE_X52Y156        FDRE                                         r  sata_top/ahci_sata_layers_i/link/state_rcvr_data_reg/C
                         clock pessimism              0.291    16.771    
                         clock uncertainty           -0.035    16.735    
    SLICE_X52Y156        FDRE (Setup_fdre_C_D)        0.071    16.806    sata_top/ahci_sata_layers_i/link/state_rcvr_data_reg
  -------------------------------------------------------------------
                         required time                         16.806    
                         arrival time                         -12.371    
  -------------------------------------------------------------------
                         slack                                  4.435    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.070ns  (arrival time - required time)
  Source:                 sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/dav_rclk_more_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
  Destination:            sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/dav_rclk_more_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
  Path Group:             usrclk2
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (usrclk2 rise@0.000ns - usrclk2 rise@0.000ns)
  Data Path Delay:        0.228ns  (logic 0.118ns (51.803%)  route 0.110ns (48.197%))
  Logic Levels:           0  
  Clock Path Skew:        0.118ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.805ns
    Source Clock Delay      (SCD):    1.524ns
    Clock Pessimism Removal (CPR):    0.163ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock usrclk2 rise edge)    0.000     0.000 r  
    SLICE_X61Y48         FDRE                         0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           0.886     0.886    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.026     0.912 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        0.612     1.524    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/usrclk2_r_reg
    SLICE_X66Y150        FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/dav_rclk_more_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y150        FDRE (Prop_fdre_C_Q)         0.118     1.642 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/dav_rclk_more_reg[0]/Q
                         net (fo=1, routed)           0.110     1.752    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/dav_rclk_more[0]
    SLICE_X66Y149        FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/dav_rclk_more_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock usrclk2 rise edge)    0.000     0.000 r  
    SLICE_X61Y48         FDRE                         0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           1.037     1.037    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.030     1.067 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        0.738     1.805    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/usrclk2_r_reg
    SLICE_X66Y149        FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/dav_rclk_more_reg[1]/C
                         clock pessimism             -0.163     1.642    
    SLICE_X66Y149        FDRE (Hold_fdre_C_D)         0.040     1.682    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/dav_rclk_more_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.682    
                         arrival time                           1.752    
  -------------------------------------------------------------------
                         slack                                  0.070    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         usrclk2
Waveform(ns):       { 0.000 6.666 }
Period(ns):         13.333
Sources:            { sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.183         13.333      11.150     RAMB36_X2Y25   sata_top/ahci_top_i/ahci_dma_i/ct_data_ram_reg_bram_0/CLKARDCLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.910         6.667       5.757      SLICE_X52Y135  sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resynchro/ram_reg_0_7_0_5/RAMC/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.910         6.666       5.756      SLICE_X32Y135  sata_top/ahci_top_i/ahci_dma_i/ahci_dma_wr_fifo_i/fifo0_ram_reg_0_7_24_29/RAMA/CLK



---------------------------------------------------------------------------------------------------
From Clock:  ddr3_clk_div
  To Clock:  ddr3_clk

Setup :            0  Failing Endpoints,  Worst Slack        0.196ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.213ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.196ns  (required time - arrival time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/C
                            (rising edge-triggered cell FDSE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_cas_i/oserdes_i/oserdes_i/T1
                            (rising edge-triggered cell OSERDESE2 clocked by ddr3_clk  {rise@0.000ns fall@1.250ns period=2.500ns})
  Path Group:             ddr3_clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.500ns  (ddr3_clk rise@2.500ns - ddr3_clk_div rise@0.000ns)
  Data Path Delay:        1.409ns  (logic 0.308ns (21.867%)  route 1.101ns (78.133%))
  Logic Levels:           0  
  Clock Path Skew:        -0.011ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.643ns = ( 6.143 - 2.500 ) 
    Source Clock Delay      (SCD):    3.797ns
    Clock Pessimism Removal (CPR):    0.143ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_clk_div rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     1.575    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.088     1.663 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           1.106     2.769    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.377     3.146 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.651     3.797    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/psincdec_reg
    SLICE_X118Y130       FDSE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X118Y130       FDSE (Prop_fdse_C_Q)         0.308     4.105 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/Q
                         net (fo=23, routed)          1.101     5.206    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_cas_i/oserdes_i/in_tri_r_reg
    OLOGIC_X1Y103        OSERDESE2                                    r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_cas_i/oserdes_i/oserdes_i/T1
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_clk rise edge)
                                                      2.500     2.500 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     2.500 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     3.937    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.083     4.020 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1
                         net (fo=1, routed)           1.016     5.036    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_pre
    BUFR_X1Y8            BUFR (Prop_bufr_I_O)         0.370     5.406 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_bufr_i/O
                         net (fo=75, routed)          0.737     6.143    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_cas_i/oserdes_i/clk
    OLOGIC_X1Y103        OSERDESE2                                    r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_cas_i/oserdes_i/oserdes_i/CLK
                         clock pessimism              0.143     6.286    
                         clock uncertainty           -0.205     6.081    
    OLOGIC_X1Y103        OSERDESE2 (Setup_oserdese2_CLK_T1)
                                                     -0.679     5.402    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_cas_i/oserdes_i/oserdes_i
  -------------------------------------------------------------------
                         required time                          5.402    
                         arrival time                          -5.206    
  -------------------------------------------------------------------
                         slack                                  0.196    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.213ns  (arrival time - required time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/C
                            (rising edge-triggered cell FDSE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[12].cmda_addr_i/oserdes_i/oserdes_i/T1
                            (rising edge-triggered cell OSERDESE2 clocked by ddr3_clk  {rise@0.000ns fall@1.250ns period=2.500ns})
  Path Group:             ddr3_clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (ddr3_clk rise@0.000ns - ddr3_clk_div rise@0.000ns)
  Data Path Delay:        0.471ns  (logic 0.118ns (25.046%)  route 0.353ns (74.954%))
  Logic Levels:           0  
  Clock Path Skew:        0.157ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.796ns
    Source Clock Delay      (SCD):    1.420ns
    Clock Pessimism Removal (CPR):    0.219ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_clk_div rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.580     0.580    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.050     0.630 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           0.433     1.063    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.090     1.153 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.267     1.420    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/psincdec_reg
    SLICE_X118Y130       FDSE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X118Y130       FDSE (Prop_fdse_C_Q)         0.118     1.538 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/Q
                         net (fo=23, routed)          0.353     1.891    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[12].cmda_addr_i/oserdes_i/in_tri_r_reg
    OLOGIC_X1Y137        OSERDESE2                                    r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[12].cmda_addr_i/oserdes_i/oserdes_i/T1
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.796     0.796    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.053     0.849 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1
                         net (fo=1, routed)           0.490     1.339    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_pre
    BUFR_X1Y8            BUFR (Prop_bufr_I_O)         0.093     1.432 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_bufr_i/O
                         net (fo=75, routed)          0.364     1.796    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[12].cmda_addr_i/oserdes_i/clk
    OLOGIC_X1Y137        OSERDESE2                                    r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[12].cmda_addr_i/oserdes_i/oserdes_i/CLK
                         clock pessimism             -0.219     1.577    
                         clock uncertainty            0.205     1.782    
    OLOGIC_X1Y137        OSERDESE2 (Hold_oserdese2_CLK_T1)
                                                     -0.104     1.678    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[12].cmda_addr_i/oserdes_i/oserdes_i
  -------------------------------------------------------------------
                         required time                         -1.678    
                         arrival time                           1.891    
  -------------------------------------------------------------------
                         slack                                  0.213    





---------------------------------------------------------------------------------------------------
From Clock:  ddr3_mclk
  To Clock:  ddr3_clk_div

Setup :            0  Failing Endpoints,  Worst Slack        0.047ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        1.423ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.047ns  (required time - arrival time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i/CLKARDCLK
                            (rising edge-triggered cell RAMB36E1 clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/tin_dqs_r_reg[1]/D
                            (rising edge-triggered cell FDSE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             ddr3_clk_div
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.750ns  (ddr3_clk_div rise@5.000ns - ddr3_mclk rise@1.250ns)
  Data Path Delay:        2.316ns  (logic 0.854ns (36.880%)  route 1.462ns (63.120%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -1.164ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.574ns = ( 8.574 - 5.000 ) 
    Source Clock Delay      (SCD):    4.881ns = ( 6.131 - 1.250 ) 
    Clock Pessimism Removal (CPR):    0.143ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     2.825    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.088     2.913 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.628     4.541    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.120     4.661 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=33322, routed)       1.470     6.131    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/CLK
    RAMB36_X6Y24         RAMB36E1                                     r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X6Y24         RAMB36E1 (Prop_ramb36e1_CLKARDCLK_DOADO[6])
                                                      0.748     6.879 f  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i/DOADO[6]
                         net (fo=1, routed)           0.691     7.569    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i_0[5]
    SLICE_X100Y116       LUT4 (Prop_lut4_I3_O)        0.053     7.622 f  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/extra_prev[5]_i_1/O
                         net (fo=6, routed)           0.280     7.902    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/RAMB36E1_i[0]
    SLICE_X100Y115       LUT6 (Prop_lut6_I1_O)        0.053     7.955 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/tin_dqs_r[1]_i_1/O
                         net (fo=2, routed)           0.491     8.446    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/tin_dqs[1]
    SLICE_X105Y116       FDSE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/tin_dqs_r_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_clk_div rise edge)
                                                      5.000     5.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     5.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     6.437    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.083     6.520 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           1.016     7.536    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.370     7.906 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.668     8.574    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/psincdec_reg_0
    SLICE_X105Y116       FDSE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/tin_dqs_r_reg[1]/C
                         clock pessimism              0.143     8.717    
                         clock uncertainty           -0.205     8.512    
    SLICE_X105Y116       FDSE (Setup_fdse_C_D)       -0.018     8.494    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/tin_dqs_r_reg[1]
  -------------------------------------------------------------------
                         required time                          8.494    
                         arrival time                          -8.446    
  -------------------------------------------------------------------
                         slack                                  0.047    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.423ns  (arrival time - required time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd_deser_dly_i/i_cmd_deser_multi/deser_r_reg[23]/C
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dly_data_r_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             ddr3_clk_div
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            -1.250ns  (ddr3_clk_div rise@0.000ns - ddr3_mclk rise@1.250ns)
  Data Path Delay:        0.271ns  (logic 0.118ns (43.501%)  route 0.153ns (56.499%))
  Logic Levels:           0  
  Clock Path Skew:        -0.144ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.818ns
    Source Clock Delay      (SCD):    1.743ns = ( 2.993 - 1.250 ) 
    Clock Pessimism Removal (CPR):    0.219ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.580     1.830    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.050     1.880 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.559     2.439    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.465 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=33322, routed)       0.528     2.993    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd_deser_dly_i/i_cmd_deser_multi/CLK
    SLICE_X70Y110        FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd_deser_dly_i/i_cmd_deser_multi/deser_r_reg[23]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y110        FDRE (Prop_fdre_C_Q)         0.118     3.111 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd_deser_dly_i/i_cmd_deser_multi/deser_r_reg[23]/Q
                         net (fo=2, routed)           0.153     3.264    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/D[7]
    SLICE_X70Y109        FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dly_data_r_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_clk_div rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.796     0.796    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.053     0.849 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           0.490     1.339    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.093     1.432 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.386     1.818    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/clk_div
    SLICE_X70Y109        FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dly_data_r_reg[7]/C
                         clock pessimism             -0.219     1.599    
                         clock uncertainty            0.205     1.804    
    SLICE_X70Y109        FDRE (Hold_fdre_C_D)         0.037     1.841    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dly_data_r_reg[7]
  -------------------------------------------------------------------
                         required time                         -1.841    
                         arrival time                           3.264    
  -------------------------------------------------------------------
                         slack                                  1.423    





---------------------------------------------------------------------------------------------------
From Clock:  ddr3_clk_div
  To Clock:  ddr3_mclk

Setup :            0  Failing Endpoints,  Worst Slack        2.762ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.533ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             2.762ns  (required time - arrival time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dci_ready_r1_reg/C
                            (falling edge-triggered cell FDRE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dci_ready_r2_reg/D
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Path Group:             ddr3_mclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.750ns  (ddr3_mclk rise@6.250ns - ddr3_clk_div fall@2.500ns)
  Data Path Delay:        1.434ns  (logic 0.272ns (18.969%)  route 1.162ns (81.031%))
  Logic Levels:           0  
  Clock Path Skew:        0.660ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.453ns = ( 10.703 - 6.250 ) 
    Source Clock Delay      (SCD):    3.936ns = ( 6.436 - 2.500 ) 
    Clock Pessimism Removal (CPR):    0.143ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_clk_div fall edge)
                                                      2.500     2.500 f  
    BUFGCTRL_X0Y23       BUFG                         0.000     2.500 f  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     4.075    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.088     4.163 f  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           1.106     5.269    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.377     5.646 f  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.790     6.436    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/clk_div
    SLICE_X59Y106        FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dci_ready_r1_reg/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y106        FDRE (Prop_fdre_C_Q)         0.272     6.708 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dci_ready_r1_reg/Q
                         net (fo=1, routed)           1.162     7.870    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dci_ready_r1
    SLICE_X52Y82         FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dci_ready_r2_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_mclk rise edge)
                                                      6.250     6.250 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     6.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     7.687    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.083     7.770 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.544     9.314    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.113     9.427 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=33322, routed)       1.276    10.703    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/CLK
    SLICE_X52Y82         FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dci_ready_r2_reg/C
                         clock pessimism              0.143    10.846    
                         clock uncertainty           -0.205    10.641    
    SLICE_X52Y82         FDRE (Setup_fdre_C_D)       -0.009    10.632    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dci_ready_r2_reg
  -------------------------------------------------------------------
                         required time                         10.632    
                         arrival time                          -7.870    
  -------------------------------------------------------------------
                         slack                                  2.762    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.533ns  (arrival time - required time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/locked_mmcm_r1_reg/C
                            (falling edge-triggered cell FDRE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/locked_mmcm_r2_reg/D
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Path Group:             ddr3_mclk
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            -1.250ns  (ddr3_mclk rise@1.250ns - ddr3_clk_div fall@2.500ns)
  Data Path Delay:        0.681ns  (logic 0.218ns (31.996%)  route 0.463ns (68.004%))
  Logic Levels:           0  
  Clock Path Skew:        1.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.807ns = ( 6.057 - 1.250 ) 
    Source Clock Delay      (SCD):    3.651ns = ( 6.151 - 2.500 ) 
    Clock Pessimism Removal (CPR):    0.143ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_clk_div fall edge)
                                                      2.500     2.500 f  
    BUFGCTRL_X0Y23       BUFG                         0.000     2.500 f  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     3.937    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.083     4.020 f  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           1.016     5.036    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.370     5.406 f  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
                         net (fo=753, routed)         0.745     6.151    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/clk_div
    SLICE_X59Y106        FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/locked_mmcm_r1_reg/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y106        FDRE (Prop_fdre_C_Q)         0.218     6.369 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/locked_mmcm_r1_reg/Q
                         net (fo=1, routed)           0.463     6.832    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/locked_mmcm_r1
    SLICE_X58Y96         FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/locked_mmcm_r2_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     2.825    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.088     2.913 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.628     4.541    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.120     4.661 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=33322, routed)       1.396     6.057    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/CLK
    SLICE_X58Y96         FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/locked_mmcm_r2_reg/C
                         clock pessimism             -0.143     5.914    
                         clock uncertainty            0.205     6.119    
    SLICE_X58Y96         FDRE (Hold_fdre_C_D)         0.180     6.299    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/locked_mmcm_r2_reg
  -------------------------------------------------------------------
                         required time                         -6.299    
                         arrival time                           6.832    
  -------------------------------------------------------------------
                         slack                                  0.533    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  axihp_clk
  To Clock:  axihp_clk

Setup :            0  Failing Endpoints,  Worst Slack        1.916ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.605ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.916ns  (required time - arrival time)
  Source:                 sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            mult_saxi_wr_i/status_wr_i/in_reg_reg/CLR
                            (recovery check against rising-edge clock axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            6.667ns  (axihp_clk rise@6.667ns - axihp_clk rise@0.000ns)
  Data Path Delay:        4.457ns  (logic 0.269ns (6.035%)  route 4.188ns (93.965%))
  Logic Levels:           0  
  Clock Path Skew:        0.033ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.937ns = ( 11.604 - 6.667 ) 
    Source Clock Delay      (SCD):    5.231ns
    Clock Pessimism Removal (CPR):    0.327ns
  Clock Uncertainty:      0.071ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.124ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock axihp_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.784     1.784    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X1Y3       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.088     1.872 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.868     3.740    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.120     3.860 r  clocks393_i/hclk_i/clk1x_i/O
                         net (fo=3868, routed)        1.371     5.231    sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/hclk
    SLICE_X39Y124        FDRE                                         r  sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y124        FDRE (Prop_fdre_C_Q)         0.269     5.500 f  sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q
                         net (fo=335, routed)         4.188     9.688    mult_saxi_wr_i/status_wr_i/rst[0]
    SLICE_X39Y169        FDCE                                         f  mult_saxi_wr_i/status_wr_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock axihp_clk rise edge)
                                                      6.667     6.667 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     6.667 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.593     8.260    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X1Y3       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.083     8.343 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.754    10.097    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.113    10.210 r  clocks393_i/hclk_i/clk1x_i/O
                         net (fo=3868, routed)        1.394    11.604    mult_saxi_wr_i/status_wr_i/hclk
    SLICE_X39Y169        FDCE                                         r  mult_saxi_wr_i/status_wr_i/in_reg_reg/C
                         clock pessimism              0.327    11.931    
                         clock uncertainty           -0.071    11.859    
    SLICE_X39Y169        FDCE (Recov_fdce_C_CLR)     -0.255    11.604    mult_saxi_wr_i/status_wr_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                         11.604    
                         arrival time                          -9.688    
  -------------------------------------------------------------------
                         slack                                  1.916    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.605ns  (arrival time - required time)
  Source:                 sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            sata_top/ahci_top_i/axi_ahci_regs_i/afi_cache_set_i/in_reg_reg/CLR
                            (removal check against rising-edge clock axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (axihp_clk rise@0.000ns - axihp_clk rise@0.000ns)
  Data Path Delay:        0.595ns  (logic 0.100ns (16.811%)  route 0.495ns (83.189%))
  Logic Levels:           0  
  Clock Path Skew:        0.040ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.561ns
    Source Clock Delay      (SCD):    2.035ns
    Clock Pessimism Removal (CPR):    0.486ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock axihp_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.666     0.666    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X1Y3       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.050     0.716 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.774     1.490    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.026     1.516 r  clocks393_i/hclk_i/clk1x_i/O
                         net (fo=3868, routed)        0.519     2.035    sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/hclk
    SLICE_X39Y124        FDRE                                         r  sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y124        FDRE (Prop_fdre_C_Q)         0.100     2.135 f  sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q
                         net (fo=335, routed)         0.495     2.630    sata_top/ahci_top_i/axi_ahci_regs_i/afi_cache_set_i/regs_reg[1][0]
    SLICE_X38Y135        FDCE                                         f  sata_top/ahci_top_i/axi_ahci_regs_i/afi_cache_set_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock axihp_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.903     0.903    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X1Y3       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.053     0.956 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.843     1.799    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.030     1.829 r  clocks393_i/hclk_i/clk1x_i/O
                         net (fo=3868, routed)        0.732     2.561    sata_top/ahci_top_i/axi_ahci_regs_i/afi_cache_set_i/hclk
    SLICE_X38Y135        FDCE                                         r  sata_top/ahci_top_i/axi_ahci_regs_i/afi_cache_set_i/in_reg_reg/C
                         clock pessimism             -0.486     2.075    
    SLICE_X38Y135        FDCE (Remov_fdce_C_CLR)     -0.050     2.025    sata_top/ahci_top_i/axi_ahci_regs_i/afi_cache_set_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                         -2.025    
                         arrival time                           2.630    
  -------------------------------------------------------------------
                         slack                                  0.605    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  ddr3_mclk
  To Clock:  ddr3_mclk

Setup :            0  Failing Endpoints,  Worst Slack        0.808ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.269ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.808ns  (required time - arrival time)
  Source:                 sync_resets_i/rst_early_master_reg_replica_8/C
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Destination:            compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_cmd_decode_i/frame_start_xclk_i/in_reg_reg/CLR
                            (recovery check against rising-edge clock ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (ddr3_mclk rise@6.250ns - ddr3_mclk rise@1.250ns)
  Data Path Delay:        3.457ns  (logic 0.246ns (7.117%)  route 3.210ns (92.883%))
  Logic Levels:           0  
  Clock Path Skew:        -0.290ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.471ns = ( 10.721 - 6.250 ) 
    Source Clock Delay      (SCD):    5.005ns = ( 6.255 - 1.250 ) 
    Clock Pessimism Removal (CPR):    0.244ns
  Clock Uncertainty:      0.085ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     2.825    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.088     2.913 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.628     4.541    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.120     4.661 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=33322, routed)       1.594     6.255    sync_resets_i/mclk
    SLICE_X63Y44         FDRE                                         r  sync_resets_i/rst_early_master_reg_replica_8/C
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y44         FDRE (Prop_fdre_C_Q)         0.246     6.501 f  sync_resets_i/rst_early_master_reg_replica_8/Q
                         net (fo=254, routed)         3.210     9.711    compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_cmd_decode_i/frame_start_xclk_i/rst[0]_repN_8_alias
    SLICE_X79Y50         FDCE                                         f  compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_cmd_decode_i/frame_start_xclk_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_mclk rise edge)
                                                      6.250     6.250 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     6.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     7.687    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.083     7.770 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.544     9.314    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.113     9.427 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=33322, routed)       1.294    10.721    compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_cmd_decode_i/frame_start_xclk_i/mclk
    SLICE_X79Y50         FDCE                                         r  compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_cmd_decode_i/frame_start_xclk_i/in_reg_reg/C
                         clock pessimism              0.244    10.965    
                         clock uncertainty           -0.085    10.880    
    SLICE_X79Y50         FDCE (Recov_fdce_C_CLR)     -0.360    10.520    compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_cmd_decode_i/frame_start_xclk_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                         10.520    
                         arrival time                          -9.712    
  -------------------------------------------------------------------
                         slack                                  0.808    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.269ns  (arrival time - required time)
  Source:                 sync_resets_i/rst_early_master_reg_replica/C
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Destination:            event_logger_i/i_we_config_debug_xclk/in_reg_reg/CLR
                            (removal check against rising-edge clock ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (ddr3_mclk rise@1.250ns - ddr3_mclk rise@1.250ns)
  Data Path Delay:        0.483ns  (logic 0.091ns (18.847%)  route 0.392ns (81.153%))
  Logic Levels:           0  
  Clock Path Skew:        0.300ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.375ns = ( 3.625 - 1.250 ) 
    Source Clock Delay      (SCD):    1.780ns = ( 3.030 - 1.250 ) 
    Clock Pessimism Removal (CPR):    0.295ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.580     1.830    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.050     1.880 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.559     2.439    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.465 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=33322, routed)       0.565     3.030    sync_resets_i/mclk
    SLICE_X101Y143       FDRE                                         r  sync_resets_i/rst_early_master_reg_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y143       FDRE (Prop_fdre_C_Q)         0.091     3.121 f  sync_resets_i/rst_early_master_reg_replica/Q
                         net (fo=321, routed)         0.392     3.513    event_logger_i/i_we_config_debug_xclk/rst[0]_repN_alias
    SLICE_X100Y150       FDCE                                         f  event_logger_i/i_we_config_debug_xclk/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.796     2.046    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.053     2.099 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.623     2.722    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.030     2.752 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
                         net (fo=33322, routed)       0.873     3.625    event_logger_i/i_we_config_debug_xclk/mclk
    SLICE_X100Y150       FDCE                                         r  event_logger_i/i_we_config_debug_xclk/in_reg_reg/C
                         clock pessimism             -0.295     3.330    
    SLICE_X100Y150       FDCE (Remov_fdce_C_CLR)     -0.086     3.244    event_logger_i/i_we_config_debug_xclk/in_reg_reg
  -------------------------------------------------------------------
                         required time                         -3.244    
                         arrival time                           3.513    
  -------------------------------------------------------------------
                         slack                                  0.269    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  iclk0
  To Clock:  iclk0

Setup :            0  Failing Endpoints,  Worst Slack        7.983ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.598ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             7.983ns  (required time - arrival time)
  Source:                 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by iclk0  {rise@0.000ns fall@5.208ns period=10.417ns})
  Destination:            sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/pulse_cross_clock_hact_a_mclk_i/in_reg_reg/CLR
                            (recovery check against rising-edge clock iclk0  {rise@0.000ns fall@5.208ns period=10.417ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.417ns  (iclk0 rise@10.417ns - iclk0 rise@0.000ns)
  Data Path Delay:        2.083ns  (logic 0.308ns (14.787%)  route 1.775ns (85.213%))
  Logic Levels:           0  
  Clock Path Skew:        -0.014ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    7.839ns = ( 18.255 - 10.417 ) 
    Source Clock Delay      (SCD):    8.381ns
    Clock Pessimism Removal (CPR):    0.528ns
  Clock Uncertainty:      0.082ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.147ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock iclk0 rise edge)      0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.906     0.906 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           1.253     2.159    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.088     2.247 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           2.009     4.256    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.120     4.376 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        1.778     6.154    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.088     6.242 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.106     7.348    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFR_X0Y1            BUFR (Prop_bufr_I_O)         0.377     7.725 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         0.656     8.381    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/ipclk
    SLICE_X4Y33          FDRE                                         r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X4Y33          FDRE (Prop_fdre_C_Q)         0.308     8.689 f  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/Q
                         net (fo=99, routed)          1.775    10.464    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/pulse_cross_clock_hact_a_mclk_i/Q[0]
    SLICE_X7Y41          FDCE                                         f  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/pulse_cross_clock_hact_a_mclk_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock iclk0 rise edge)     10.417    10.417 r  
    Y12                                               0.000    10.417 r  ffclk0p (IN)
                         net (fo=0)                   0.000    10.417    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.827    11.243 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           1.170    12.413    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.083    12.496 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.911    14.407    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.113    14.520 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        1.646    16.166    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.083    16.249 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.016    17.265    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFR_X0Y1            BUFR (Prop_bufr_I_O)         0.370    17.635 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         0.620    18.255    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/pulse_cross_clock_hact_a_mclk_i/ipclk
    SLICE_X7Y41          FDCE                                         r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/pulse_cross_clock_hact_a_mclk_i/in_reg_reg/C
                         clock pessimism              0.528    18.784    
                         clock uncertainty           -0.082    18.702    
    SLICE_X7Y41          FDCE (Recov_fdce_C_CLR)     -0.255    18.447    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/pulse_cross_clock_hact_a_mclk_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                         18.447    
                         arrival time                         -10.464    
  -------------------------------------------------------------------
                         slack                                  7.983    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.598ns  (arrival time - required time)
  Source:                 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by iclk0  {rise@0.000ns fall@5.208ns period=10.417ns})
  Destination:            sensors393_i/sensor_channel_block[0].sensor_channel_i/sensor_fifo_i/pulse_cross_clock_eof_i/in_reg_reg/CLR
                            (removal check against rising-edge clock iclk0  {rise@0.000ns fall@5.208ns period=10.417ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (iclk0 rise@0.000ns - iclk0 rise@0.000ns)
  Data Path Delay:        0.592ns  (logic 0.118ns (19.936%)  route 0.474ns (80.064%))
  Logic Levels:           0  
  Clock Path Skew:        0.063ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.848ns
    Source Clock Delay      (SCD):    3.289ns
    Clock Pessimism Removal (CPR):    0.496ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock iclk0 rise edge)      0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.446     0.446 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           0.503     0.949    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.050     0.999 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.771     1.770    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.796 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        0.649     2.445    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     2.495 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.433     2.928    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFR_X0Y1            BUFR (Prop_bufr_I_O)         0.090     3.018 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         0.271     3.289    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/ipclk
    SLICE_X4Y33          FDRE                                         r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X4Y33          FDRE (Prop_fdre_C_Q)         0.118     3.407 f  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/Q
                         net (fo=99, routed)          0.474     3.880    sensors393_i/sensor_channel_block[0].sensor_channel_i/sensor_fifo_i/pulse_cross_clock_eof_i/Q[0]
    SLICE_X13Y29         FDCE                                         f  sensors393_i/sensor_channel_block[0].sensor_channel_i/sensor_fifo_i/pulse_cross_clock_eof_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock iclk0 rise edge)      0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.521     0.521 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           0.554     1.075    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.128 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.840     1.968    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.030     1.998 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        0.880     2.878    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.053     2.931 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.490     3.421    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFR_X0Y1            BUFR (Prop_bufr_I_O)         0.093     3.514 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         0.334     3.848    sensors393_i/sensor_channel_block[0].sensor_channel_i/sensor_fifo_i/pulse_cross_clock_eof_i/ipclk
    SLICE_X13Y29         FDCE                                         r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sensor_fifo_i/pulse_cross_clock_eof_i/in_reg_reg/C
                         clock pessimism             -0.496     3.352    
    SLICE_X13Y29         FDCE (Remov_fdce_C_CLR)     -0.069     3.283    sensors393_i/sensor_channel_block[0].sensor_channel_i/sensor_fifo_i/pulse_cross_clock_eof_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                         -3.283    
                         arrival time                           3.880    
  -------------------------------------------------------------------
                         slack                                  0.598    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  iclk1
  To Clock:  iclk1

Setup :            0  Failing Endpoints,  Worst Slack        7.597ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.610ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             7.597ns  (required time - arrival time)
  Source:                 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by iclk1  {rise@0.000ns fall@5.208ns period=10.417ns})
  Destination:            sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/pulse_cross_clock_hact_ext_a_mclk_i/in_reg_reg/CLR
                            (recovery check against rising-edge clock iclk1  {rise@0.000ns fall@5.208ns period=10.417ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.417ns  (iclk1 rise@10.417ns - iclk1 rise@0.000ns)
  Data Path Delay:        2.444ns  (logic 0.269ns (11.009%)  route 2.175ns (88.991%))
  Logic Levels:           0  
  Clock Path Skew:        -0.040ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    8.882ns = ( 19.298 - 10.417 ) 
    Source Clock Delay      (SCD):    9.505ns
    Clock Pessimism Removal (CPR):    0.583ns
  Clock Uncertainty:      0.082ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.147ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock iclk1 rise edge)      0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.906     0.906 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           1.253     2.159    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.088     2.247 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           2.009     4.256    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.120     4.376 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        1.581     5.957    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.088     6.045 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.628     7.673    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.120     7.793 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         1.712     9.505    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/ipclk
    SLICE_X1Y12          FDRE                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X1Y12          FDRE (Prop_fdre_C_Q)         0.269     9.774 f  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/Q
                         net (fo=99, routed)          2.175    11.948    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/pulse_cross_clock_hact_ext_a_mclk_i/Q[0]
    SLICE_X5Y24          FDCE                                         f  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/pulse_cross_clock_hact_ext_a_mclk_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock iclk1 rise edge)     10.417    10.417 r  
    Y12                                               0.000    10.417 r  ffclk0p (IN)
                         net (fo=0)                   0.000    10.417    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.827    11.243 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           1.170    12.413    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.083    12.496 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.911    14.407    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.113    14.520 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        1.450    15.970    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.083    16.053 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.544    17.597    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.113    17.710 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         1.588    19.298    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/pulse_cross_clock_hact_ext_a_mclk_i/ipclk
    SLICE_X5Y24          FDCE                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/pulse_cross_clock_hact_ext_a_mclk_i/in_reg_reg/C
                         clock pessimism              0.583    19.882    
                         clock uncertainty           -0.082    19.800    
    SLICE_X5Y24          FDCE (Recov_fdce_C_CLR)     -0.255    19.545    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/pulse_cross_clock_hact_ext_a_mclk_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                         19.545    
                         arrival time                         -11.948    
  -------------------------------------------------------------------
                         slack                                  7.597    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.610ns  (arrival time - required time)
  Source:                 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by iclk1  {rise@0.000ns fall@5.208ns period=10.417ns})
  Destination:            sensors393_i/sensor_channel_block[1].sensor_channel_i/sensor_fifo_i/pulse_cross_clock_sof_i/in_reg_reg/CLR
                            (removal check against rising-edge clock iclk1  {rise@0.000ns fall@5.208ns period=10.417ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (iclk1 rise@0.000ns - iclk1 rise@0.000ns)
  Data Path Delay:        0.576ns  (logic 0.100ns (17.370%)  route 0.476ns (82.630%))
  Logic Levels:           0  
  Clock Path Skew:        0.035ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.399ns
    Source Clock Delay      (SCD):    3.692ns
    Clock Pessimism Removal (CPR):    0.672ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock iclk1 rise edge)      0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.446     0.446 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           0.503     0.949    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.050     0.999 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.771     1.770    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.796 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        0.596     2.392    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     2.442 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.559     3.001    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.026     3.027 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         0.665     3.692    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/ipclk
    SLICE_X1Y12          FDRE                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X1Y12          FDRE (Prop_fdre_C_Q)         0.100     3.792 f  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/Q
                         net (fo=99, routed)          0.476     4.267    sensors393_i/sensor_channel_block[1].sensor_channel_i/sensor_fifo_i/pulse_cross_clock_sof_i/Q[0]
    SLICE_X5Y8           FDCE                                         f  sensors393_i/sensor_channel_block[1].sensor_channel_i/sensor_fifo_i/pulse_cross_clock_sof_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock iclk1 rise edge)      0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.521     0.521 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           0.554     1.075    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.128 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.840     1.968    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.030     1.998 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        0.807     2.805    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.053     2.858 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.623     3.481    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.030     3.511 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         0.888     4.399    sensors393_i/sensor_channel_block[1].sensor_channel_i/sensor_fifo_i/pulse_cross_clock_sof_i/ipclk
    SLICE_X5Y8           FDCE                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sensor_fifo_i/pulse_cross_clock_sof_i/in_reg_reg/C
                         clock pessimism             -0.672     3.727    
    SLICE_X5Y8           FDCE (Remov_fdce_C_CLR)     -0.069     3.658    sensors393_i/sensor_channel_block[1].sensor_channel_i/sensor_fifo_i/pulse_cross_clock_sof_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                         -3.658    
                         arrival time                           4.267    
  -------------------------------------------------------------------
                         slack                                  0.610    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  iclk2
  To Clock:  iclk2

Setup :            0  Failing Endpoints,  Worst Slack        8.829ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.353ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             8.829ns  (required time - arrival time)
  Source:                 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by iclk2  {rise@0.000ns fall@5.208ns period=10.417ns})
  Destination:            sensors393_i/sensor_channel_block[2].sensor_channel_i/sensor_fifo_i/pulse_cross_clock_eof_i/in_reg_reg/CLR
                            (recovery check against rising-edge clock iclk2  {rise@0.000ns fall@5.208ns period=10.417ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.417ns  (iclk2 rise@10.417ns - iclk2 rise@0.000ns)
  Data Path Delay:        1.278ns  (logic 0.308ns (24.104%)  route 0.970ns (75.896%))
  Logic Levels:           0  
  Clock Path Skew:        -0.036ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    7.639ns = ( 18.055 - 10.417 ) 
    Source Clock Delay      (SCD):    8.179ns
    Clock Pessimism Removal (CPR):    0.504ns
  Clock Uncertainty:      0.082ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.147ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock iclk2 rise edge)      0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.906     0.906 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           1.253     2.159    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.088     2.247 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           2.009     4.256    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.120     4.376 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        1.582     5.958    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.088     6.046 r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.106     7.152    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFR_X0Y5            BUFR (Prop_bufr_I_O)         0.377     7.529 r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         0.650     8.179    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/ipclk
    SLICE_X4Y78          FDRE                                         r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X4Y78          FDRE (Prop_fdre_C_Q)         0.308     8.487 f  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/Q
                         net (fo=99, routed)          0.970     9.457    sensors393_i/sensor_channel_block[2].sensor_channel_i/sensor_fifo_i/pulse_cross_clock_eof_i/Q[0]
    SLICE_X0Y66          FDCE                                         f  sensors393_i/sensor_channel_block[2].sensor_channel_i/sensor_fifo_i/pulse_cross_clock_eof_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock iclk2 rise edge)     10.417    10.417 r  
    Y12                                               0.000    10.417 r  ffclk0p (IN)
                         net (fo=0)                   0.000    10.417    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.827    11.243 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           1.170    12.413    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.083    12.496 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.911    14.407    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.113    14.520 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        1.452    15.972    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.083    16.055 r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.016    17.071    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFR_X0Y5            BUFR (Prop_bufr_I_O)         0.370    17.441 r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         0.614    18.055    sensors393_i/sensor_channel_block[2].sensor_channel_i/sensor_fifo_i/pulse_cross_clock_eof_i/ipclk
    SLICE_X0Y66          FDCE                                         r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sensor_fifo_i/pulse_cross_clock_eof_i/in_reg_reg/C
                         clock pessimism              0.504    18.559    
                         clock uncertainty           -0.082    18.478    
    SLICE_X0Y66          FDCE (Recov_fdce_C_CLR)     -0.192    18.286    sensors393_i/sensor_channel_block[2].sensor_channel_i/sensor_fifo_i/pulse_cross_clock_eof_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                         18.286    
                         arrival time                          -9.457    
  -------------------------------------------------------------------
                         slack                                  8.829    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.353ns  (arrival time - required time)
  Source:                 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by iclk2  {rise@0.000ns fall@5.208ns period=10.417ns})
  Destination:            sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/pulse_cross_clock_hact_a_mclk_i/in_reg_reg/CLR
                            (removal check against rising-edge clock iclk2  {rise@0.000ns fall@5.208ns period=10.417ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (iclk2 rise@0.000ns - iclk2 rise@0.000ns)
  Data Path Delay:        0.319ns  (logic 0.118ns (37.039%)  route 0.201ns (62.961%))
  Logic Levels:           0  
  Clock Path Skew:        0.035ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.743ns
    Source Clock Delay      (SCD):    3.232ns
    Clock Pessimism Removal (CPR):    0.476ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock iclk2 rise edge)      0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.446     0.446 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           0.503     0.949    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.050     0.999 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.771     1.770    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.796 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        0.597     2.393    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     2.443 r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.433     2.876    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFR_X0Y5            BUFR (Prop_bufr_I_O)         0.090     2.966 r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         0.266     3.232    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/ipclk
    SLICE_X4Y78          FDRE                                         r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X4Y78          FDRE (Prop_fdre_C_Q)         0.118     3.350 f  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/Q
                         net (fo=99, routed)          0.201     3.550    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/pulse_cross_clock_hact_a_mclk_i/Q[0]
    SLICE_X3Y78          FDCE                                         f  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/pulse_cross_clock_hact_a_mclk_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock iclk2 rise edge)      0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.521     0.521 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           0.554     1.075    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.128 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.840     1.968    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.030     1.998 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        0.808     2.806    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.053     2.859 r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.490     3.349    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFR_X0Y5            BUFR (Prop_bufr_I_O)         0.093     3.442 r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         0.301     3.743    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/pulse_cross_clock_hact_a_mclk_i/ipclk
    SLICE_X3Y78          FDCE                                         r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/pulse_cross_clock_hact_a_mclk_i/in_reg_reg/C
                         clock pessimism             -0.476     3.267    
    SLICE_X3Y78          FDCE (Remov_fdce_C_CLR)     -0.069     3.198    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/pulse_cross_clock_hact_a_mclk_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                         -3.198    
                         arrival time                           3.550    
  -------------------------------------------------------------------
                         slack                                  0.353    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  iclk3
  To Clock:  iclk3

Setup :            0  Failing Endpoints,  Worst Slack        6.939ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.575ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             6.939ns  (required time - arrival time)
  Source:                 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by iclk3  {rise@0.000ns fall@5.208ns period=10.417ns})
  Destination:            sensors393_i/sensor_channel_block[3].sensor_channel_i/sensor_fifo_i/pulse_cross_clock_sof_i/in_reg_reg/CLR
                            (recovery check against rising-edge clock iclk3  {rise@0.000ns fall@5.208ns period=10.417ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.417ns  (iclk3 rise@10.417ns - iclk3 rise@0.000ns)
  Data Path Delay:        2.889ns  (logic 0.282ns (9.760%)  route 2.607ns (90.240%))
  Logic Levels:           0  
  Clock Path Skew:        -0.150ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    8.916ns = ( 19.332 - 10.417 ) 
    Source Clock Delay      (SCD):    9.735ns
    Clock Pessimism Removal (CPR):    0.669ns
  Clock Uncertainty:      0.082ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.147ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock iclk3 rise edge)      0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.906     0.906 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           1.253     2.159    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.088     2.247 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           2.009     4.256    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.120     4.376 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        1.759     6.135    sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X1Y3      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.088     6.223 r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.875     8.098    sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.120     8.218 r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         1.517     9.735    sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/ipclk
    SLICE_X6Y62          FDRE                                         r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X6Y62          FDRE (Prop_fdre_C_Q)         0.282    10.017 f  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/Q
                         net (fo=99, routed)          2.607    12.624    sensors393_i/sensor_channel_block[3].sensor_channel_i/sensor_fifo_i/pulse_cross_clock_sof_i/Q[0]
    SLICE_X35Y59         FDCE                                         f  sensors393_i/sensor_channel_block[3].sensor_channel_i/sensor_fifo_i/pulse_cross_clock_sof_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock iclk3 rise edge)     10.417    10.417 r  
    Y12                                               0.000    10.417 r  ffclk0p (IN)
                         net (fo=0)                   0.000    10.417    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.827    11.243 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           1.170    12.413    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.083    12.496 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.911    14.407    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.113    14.520 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        1.571    16.091    sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X1Y3      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.083    16.174 r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.760    17.934    sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.113    18.047 r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         1.285    19.332    sensors393_i/sensor_channel_block[3].sensor_channel_i/sensor_fifo_i/pulse_cross_clock_sof_i/ipclk
    SLICE_X35Y59         FDCE                                         r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sensor_fifo_i/pulse_cross_clock_sof_i/in_reg_reg/C
                         clock pessimism              0.669    20.002    
                         clock uncertainty           -0.082    19.920    
    SLICE_X35Y59         FDCE (Recov_fdce_C_CLR)     -0.357    19.563    sensors393_i/sensor_channel_block[3].sensor_channel_i/sensor_fifo_i/pulse_cross_clock_sof_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                         19.563    
                         arrival time                         -12.624    
  -------------------------------------------------------------------
                         slack                                  6.939    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.575ns  (arrival time - required time)
  Source:                 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by iclk3  {rise@0.000ns fall@5.208ns period=10.417ns})
  Destination:            sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/pulse_cross_clock_hact_ext_a_mclk_i/in_reg_reg/CLR
                            (removal check against rising-edge clock iclk3  {rise@0.000ns fall@5.208ns period=10.417ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (iclk3 rise@0.000ns - iclk3 rise@0.000ns)
  Data Path Delay:        0.522ns  (logic 0.107ns (20.500%)  route 0.415ns (79.500%))
  Logic Levels:           0  
  Clock Path Skew:        0.033ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.617ns
    Source Clock Delay      (SCD):    3.904ns
    Clock Pessimism Removal (CPR):    0.680ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock iclk3 rise edge)      0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.446     0.446 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           0.503     0.949    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.050     0.999 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.771     1.770    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.796 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        0.662     2.458    sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X1Y3      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     2.508 r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.756     3.264    sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.026     3.290 r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         0.614     3.904    sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/ipclk
    SLICE_X6Y62          FDRE                                         r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X6Y62          FDRE (Prop_fdre_C_Q)         0.107     4.011 f  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/irst_r_reg[2]/Q
                         net (fo=99, routed)          0.415     4.425    sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/pulse_cross_clock_hact_ext_a_mclk_i/Q[0]
    SLICE_X0Y64          FDCE                                         f  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/pulse_cross_clock_hact_ext_a_mclk_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock iclk3 rise edge)      0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.521     0.521 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           0.554     1.075    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.128 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.840     1.968    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.030     1.998 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        0.898     2.896    sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clk1x
    MMCME2_ADV_X1Y3      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.053     2.949 r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.823     3.772    sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/ipclk_pre
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.030     3.802 r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/clk1x_i/O
                         net (fo=175, routed)         0.815     4.617    sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/pulse_cross_clock_hact_ext_a_mclk_i/ipclk
    SLICE_X0Y64          FDCE                                         r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/pulse_cross_clock_hact_ext_a_mclk_i/in_reg_reg/C
                         clock pessimism             -0.680     3.937    
    SLICE_X0Y64          FDCE (Remov_fdce_C_CLR)     -0.086     3.851    sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/pulse_cross_clock_hact_ext_a_mclk_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                         -3.851    
                         arrival time                           4.425    
  -------------------------------------------------------------------
                         slack                                  0.575    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  pclk
  To Clock:  pclk

Setup :            0  Failing Endpoints,  Worst Slack        5.578ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.433ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             5.578ns  (required time - arrival time)
  Source:                 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/prst_with_sens_mrst_reg[0]/C
                            (rising edge-triggered cell FDPE clocked by pclk  {rise@0.000ns fall@5.208ns period=10.417ns})
  Destination:            sensors393_i/sensor_channel_block[1].sensor_channel_i/pulse_cross_clock_eof_mclk_i/in_reg_reg/CLR
                            (recovery check against rising-edge clock pclk  {rise@0.000ns fall@5.208ns period=10.417ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.417ns  (pclk rise@10.417ns - pclk rise@0.000ns)
  Data Path Delay:        4.393ns  (logic 0.308ns (7.010%)  route 4.085ns (92.990%))
  Logic Levels:           0  
  Clock Path Skew:        -0.071ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.646ns = ( 16.062 - 10.417 ) 
    Source Clock Delay      (SCD):    6.073ns
    Clock Pessimism Removal (CPR):    0.356ns
  Clock Uncertainty:      0.119ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.227ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock pclk rise edge)       0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.906     0.906 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           1.253     2.159    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.088     2.247 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           2.009     4.256    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.120     4.376 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        1.697     6.073    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/clk1x
    SLICE_X0Y24          FDPE                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/prst_with_sens_mrst_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X0Y24          FDPE (Prop_fdpe_C_Q)         0.308     6.381 f  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/prst_with_sens_mrst_reg[0]/Q
                         net (fo=126, routed)         4.085    10.466    sensors393_i/sensor_channel_block[1].sensor_channel_i/pulse_cross_clock_eof_mclk_i/Q[0]
    SLICE_X19Y40         FDCE                                         f  sensors393_i/sensor_channel_block[1].sensor_channel_i/pulse_cross_clock_eof_mclk_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock pclk rise edge)      10.417    10.417 r  
    Y12                                               0.000    10.417 r  ffclk0p (IN)
                         net (fo=0)                   0.000    10.417    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.827    11.243 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           1.170    12.413    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.083    12.496 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.911    14.407    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.113    14.520 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        1.542    16.062    sensors393_i/sensor_channel_block[1].sensor_channel_i/pulse_cross_clock_eof_mclk_i/clk1x
    SLICE_X19Y40         FDCE                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/pulse_cross_clock_eof_mclk_i/in_reg_reg/C
                         clock pessimism              0.356    16.418    
                         clock uncertainty           -0.119    16.300    
    SLICE_X19Y40         FDCE (Recov_fdce_C_CLR)     -0.255    16.045    sensors393_i/sensor_channel_block[1].sensor_channel_i/pulse_cross_clock_eof_mclk_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                         16.045    
                         arrival time                         -10.466    
  -------------------------------------------------------------------
                         slack                                  5.578    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.433ns  (arrival time - required time)
  Source:                 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/en_pclk_reg/C
                            (rising edge-triggered cell FDRE clocked by pclk  {rise@0.000ns fall@5.208ns period=10.417ns})
  Destination:            sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/in_reg_reg/CLR
                            (removal check against rising-edge clock pclk  {rise@0.000ns fall@5.208ns period=10.417ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (pclk rise@0.000ns - pclk rise@0.000ns)
  Data Path Delay:        0.413ns  (logic 0.157ns (38.021%)  route 0.256ns (61.979%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.030ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.732ns
    Source Clock Delay      (SCD):    2.332ns
    Clock Pessimism Removal (CPR):    0.370ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock pclk rise edge)       0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.446     0.446 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           0.503     0.949    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.050     0.999 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.771     1.770    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.796 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        0.536     2.332    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/clk1x
    SLICE_X47Y78         FDRE                                         r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/en_pclk_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y78         FDRE (Prop_fdre_C_Q)         0.091     2.423 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/en_pclk_reg/Q
                         net (fo=1, routed)           0.052     2.474    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/en_pclk
    SLICE_X47Y78         LUT1 (Prop_lut1_I0_O)        0.066     2.540 f  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/in_reg_i_2__0/O
                         net (fo=2, routed)           0.204     2.744    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/rst0
    SLICE_X50Y78         FDCE                                         f  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock pclk rise edge)       0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.521     0.521 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=2, routed)           0.554     1.075    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.128 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.840     1.968    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.030     1.998 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
                         net (fo=4169, routed)        0.734     2.732    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/clk1x
    SLICE_X50Y78         FDCE                                         r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/in_reg_reg/C
                         clock pessimism             -0.370     2.362    
    SLICE_X50Y78         FDCE (Remov_fdce_C_CLR)     -0.050     2.312    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                         -2.312    
                         arrival time                           2.744    
  -------------------------------------------------------------------
                         slack                                  0.433    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  sclk
  To Clock:  sclk

Setup :            0  Failing Endpoints,  Worst Slack        5.107ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.367ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             5.107ns  (required time - arrival time)
  Source:                 timing393_i/camsync393_i/level_cross_clocks_en_pclki/level_cross_clock_block[0].level_cross_clocks_sync_i/sync_zer_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            timing393_i/camsync393_i/i_ts_stb_mclk0/in_reg_reg/CLR
                            (recovery check against rising-edge clock sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (sclk rise@10.000ns - sclk rise@0.000ns)
  Data Path Delay:        4.199ns  (logic 0.399ns (9.502%)  route 3.800ns (90.498%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.363ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.807ns = ( 14.807 - 10.000 ) 
    Source Clock Delay      (SCD):    5.497ns
    Clock Pessimism Removal (CPR):    0.327ns
  Clock Uncertainty:      0.075ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.133ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.784     1.784    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X1Y3       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.088     1.872 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.868     3.740    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y22       BUFG (Prop_bufg_I_O)         0.120     3.860 r  clocks393_i/sync_clk_i/clk1x_i/O
                         net (fo=1443, routed)        1.637     5.497    timing393_i/camsync393_i/level_cross_clocks_en_pclki/level_cross_clock_block[0].level_cross_clocks_sync_i/camsync_clk
    SLICE_X109Y153       FDRE                                         r  timing393_i/camsync393_i/level_cross_clocks_en_pclki/level_cross_clock_block[0].level_cross_clocks_sync_i/sync_zer_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y153       FDRE (Prop_fdre_C_Q)         0.246     5.743 r  timing393_i/camsync393_i/level_cross_clocks_en_pclki/level_cross_clock_block[0].level_cross_clocks_sync_i/sync_zer_reg[1]/Q
                         net (fo=3, routed)           1.024     6.767    sync_resets_i/rst_block[3].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/sync_zer_reg[1]_0[0]
    SLICE_X102Y141       LUT2 (Prop_lut2_I1_O)        0.153     6.920 f  sync_resets_i/rst_block[3].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/in_reg_i_1__139/O
                         net (fo=33, routed)          2.776     9.696    timing393_i/camsync393_i/i_ts_stb_mclk0/regs_reg[1]
    SLICE_X71Y130        FDCE                                         f  timing393_i/camsync393_i/i_ts_stb_mclk0/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock sclk rise edge)      10.000    10.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000    10.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.593    11.593    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X1Y3       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.083    11.676 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.754    13.430    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y22       BUFG (Prop_bufg_I_O)         0.113    13.543 r  clocks393_i/sync_clk_i/clk1x_i/O
                         net (fo=1443, routed)        1.264    14.807    timing393_i/camsync393_i/i_ts_stb_mclk0/camsync_clk
    SLICE_X71Y130        FDCE                                         r  timing393_i/camsync393_i/i_ts_stb_mclk0/in_reg_reg/C
                         clock pessimism              0.327    15.134    
                         clock uncertainty           -0.075    15.059    
    SLICE_X71Y130        FDCE (Recov_fdce_C_CLR)     -0.255    14.804    timing393_i/camsync393_i/i_ts_stb_mclk0/in_reg_reg
  -------------------------------------------------------------------
                         required time                         14.804    
                         arrival time                          -9.696    
  -------------------------------------------------------------------
                         slack                                  5.107    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.367ns  (arrival time - required time)
  Source:                 sync_resets_i/rst_block[4].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/busy_r_reg/CLR
                            (removal check against rising-edge clock sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (sclk rise@0.000ns - sclk rise@0.000ns)
  Data Path Delay:        0.312ns  (logic 0.100ns (32.040%)  route 0.212ns (67.960%))
  Logic Levels:           0  
  Clock Path Skew:        0.014ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.602ns
    Source Clock Delay      (SCD):    2.082ns
    Clock Pessimism Removal (CPR):    0.506ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.666     0.666    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X1Y3       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.050     0.716 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.774     1.490    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y22       BUFG (Prop_bufg_I_O)         0.026     1.516 r  clocks393_i/sync_clk_i/clk1x_i/O
                         net (fo=1443, routed)        0.566     2.082    sync_resets_i/rst_block[4].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/camsync_clk
    SLICE_X101Y148       FDRE                                         r  sync_resets_i/rst_block[4].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y148       FDRE (Prop_fdre_C_Q)         0.100     2.182 f  sync_resets_i/rst_block[4].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q
                         net (fo=3, routed)           0.212     2.394    timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/rst[0]
    SLICE_X101Y149       FDCE                                         f  timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/busy_r_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock sclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.903     0.903    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X1Y3       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.053     0.956 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.843     1.799    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y22       BUFG (Prop_bufg_I_O)         0.030     1.829 r  clocks393_i/sync_clk_i/clk1x_i/O
                         net (fo=1443, routed)        0.773     2.602    timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/camsync_clk
    SLICE_X101Y149       FDCE                                         r  timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/busy_r_reg/C
                         clock pessimism             -0.506     2.096    
    SLICE_X101Y149       FDCE (Remov_fdce_C_CLR)     -0.069     2.027    timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/busy_r_reg
  -------------------------------------------------------------------
                         required time                         -2.027    
                         arrival time                           2.394    
  -------------------------------------------------------------------
                         slack                                  0.367    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  usrclk2
  To Clock:  usrclk2

Setup :            0  Failing Endpoints,  Worst Slack        6.352ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.984ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             6.352ns  (required time - arrival time)
  Source:                 sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
  Destination:            sata_top/ahci_sata_layers_i/dbg_was_link5_i/in_reg_reg/CLR
                            (recovery check against rising-edge clock usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            13.333ns  (usrclk2 rise@13.333ns - usrclk2 rise@0.000ns)
  Data Path Delay:        6.500ns  (logic 0.322ns (4.953%)  route 6.178ns (95.047%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        -0.190ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.146ns = ( 16.479 - 13.333 ) 
    Source Clock Delay      (SCD):    3.627ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock usrclk2 rise edge)    0.000     0.000 r  
    SLICE_X61Y48         FDRE                         0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           1.917     1.917    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.120     2.037 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        1.590     3.627    sata_top/ahci_sata_layers_i/phy/rxdata_reg[0]__0
    SLICE_X61Y44         FDCE                                         r  sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X61Y44         FDCE (Prop_fdce_C_Q)         0.269     3.896 r  sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[0]/Q
                         net (fo=2, routed)           0.473     4.368    sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg_n_0_[0]
    SLICE_X60Y44         LUT3 (Prop_lut3_I0_O)        0.053     4.421 f  sata_top/ahci_sata_layers_i/phy/was_rst_i_1/O
                         net (fo=278, routed)         5.706    10.127    sata_top/ahci_sata_layers_i/dbg_was_link5_i/sata_reset_done_r_reg[0]
    SLICE_X43Y164        FDCE                                         f  sata_top/ahci_sata_layers_i/dbg_was_link5_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock usrclk2 rise edge)   13.333    13.333 r  
    SLICE_X61Y48         FDRE                         0.000    13.333 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           1.633    14.966    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.113    15.079 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        1.400    16.479    sata_top/ahci_sata_layers_i/dbg_was_link5_i/usrclk2_r_reg
    SLICE_X43Y164        FDCE                                         r  sata_top/ahci_sata_layers_i/dbg_was_link5_i/in_reg_reg/C
                         clock pessimism              0.291    16.770    
                         clock uncertainty           -0.035    16.734    
    SLICE_X43Y164        FDCE (Recov_fdce_C_CLR)     -0.255    16.479    sata_top/ahci_sata_layers_i/dbg_was_link5_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                         16.479    
                         arrival time                         -10.127    
  -------------------------------------------------------------------
                         slack                                  6.352    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.984ns  (arrival time - required time)
  Source:                 sata_top/ahci_top_i/ahci_dma_i/abort_busy_mclk_reg/C
                            (rising edge-triggered cell FDRE clocked by usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
  Destination:            sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/in_reg_reg/CLR
                            (removal check against rising-edge clock usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (usrclk2 rise@0.000ns - usrclk2 rise@0.000ns)
  Data Path Delay:        0.927ns  (logic 0.128ns (13.813%)  route 0.799ns (86.187%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.012ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.798ns
    Source Clock Delay      (SCD):    1.439ns
    Clock Pessimism Removal (CPR):    0.347ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock usrclk2 rise edge)    0.000     0.000 r  
    SLICE_X61Y48         FDRE                         0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           0.886     0.886    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.026     0.912 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        0.527     1.439    sata_top/ahci_top_i/ahci_dma_i/usrclk2_r_reg
    SLICE_X47Y133        FDRE                                         r  sata_top/ahci_top_i/ahci_dma_i/abort_busy_mclk_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y133        FDRE (Prop_fdre_C_Q)         0.100     1.539 f  sata_top/ahci_top_i/ahci_dma_i/abort_busy_mclk_reg/Q
                         net (fo=18, routed)          0.395     1.934    sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/ahci_dma_rd_stuff_i/abort_busy_mclk_reg
    SLICE_X46Y129        LUT2 (Prop_lut2_I0_O)        0.028     1.962 f  sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/ahci_dma_rd_stuff_i/dout_vld_r[1]_i_1/O
                         net (fo=15, routed)          0.404     2.365    sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/abort_busy_mclk_reg
    SLICE_X45Y133        FDCE                                         f  sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock usrclk2 rise edge)    0.000     0.000 r  
    SLICE_X61Y48         FDRE                         0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           1.037     1.037    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.030     1.067 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        0.731     1.798    sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/usrclk2_r_reg
    SLICE_X45Y133        FDCE                                         r  sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/in_reg_reg/C
                         clock pessimism             -0.347     1.451    
    SLICE_X45Y133        FDCE (Remov_fdce_C_CLR)     -0.069     1.382    sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                         -1.382    
                         arrival time                           2.365    
  -------------------------------------------------------------------
                         slack                                  0.984    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  xclk
  To Clock:  xclk

Setup :            0  Failing Endpoints,  Worst Slack        0.616ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.498ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.616ns  (required time - arrival time)
  Source:                 sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            compressor393_i/cmprs_channel_block[0].jp_channel_i/cmprs_frame_sync_i/last_mb_started_i/in_reg_reg/CLR
                            (recovery check against rising-edge clock xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            4.167ns  (xclk rise@4.167ns - xclk rise@0.000ns)
  Data Path Delay:        3.327ns  (logic 0.269ns (8.086%)  route 3.058ns (91.914%))
  Logic Levels:           0  
  Clock Path Skew:        0.098ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.019ns = ( 9.186 - 4.167 ) 
    Source Clock Delay      (SCD):    5.248ns
    Clock Pessimism Removal (CPR):    0.327ns
  Clock Uncertainty:      0.067ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.114ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock xclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.784     1.784    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X1Y3       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.088     1.872 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           1.868     3.740    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.120     3.860 r  clocks393_i/xclk_i/clk1x_i/O
                         net (fo=13492, routed)       1.388     5.248    sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/pwrdwn_clk_reg[0]
    SLICE_X72Y72         FDRE                                         r  sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X72Y72         FDRE (Prop_fdre_C_Q)         0.269     5.517 f  sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q
                         net (fo=116, routed)         3.058     8.575    compressor393_i/cmprs_channel_block[0].jp_channel_i/cmprs_frame_sync_i/last_mb_started_i/Q[0]
    SLICE_X45Y38         FDCE                                         f  compressor393_i/cmprs_channel_block[0].jp_channel_i/cmprs_frame_sync_i/last_mb_started_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock xclk rise edge)       4.167     4.167 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     4.167 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.593     5.760    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X1Y3       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.083     5.843 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           1.754     7.597    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.113     7.710 r  clocks393_i/xclk_i/clk1x_i/O
                         net (fo=13492, routed)       1.476     9.186    compressor393_i/cmprs_channel_block[0].jp_channel_i/cmprs_frame_sync_i/last_mb_started_i/xclk
    SLICE_X45Y38         FDCE                                         r  compressor393_i/cmprs_channel_block[0].jp_channel_i/cmprs_frame_sync_i/last_mb_started_i/in_reg_reg/C
                         clock pessimism              0.327     9.513    
                         clock uncertainty           -0.067     9.445    
    SLICE_X45Y38         FDCE (Recov_fdce_C_CLR)     -0.255     9.190    compressor393_i/cmprs_channel_block[0].jp_channel_i/cmprs_frame_sync_i/last_mb_started_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                          9.190    
                         arrival time                          -8.575    
  -------------------------------------------------------------------
                         slack                                  0.616    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.498ns  (arrival time - required time)
  Source:                 sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            compressor393_i/cmprs_channel_block[1].jp_channel_i/cmprs_out_fifo_i/written32b_i/in_reg_reg/CLR
                            (removal check against rising-edge clock xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (xclk rise@0.000ns - xclk rise@0.000ns)
  Data Path Delay:        0.481ns  (logic 0.100ns (20.784%)  route 0.381ns (79.216%))
  Logic Levels:           0  
  Clock Path Skew:        0.033ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.571ns
    Source Clock Delay      (SCD):    2.057ns
    Clock Pessimism Removal (CPR):    0.481ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock xclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.666     0.666    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X1Y3       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.050     0.716 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           0.774     1.490    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     1.516 r  clocks393_i/xclk_i/clk1x_i/O
                         net (fo=13492, routed)       0.541     2.057    sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/pwrdwn_clk_reg[0]
    SLICE_X72Y72         FDRE                                         r  sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X72Y72         FDRE (Prop_fdre_C_Q)         0.100     2.157 f  sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q
                         net (fo=116, routed)         0.381     2.538    compressor393_i/cmprs_channel_block[1].jp_channel_i/cmprs_out_fifo_i/written32b_i/regs_reg[1][0]
    SLICE_X70Y66         FDCE                                         f  compressor393_i/cmprs_channel_block[1].jp_channel_i/cmprs_out_fifo_i/written32b_i/in_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock xclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y23       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.903     0.903    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X1Y3       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.053     0.956 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           0.843     1.799    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.030     1.829 r  clocks393_i/xclk_i/clk1x_i/O
                         net (fo=13492, routed)       0.742     2.571    compressor393_i/cmprs_channel_block[1].jp_channel_i/cmprs_out_fifo_i/written32b_i/xclk
    SLICE_X70Y66         FDCE                                         r  compressor393_i/cmprs_channel_block[1].jp_channel_i/cmprs_out_fifo_i/written32b_i/in_reg_reg/C
                         clock pessimism             -0.481     2.090    
    SLICE_X70Y66         FDCE (Remov_fdce_C_CLR)     -0.050     2.040    compressor393_i/cmprs_channel_block[1].jp_channel_i/cmprs_out_fifo_i/written32b_i/in_reg_reg
  -------------------------------------------------------------------
                         required time                         -2.040    
                         arrival time                           2.538    
  -------------------------------------------------------------------
                         slack                                  0.498