x393_vospi.timing_summary_impl 253 KB
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Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
4
| Date         : Tue Apr 30 13:07:51 2019
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89
| Host         : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS
| Command      : report_timing_summary -file vivado_build/x393.timing_summary_impl
| Design       : x393
| Device       : 7z030-fbg484
| Speed File   : -1  PRODUCTION 1.11 2014-09-11
------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  false

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        



check_timing report

Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops

1. checking no_clock
--------------------
 There are 16 register/latch pins with no clock driven by root clock pin: DQSL (HIGH)

 There are 16 register/latch pins with no clock driven by root clock pin: DQSU (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: ffclk1p (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: memclk (HIGH)


2. checking constant_clock
--------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock
-----------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints
--------------------------------------------
 There are 20 pins that are not constrained for maximum delay. (HIGH)

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay
--------------------------
 There are 90 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay
---------------------------
90
 There are 99 ports with no output delay specified. (HIGH)
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock
--------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks
----------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops
-----------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay
--------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay
---------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops
------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
135
      0.079        0.000                      0               149132        0.016        0.000                      0               149132        0.264        0.000                       0                 60698  
136 137


138
All user specified timing constraints are met.
139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock           Waveform(ns)         Period(ns)      Frequency(MHz)
-----           ------------         ----------      --------------
axi_aclk        {0.000 10.000}       20.000          50.000          
  axihp_clk     {0.000 3.333}        6.667           150.000         
  clk_fb        {0.000 10.000}       20.000          50.000          
  ddr3_clk      {0.000 1.250}        2.500           400.000         
  ddr3_clk_div  {0.000 2.500}        5.000           200.000         
  ddr3_clk_ref  {0.000 2.500}        5.000           200.000         
  ddr3_mclk     {1.250 3.750}        5.000           200.000         
  ddr3_sdclk    {0.000 1.250}        2.500           400.000         
  multi_clkfb   {0.000 10.000}       20.000          50.000          
  sclk          {0.000 5.000}        10.000          100.000         
  xclk          {0.000 2.083}        4.167           240.000         
ffclk0          {0.000 20.833}       41.667          24.000          
  clkfb         {0.000 20.833}       41.667          24.000          
  pclk          {0.000 50.000}       100.001         10.000          
gtrefclk        {0.000 3.333}        6.666           150.015         
rx_clk          {0.000 3.333}        6.666           150.015         
txoutclk        {0.000 3.333}        6.666           150.015         
usrclk2         {0.000 6.666}        13.333          75.002          


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock               WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----               -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
175 176
axi_aclk             13.268        0.000                      0                 2685        0.044        0.000                      0                 2685        7.000        0.000                       0                   737  
  axihp_clk           0.531        0.000                      0                10217        0.056        0.000                      0                10217        0.267        0.000                       0                  3863  
177 178
  clk_fb                                                                                                                                                         18.751        0.000                       0                     2  
  ddr3_clk                                                                                                                                                        0.279        0.000                       0                    45  
179
  ddr3_clk_div        0.362        0.000                      0                 2158        0.138        0.000                      0                 2158        1.389        0.000                       0                   755  
180
  ddr3_clk_ref                                                                                                                                                    0.264        0.000                       0                     3  
181
  ddr3_mclk           0.191        0.000                      0                81120        0.026        0.000                      0                81120        1.590        0.000                       0                 32764  
182 183
  ddr3_sdclk                                                                                                                                                      1.092        0.000                       0                     3  
  multi_clkfb                                                                                                                                                    18.751        0.000                       0                     2  
184 185 186
  sclk                4.234        0.000                      0                 2736        0.044        0.000                      0                 2736        4.090        0.000                       0                  1349  
  xclk                0.079        0.000                      0                33078        0.033        0.000                      0                33078        0.875        0.000                       0                 13490  
ffclk0               40.950        0.000                      0                    1        0.233        0.000                      0                    1       10.833        0.000                       0                     3  
187
  clkfb                                                                                                                                                          10.966        0.000                       0                     2  
188 189 190 191 192
  pclk               42.687        0.000                      0                10525        0.016        0.000                      0                10525       49.090        0.000                       0                  5164  
gtrefclk              4.119        0.000                      0                   45        0.262        0.000                      0                   45        2.553        0.000                       0                    25  
rx_clk                0.497        0.000                      0                  916        0.055        0.000                      0                  916        2.423        0.000                       0                   329  
txoutclk              2.153        0.000                      0                  232        0.123        0.000                      0                  232        2.666        0.000                       0                   138  
usrclk2               4.057        0.000                      0                 4576        0.063        0.000                      0                 4576        5.756        0.000                       0                  2024  
193 194 195 196 197 198 199 200 201


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
202 203 204
ddr3_clk_div  ddr3_clk            0.272        0.000                      0                   23        0.240        0.000                      0                   23  
ddr3_mclk     ddr3_clk_div        0.106        0.000                      0                  146        1.452        0.000                      0                  146  
ddr3_clk_div  ddr3_mclk           2.829        0.000                      0                   76        0.141        0.000                      0                   76  
205 206 207 208 209 210 211 212 213


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group         From Clock         To Clock               WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------         ----------         --------               -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
214 215 216 217 218 219
**async_default**  axihp_clk          axihp_clk                1.752        0.000                      0                   23        0.588        0.000                      0                   23  
**async_default**  ddr3_mclk          ddr3_mclk                0.639        0.000                      0                  461        0.286        0.000                      0                  461  
**async_default**  pclk               pclk                    92.425        0.000                      0                   20        0.440        0.000                      0                   20  
**async_default**  sclk               sclk                     7.406        0.000                      0                   16        0.291        0.000                      0                   16  
**async_default**  usrclk2            usrclk2                  5.054        0.000                      0                    7        0.790        0.000                      0                    7  
**async_default**  xclk               xclk                     0.679        0.000                      0                   72        0.421        0.000                      0                   72  
220 221 222 223 224 225 226 227 228 229 230 231


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  axi_aclk
  To Clock:  axi_aclk

232
Setup :            0  Failing Endpoints,  Worst Slack       13.268ns,  Total Violation        0.000ns
233
Hold  :            0  Failing Endpoints,  Worst Slack        0.044ns,  Total Violation        0.000ns
234 235 236 237 238 239
PW    :            0  Failing Endpoints,  Worst Slack        7.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
240 241 242 243
Slack (MET) :             13.268ns  (required time - arrival time)
  Source:                 axibram_write_i/wdata_i/out_full_reg/C
                            (rising edge-triggered cell FDRE clocked by axi_aclk  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            mcntrl393_i/cmd_we_reg/D
244 245 246 247
                            (rising edge-triggered cell FDRE clocked by axi_aclk  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             axi_aclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            20.000ns  (axi_aclk rise@20.000ns - axi_aclk rise@0.000ns)
248 249 250 251 252 253
  Data Path Delay:        6.311ns  (logic 0.505ns (8.002%)  route 5.806ns (91.998%))
  Logic Levels:           2  (LUT2=1 LUT3=1)
  Clock Path Skew:        -0.235ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.328ns = ( 21.328 - 20.000 ) 
    Source Clock Delay      (SCD):    1.573ns
    Clock Pessimism Removal (CPR):    0.010ns
254 255 256 257 258 259 260 261 262 263 264
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock axi_aclk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
265 266
                         net (fo=738, routed)         1.573     1.573    axibram_write_i/wdata_i/axi_clk
    SLICE_X33Y150        FDRE                                         r  axibram_write_i/wdata_i/out_full_reg/C
267
  -------------------------------------------------------------------    -------------------
268 269 270 271 272 273 274
    SLICE_X33Y150        FDRE (Prop_fdre_C_Q)         0.269     1.842 r  axibram_write_i/wdata_i/out_full_reg/Q
                         net (fo=8, routed)           1.246     3.088    axibram_write_i/wdata_i/w_nempty_2
    SLICE_X33Y150        LUT3 (Prop_lut3_I1_O)        0.056     3.144 r  axibram_write_i/wdata_i/buf_waddr[9]_i_1/O
                         net (fo=48, routed)          3.372     6.516    axibram_write_i/wdata_i/buf_wdata_reg[0]
    SLICE_X64Y126        LUT2 (Prop_lut2_I0_O)        0.180     6.696 r  axibram_write_i/wdata_i/cmd_we_i_1/O
                         net (fo=1, routed)           1.188     7.884    mcntrl393_i/cmd_we0
    SLICE_X92Y112        FDRE                                         r  mcntrl393_i/cmd_we_reg/D
275 276 277 278 279
  -------------------------------------------------------------------    -------------------

                         (clock axi_aclk rise edge)
                                                     20.000    20.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000    20.000 r  clocks393_i/bufg_axi_aclk_i/O
280 281 282 283 284
                         net (fo=738, routed)         1.328    21.328    mcntrl393_i/axi_clk
    SLICE_X92Y112        FDRE                                         r  mcntrl393_i/cmd_we_reg/C
                         clock pessimism              0.010    21.338    
                         clock uncertainty           -0.035    21.303    
    SLICE_X92Y112        FDRE (Setup_fdre_C_D)       -0.151    21.152    mcntrl393_i/cmd_we_reg
285
  -------------------------------------------------------------------
286 287
                         required time                         21.152    
                         arrival time                          -7.884    
288
  -------------------------------------------------------------------
289
                         slack                                 13.268    
290 291 292 293 294 295 296





Min Delay Paths
--------------------------------------------------------------------------------------
297
Slack (MET) :             0.044ns  (arrival time - required time)
298
  Source:                 axibram_read_i/raddr_i/inreg_reg[22]/C
299
                            (rising edge-triggered cell FDRE clocked by axi_aclk  {rise@0.000ns fall@10.000ns period=20.000ns})
300
  Destination:            axibram_read_i/raddr_i/ram_reg_0_15_18_23/RAMC/I
301 302 303 304
                            (rising edge-triggered cell RAMD32 clocked by axi_aclk  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             axi_aclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (axi_aclk rise@0.000ns - axi_aclk rise@0.000ns)
305
  Data Path Delay:        0.146ns  (logic 0.091ns (62.374%)  route 0.055ns (37.626%))
306
  Logic Levels:           0  
307
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
308 309
    Destination Clock Delay (DCD):    0.755ns
    Source Clock Delay      (SCD):    0.549ns
310
    Clock Pessimism Removal (CPR):    0.195ns
311 312 313 314 315 316

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock axi_aclk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
317 318
                         net (fo=738, routed)         0.549     0.549    axibram_read_i/raddr_i/axi_clk
    SLICE_X27Y142        FDRE                                         r  axibram_read_i/raddr_i/inreg_reg[22]/C
319
  -------------------------------------------------------------------    -------------------
320 321 322
    SLICE_X27Y142        FDRE (Prop_fdre_C_Q)         0.091     0.640 r  axibram_read_i/raddr_i/inreg_reg[22]/Q
                         net (fo=1, routed)           0.055     0.695    axibram_read_i/raddr_i/ram_reg_0_15_18_23/DIC0
    SLICE_X26Y142        RAMD32                                       r  axibram_read_i/raddr_i/ram_reg_0_15_18_23/RAMC/I
323 324 325 326 327
  -------------------------------------------------------------------    -------------------

                         (clock axi_aclk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
328 329 330 331 332
                         net (fo=738, routed)         0.755     0.755    axibram_read_i/raddr_i/ram_reg_0_15_18_23/WCLK
    SLICE_X26Y142        RAMD32                                       r  axibram_read_i/raddr_i/ram_reg_0_15_18_23/RAMC/CLK
                         clock pessimism             -0.195     0.560    
    SLICE_X26Y142        RAMD32 (Hold_ramd32_CLK_I)
                                                      0.091     0.651    axibram_read_i/raddr_i/ram_reg_0_15_18_23/RAMC
333
  -------------------------------------------------------------------
334 335
                         required time                         -0.651    
                         arrival time                           0.695    
336
  -------------------------------------------------------------------
337
                         slack                                  0.044    
338 339 340 341 342 343 344 345 346 347 348 349 350





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         axi_aclk
Waveform(ns):       { 0.000 10.000 }
Period(ns):         20.000
Sources:            { clocks393_i/bufg_axi_aclk_i/O }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
351
Min Period        n/a     RAMB36E1/CLKBWRCLK  n/a            2.183         20.000      17.817     RAMB36_X2Y28    cmd_readback_i/ram_reg_0/CLKBWRCLK
352 353 354 355 356 357 358 359 360 361
Max Period        n/a     PLLE2_ADV/CLKIN1    n/a            52.633        20.000      32.633     PLLE2_ADV_X0Y0  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKIN1
Low Pulse Width   Slow    PLLE2_ADV/CLKIN1    n/a            3.000         10.000      7.000      PLLE2_ADV_X0Y0  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKIN1
High Pulse Width  Slow    PLLE2_ADV/CLKIN1    n/a            3.000         10.000      7.000      PLLE2_ADV_X0Y0  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKIN1



---------------------------------------------------------------------------------------------------
From Clock:  axihp_clk
  To Clock:  axihp_clk

362 363
Setup :            0  Failing Endpoints,  Worst Slack        0.531ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.056ns,  Total Violation        0.000ns
364 365 366 367 368 369
PW    :            0  Failing Endpoints,  Worst Slack        0.267ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
370
Slack (MET) :             0.531ns  (required time - arrival time)
371
  Source:                 sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
372
                            (rising edge-triggered cell FDRE clocked by axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
373
  Destination:            sata_top/ahci_sata_layers_i/phy/gtx_wrap/drp_other_registers_i/drp_register2_r_reg[1]/R
374 375 376 377
                            (rising edge-triggered cell FDRE clocked by axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             axihp_clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (axihp_clk rise@6.667ns - axihp_clk rise@0.000ns)
378 379 380 381 382
  Data Path Delay:        5.640ns  (logic 0.269ns (4.769%)  route 5.371ns (95.231%))
  Logic Levels:           0  
  Clock Path Skew:        -0.057ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.316ns = ( 11.983 - 6.667 ) 
    Source Clock Delay      (SCD):    5.618ns
383
    Clock Pessimism Removal (CPR):    0.245ns
384 385 386 387 388 389 390 391 392 393 394 395 396 397 398
  Clock Uncertainty:      0.071ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.124ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock axihp_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.807     1.807    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.088     1.895 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           2.009     3.904    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.120     4.024 r  clocks393_i/hclk_i/clk1x_i/O
399 400
                         net (fo=3868, routed)        1.594     5.618    sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/hclk
    SLICE_X27Y170        FDRE                                         r  sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
401
  -------------------------------------------------------------------    -------------------
402 403 404
    SLICE_X27Y170        FDRE (Prop_fdre_C_Q)         0.269     5.887 r  sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q
                         net (fo=335, routed)         5.371    11.258    sata_top/ahci_sata_layers_i/phy/gtx_wrap/drp_other_registers_i/regs_reg[1][0]
    SLICE_X111Y13        FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/drp_other_registers_i/drp_register2_r_reg[1]/R
405 406 407 408 409 410 411 412 413 414
  -------------------------------------------------------------------    -------------------

                         (clock axihp_clk rise edge)
                                                      6.667     6.667 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     6.667 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.672     8.339    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.083     8.422 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.911    10.333    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.113    10.446 r  clocks393_i/hclk_i/clk1x_i/O
415 416 417 418 419
                         net (fo=3868, routed)        1.537    11.983    sata_top/ahci_sata_layers_i/phy/gtx_wrap/drp_other_registers_i/hclk
    SLICE_X111Y13        FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/drp_other_registers_i/drp_register2_r_reg[1]/C
                         clock pessimism              0.245    12.228    
                         clock uncertainty           -0.071    12.156    
    SLICE_X111Y13        FDRE (Setup_fdre_C_R)       -0.367    11.789    sata_top/ahci_sata_layers_i/phy/gtx_wrap/drp_other_registers_i/drp_register2_r_reg[1]
420
  -------------------------------------------------------------------
421 422
                         required time                         11.789    
                         arrival time                         -11.258    
423
  -------------------------------------------------------------------
424
                         slack                                  0.531    
425 426 427 428 429 430 431





Min Delay Paths
--------------------------------------------------------------------------------------
432 433
Slack (MET) :             0.056ns  (arrival time - required time)
  Source:                 mult_saxi_wr_i/fifo_same_clock_i/inreg_reg[26]/C
434
                            (rising edge-triggered cell FDRE clocked by axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
435
  Destination:            mult_saxi_wr_i/fifo_same_clock_i/ram_reg_0_15_24_29/RAMB/I
436
                            (rising edge-triggered cell RAMD32 clocked by axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
437 438 439
  Path Group:             axihp_clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (axihp_clk rise@0.000ns - axihp_clk rise@0.000ns)
440
  Data Path Delay:        0.201ns  (logic 0.100ns (49.804%)  route 0.101ns (50.196%))
441
  Logic Levels:           0  
442 443 444 445
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.664ns
    Source Clock Delay      (SCD):    2.132ns
    Clock Pessimism Removal (CPR):    0.519ns
446 447 448 449 450 451 452 453 454 455 456

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock axihp_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.657     0.657    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.050     0.707 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.771     1.478    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     1.504 r  clocks393_i/hclk_i/clk1x_i/O
457 458
                         net (fo=3868, routed)        0.628     2.132    mult_saxi_wr_i/fifo_same_clock_i/hclk
    SLICE_X31Y182        FDRE                                         r  mult_saxi_wr_i/fifo_same_clock_i/inreg_reg[26]/C
459
  -------------------------------------------------------------------    -------------------
460 461 462
    SLICE_X31Y182        FDRE (Prop_fdre_C_Q)         0.100     2.232 r  mult_saxi_wr_i/fifo_same_clock_i/inreg_reg[26]/Q
                         net (fo=1, routed)           0.101     2.333    mult_saxi_wr_i/fifo_same_clock_i/ram_reg_0_15_24_29/DIB0
    SLICE_X30Y183        RAMD32                                       r  mult_saxi_wr_i/fifo_same_clock_i/ram_reg_0_15_24_29/RAMB/I
463 464 465 466 467 468 469 470 471 472
  -------------------------------------------------------------------    -------------------

                         (clock axihp_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.889     0.889    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.053     0.942 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.840     1.782    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.030     1.812 r  clocks393_i/hclk_i/clk1x_i/O
473 474 475 476 477
                         net (fo=3868, routed)        0.852     2.664    mult_saxi_wr_i/fifo_same_clock_i/ram_reg_0_15_24_29/WCLK
    SLICE_X30Y183        RAMD32                                       r  mult_saxi_wr_i/fifo_same_clock_i/ram_reg_0_15_24_29/RAMB/CLK
                         clock pessimism             -0.519     2.145    
    SLICE_X30Y183        RAMD32 (Hold_ramd32_CLK_I)
                                                      0.132     2.277    mult_saxi_wr_i/fifo_same_clock_i/ram_reg_0_15_24_29/RAMB
478
  -------------------------------------------------------------------
479 480
                         required time                         -2.277    
                         arrival time                           2.333    
481
  -------------------------------------------------------------------
482
                         slack                                  0.056    
483 484 485 486 487 488 489 490 491 492 493 494 495 496 497





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         axihp_clk
Waveform(ns):       { 0.000 3.333 }
Period(ns):         6.667
Sources:            { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 }

Check Type        Corner  Lib Pin               Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location            Pin
Min Period        n/a     GTXE2_CHANNEL/DRPCLK  n/a            6.400         6.667       0.267      GTXE2_CHANNEL_X0Y0  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/DRPCLK
Max Period        n/a     PLLE2_ADV/CLKOUT0     n/a            160.000       6.667       153.333    PLLE2_ADV_X0Y0      clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
498 499
Low Pulse Width   Slow    RAMD32/CLK            n/a            0.910         3.333       2.423      SLICE_X18Y83        compressor393_i/cmprs_afi0_mux_i/cmprs_afi_mux_ptr_wresp_i/len_ram_reg_0_3_24_26/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK            n/a            0.910         3.333       2.423      SLICE_X38Y134       sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/fifo_ram_reg_0_7_0_5/RAMA/CLK
500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552



---------------------------------------------------------------------------------------------------
From Clock:  clk_fb
  To Clock:  clk_fb

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack       18.751ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_fb
Waveform(ns):       { 0.000 10.000 }
Period(ns):         20.000
Sources:            { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT }

Check Type  Corner  Lib Pin              Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            1.249         20.000      18.751     MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT
Max Period  n/a     MMCME2_ADV/CLKFBIN   n/a            100.000       20.000      80.000     MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBIN



---------------------------------------------------------------------------------------------------
From Clock:  ddr3_clk
  To Clock:  ddr3_clk

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.279ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ddr3_clk
Waveform(ns):       { 0.000 1.250 }
Period(ns):         2.500
Sources:            { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1 }

Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     BUFR/I              n/a            2.221         2.500       0.279      BUFR_X1Y8        mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_bufr_i/I
Max Period  n/a     MMCME2_ADV/CLKOUT1  n/a            213.360       2.500       210.860    MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1



---------------------------------------------------------------------------------------------------
From Clock:  ddr3_clk_div
  To Clock:  ddr3_clk_div

553 554
Setup :            0  Failing Endpoints,  Worst Slack        0.362ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.138ns,  Total Violation        0.000ns
555 556 557 558 559 560
PW    :            0  Failing Endpoints,  Worst Slack        1.389ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
561
Slack (MET) :             0.362ns  (required time - arrival time)
562 563
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/rst_reg/C
                            (rising edge-triggered cell FDRE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
564
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[7].dq_i/oserdes_i/oserdes_i/RST
565 566 567 568
                            (rising edge-triggered cell OSERDESE2 clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             ddr3_clk_div
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (ddr3_clk_div rise@5.000ns - ddr3_clk_div rise@0.000ns)
569
  Data Path Delay:        3.832ns  (logic 0.308ns (8.039%)  route 3.524ns (91.962%))
570
  Logic Levels:           0  
571 572 573
  Clock Path Skew:        0.024ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.634ns = ( 8.634 - 5.000 ) 
    Source Clock Delay      (SCD):    3.866ns
574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589
    Clock Pessimism Removal (CPR):    0.256ns
  Clock Uncertainty:      0.085ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_clk_div rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     1.575    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.088     1.663 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           1.106     2.769    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.377     3.146 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
590 591
                         net (fo=753, routed)         0.720     3.866    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/CLK
    SLICE_X96Y107        FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/rst_reg/C
592
  -------------------------------------------------------------------    -------------------
593 594 595
    SLICE_X96Y107        FDRE (Prop_fdre_C_Q)         0.308     4.174 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/rst_reg/Q
                         net (fo=786, routed)         3.524     7.698    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[7].dq_i/oserdes_i/tin
    OLOGIC_X1Y129        OSERDESE2                                    r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[7].dq_i/oserdes_i/oserdes_i/RST
596 597 598 599 600 601 602 603 604 605
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_clk_div rise edge)
                                                      5.000     5.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     5.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     6.437    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.083     6.520 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           1.016     7.536    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.370     7.906 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
606 607 608 609 610 611
                         net (fo=753, routed)         0.728     8.634    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[7].dq_i/oserdes_i/psincdec_reg_0
    OLOGIC_X1Y129        OSERDESE2                                    r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[7].dq_i/oserdes_i/oserdes_i/CLKDIV
                         clock pessimism              0.256     8.890    
                         clock uncertainty           -0.085     8.805    
    OLOGIC_X1Y129        OSERDESE2 (Setup_oserdese2_CLKDIV_RST)
                                                     -0.745     8.060    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[7].dq_i/oserdes_i/oserdes_i
612
  -------------------------------------------------------------------
613 614
                         required time                          8.060    
                         arrival time                          -7.698    
615
  -------------------------------------------------------------------
616
                         slack                                  0.362    
617 618 619 620 621 622 623





Min Delay Paths
--------------------------------------------------------------------------------------
624 625
Slack (MET) :             0.138ns  (arrival time - required time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[5].dq_i/dq_out_dly_i/fdly_pre_reg[0]/C
626
                            (rising edge-triggered cell FDRE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
627
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[5].dq_i/dq_out_dly_i/fdly_reg[0]/D
628 629 630 631
                            (rising edge-triggered cell FDRE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             ddr3_clk_div
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (ddr3_clk_div rise@0.000ns - ddr3_clk_div rise@0.000ns)
632
  Data Path Delay:        0.182ns  (logic 0.118ns (64.991%)  route 0.064ns (35.009%))
633
  Logic Levels:           0  
634
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
635 636
    Destination Clock Delay (DCD):    1.734ns
    Source Clock Delay      (SCD):    1.419ns
637
    Clock Pessimism Removal (CPR):    0.304ns
638 639 640 641 642 643 644 645 646 647 648

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_clk_div rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.580     0.580    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.050     0.630 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           0.433     1.063    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.090     1.153 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
649 650
                         net (fo=753, routed)         0.266     1.419    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[5].dq_i/dq_out_dly_i/psincdec_reg
    SLICE_X118Y129       FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[5].dq_i/dq_out_dly_i/fdly_pre_reg[0]/C
651
  -------------------------------------------------------------------    -------------------
652 653 654
    SLICE_X118Y129       FDRE (Prop_fdre_C_Q)         0.118     1.537 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[5].dq_i/dq_out_dly_i/fdly_pre_reg[0]/Q
                         net (fo=2, routed)           0.064     1.601    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[5].dq_i/dq_out_dly_i/fdly_pre[0]
    SLICE_X119Y129       FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[5].dq_i/dq_out_dly_i/fdly_reg[0]/D
655 656 657 658 659 660 661 662 663 664
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_clk_div rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.796     0.796    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.053     0.849 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           0.490     1.339    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.093     1.432 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
665 666 667 668
                         net (fo=753, routed)         0.302     1.734    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[5].dq_i/dq_out_dly_i/psincdec_reg
    SLICE_X119Y129       FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[5].dq_i/dq_out_dly_i/fdly_reg[0]/C
                         clock pessimism             -0.304     1.430    
    SLICE_X119Y129       FDRE (Hold_fdre_C_D)         0.033     1.463    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[5].dq_i/dq_out_dly_i/fdly_reg[0]
669
  -------------------------------------------------------------------
670 671
                         required time                         -1.463    
                         arrival time                           1.601    
672
  -------------------------------------------------------------------
673
                         slack                                  0.138    
674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ddr3_clk_div
Waveform(ns):       { 0.000 2.500 }
Period(ns):         5.000
Sources:            { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     BUFR/I              n/a            2.221         5.000       2.779      BUFR_X1Y9        mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/I
Max Period        n/a     MMCME2_ADV/CLKOUT2  n/a            213.360       5.000       208.360    MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
Low Pulse Width   Slow    MMCME2_ADV/PSCLK    n/a            1.111         2.500       1.389      MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/PSCLK
High Pulse Width  Slow    MMCME2_ADV/PSCLK    n/a            1.111         2.500       1.389      MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/PSCLK



---------------------------------------------------------------------------------------------------
From Clock:  ddr3_clk_ref
  To Clock:  ddr3_clk_ref

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.264ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ddr3_clk_ref
Waveform(ns):       { 0.000 2.500 }
Period(ns):         5.000
Sources:            { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT5 }

Check Type  Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     IDELAYCTRL/REFCLK  n/a            3.225         5.000       1.775      IDELAYCTRL_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/idelay_ctrl_i/idelay_ctrl_i/REFCLK
Max Period  n/a     IDELAYCTRL/REFCLK  n/a            5.264         5.000       0.264      IDELAYCTRL_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/idelay_ctrl_i/idelay_ctrl_i/REFCLK



---------------------------------------------------------------------------------------------------
From Clock:  ddr3_mclk
  To Clock:  ddr3_mclk

721 722
Setup :            0  Failing Endpoints,  Worst Slack        0.191ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.026ns,  Total Violation        0.000ns
723 724 725 726 727 728
PW    :            0  Failing Endpoints,  Worst Slack        1.590ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
729 730
Slack (MET) :             0.191ns  (required time - arrival time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/wbuf_delay_reg[1]/C
731
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
732
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/run_refresh_w_d_negedge_reg/D
733
                            (falling edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
734 735
  Path Group:             ddr3_mclk
  Path Type:              Setup (Max at Slow Process Corner)
736
  Requirement:            2.500ns  (ddr3_mclk fall@3.750ns - ddr3_mclk rise@1.250ns)
737
  Data Path Delay:        2.114ns  (logic 0.375ns (17.739%)  route 1.739ns (82.261%))
738
  Logic Levels:           2  (LUT3=1 SRL16E=1)
739 740 741 742
  Clock Path Skew:        -0.080ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.474ns = ( 8.224 - 3.750 ) 
    Source Clock Delay      (SCD):    4.870ns = ( 6.120 - 1.250 ) 
    Clock Pessimism Removal (CPR):    0.316ns
743 744 745 746 747 748 749 750 751 752 753 754 755 756 757
  Clock Uncertainty:      0.085ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     2.825    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.088     2.913 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.628     4.541    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.120     4.661 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
758 759
                         net (fo=32762, routed)       1.459     6.120    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/dbg1_reg
    SLICE_X92Y99         FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/wbuf_delay_reg[1]/C
760
  -------------------------------------------------------------------    -------------------
761 762 763 764 765 766 767
    SLICE_X92Y99         FDRE (Prop_fdre_C_Q)         0.269     6.389 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/wbuf_delay_reg[1]/Q
                         net (fo=5, routed)           0.612     7.001    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/buf_wchn_dly_i/bit_block[0].dly01_16_i/Q[1]
    SLICE_X91Y99         LUT3 (Prop_lut3_I0_O)        0.053     7.054 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/buf_wchn_dly_i/bit_block[0].dly01_16_i/sr_reg[0]_srl1_i_4/O
                         net (fo=6, routed)           0.652     7.706    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/buf_wchn_dly_i/bit_block[4].dly01_16_i/wbuf_delay_reg[1]
    SLICE_X90Y99         SRL16E (Prop_srl16e_A2_Q)    0.053     7.759 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/buf_wchn_dly_i/bit_block[4].dly01_16_i/sr_reg[0]_srl1/Q
                         net (fo=1, routed)           0.475     8.234    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/run_refresh_w_d
    SLICE_X91Y99         FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/run_refresh_w_d_negedge_reg/D
768 769
  -------------------------------------------------------------------    -------------------

770 771 772 773
                         (clock ddr3_mclk fall edge)
                                                      3.750     3.750 f  
    BUFGCTRL_X0Y17       BUFG                         0.000     3.750 f  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     5.187    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
774
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
775 776 777
                                                      0.083     5.270 f  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.544     6.814    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.113     6.927 f  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
778 779 780 781 782
                         net (fo=32762, routed)       1.297     8.224    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/dbg1_reg
    SLICE_X91Y99         FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/run_refresh_w_d_negedge_reg/C  (IS_INVERTED)
                         clock pessimism              0.316     8.540    
                         clock uncertainty           -0.085     8.455    
    SLICE_X91Y99         FDRE (Setup_fdre_C_D)       -0.030     8.425    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/run_refresh_w_d_negedge_reg
783
  -------------------------------------------------------------------
784 785
                         required time                          8.425    
                         arrival time                          -8.234    
786
  -------------------------------------------------------------------
787
                         slack                                  0.191    
788 789 790 791 792 793 794





Min Delay Paths
--------------------------------------------------------------------------------------
795 796 797 798
Slack (MET) :             0.026ns  (arrival time - required time)
  Source:                 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_sync_i/cmd_deser_sens_sync_i/i_cmd_deser_multi/deser_r_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Destination:            sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_sync_i/cmd_data_r_reg[4]/D
799 800 801 802
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Path Group:             ddr3_mclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (ddr3_mclk rise@1.250ns - ddr3_mclk rise@1.250ns)
803
  Data Path Delay:        0.262ns  (logic 0.118ns (44.970%)  route 0.144ns (55.030%))
804
  Logic Levels:           0  
805 806 807
  Clock Path Skew:        0.189ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.274ns = ( 3.524 - 1.250 ) 
    Source Clock Delay      (SCD):    1.798ns = ( 3.048 - 1.250 ) 
808 809 810 811 812 813 814 815 816 817 818 819
    Clock Pessimism Removal (CPR):    0.287ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.580     1.830    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.050     1.880 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.559     2.439    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.465 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
820 821
                         net (fo=32762, routed)       0.583     3.048    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_sync_i/cmd_deser_sens_sync_i/i_cmd_deser_multi/mclk
    SLICE_X96Y99         FDRE                                         r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_sync_i/cmd_deser_sens_sync_i/i_cmd_deser_multi/deser_r_reg[20]/C
822
  -------------------------------------------------------------------    -------------------
823 824 825
    SLICE_X96Y99         FDRE (Prop_fdre_C_Q)         0.118     3.166 r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_sync_i/cmd_deser_sens_sync_i/i_cmd_deser_multi/deser_r_reg[20]/Q
                         net (fo=1, routed)           0.144     3.310    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_sync_i/cmd_data[4]
    SLICE_X97Y100        FDRE                                         r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_sync_i/cmd_data_r_reg[4]/D
826 827 828 829 830 831 832 833 834 835
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.796     2.046    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.053     2.099 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.623     2.722    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.030     2.752 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
836 837 838 839
                         net (fo=32762, routed)       0.772     3.524    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_sync_i/mclk
    SLICE_X97Y100        FDRE                                         r  sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_sync_i/cmd_data_r_reg[4]/C
                         clock pessimism             -0.287     3.237    
    SLICE_X97Y100        FDRE (Hold_fdre_C_D)         0.047     3.284    sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_sync_i/cmd_data_r_reg[4]
840
  -------------------------------------------------------------------
841 842
                         required time                         -3.284    
                         arrival time                           3.310    
843
  -------------------------------------------------------------------
844
                         slack                                  0.026    
845 846 847 848 849 850 851 852 853 854 855 856 857





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ddr3_mclk
Waveform(ns):       { 1.250 3.750 }
Period(ns):         5.000
Sources:            { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
858
Min Period        n/a     RAMB36E1/CLKBWRCLK  n/a            2.495         5.000       2.505      RAMB36_X5Y33     sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/sens_hist_ram_snglclk_32_i/ramt_var_w_var_r_even_i/RAMB36E1_i/CLKBWRCLK
859
Max Period        n/a     MMCME2_ADV/CLKOUT3  n/a            213.360       5.000       208.360    MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
860 861
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.910         2.500       1.590      SLICE_X114Y164   sensors393_i/sensor_channel_block[2].sensor_channel_i/lens_flat393_i/BX_ram_reg_0_3_18_20/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.910         2.500       1.590      SLICE_X106Y135   sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/scales_ram_reg_0_15_0_5/RAMA/CLK
862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914



---------------------------------------------------------------------------------------------------
From Clock:  ddr3_sdclk
  To Clock:  ddr3_sdclk

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        1.092ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ddr3_sdclk
Waveform(ns):       { 0.000 1.250 }
Period(ns):         2.500
Sources:            { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0 }

Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     BUFIO/I             n/a            1.408         2.500       1.092      BUFIO_X1Y9       mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/iclk_bufio_i/I
Max Period  n/a     MMCME2_ADV/CLKOUT0  n/a            213.360       2.500       210.860    MMCME2_ADV_X1Y2  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0



---------------------------------------------------------------------------------------------------
From Clock:  multi_clkfb
  To Clock:  multi_clkfb

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack       18.751ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         multi_clkfb
Waveform(ns):       { 0.000 10.000 }
Period(ns):         20.000
Sources:            { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT }

Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period  n/a     PLLE2_ADV/CLKFBOUT  n/a            1.249         20.000      18.751     PLLE2_ADV_X0Y0  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT
Max Period  n/a     PLLE2_ADV/CLKFBIN   n/a            52.633        20.000      32.633     PLLE2_ADV_X0Y0  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKFBIN



---------------------------------------------------------------------------------------------------
From Clock:  sclk
  To Clock:  sclk

915 916
Setup :            0  Failing Endpoints,  Worst Slack        4.234ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.044ns,  Total Violation        0.000ns
917 918 919 920 921 922
PW    :            0  Failing Endpoints,  Worst Slack        4.090ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
923
Slack (MET) :             4.234ns  (required time - arrival time)
924 925 926 927 928 929 930
  Source:                 event_logger_i/i_imu_spi/sngl_wire_stb_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            event_logger_i/i_imu_spi/sngl_wire_r_reg[1]/D
                            (falling edge-triggered cell FDRE clocked by sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             sclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (sclk fall@5.000ns - sclk rise@0.000ns)
931
  Data Path Delay:        0.658ns  (logic 0.269ns (40.857%)  route 0.389ns (59.143%))
932
  Logic Levels:           0  
933 934
  Clock Path Skew:        -0.028ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.054ns = ( 10.054 - 5.000 ) 
935
    Source Clock Delay      (SCD):    5.416ns
936
    Clock Pessimism Removal (CPR):    0.334ns
937 938 939 940 941 942 943 944 945 946 947 948 949 950
  Clock Uncertainty:      0.075ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.133ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.807     1.807    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.088     1.895 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           2.009     3.904    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y7        BUFG (Prop_bufg_I_O)         0.120     4.024 r  clocks393_i/sync_clk_i/clk1x_i/O
951
                         net (fo=1347, routed)        1.392     5.416    event_logger_i/i_imu_spi/camsync_clk
952
    SLICE_X68Y142        FDRE                                         r  event_logger_i/i_imu_spi/sngl_wire_stb_reg[0]/C
953
  -------------------------------------------------------------------    -------------------
954 955 956
    SLICE_X68Y142        FDRE (Prop_fdre_C_Q)         0.269     5.685 r  event_logger_i/i_imu_spi/sngl_wire_stb_reg[0]/Q
                         net (fo=2, routed)           0.389     6.074    event_logger_i/i_imu_spi/sngl_wire_stb_reg_n_0_[0]
    SLICE_X70Y142        FDRE                                         r  event_logger_i/i_imu_spi/sngl_wire_r_reg[1]/D
957 958 959 960 961 962 963 964 965
  -------------------------------------------------------------------    -------------------

                         (clock sclk fall edge)       5.000     5.000 f  
    BUFGCTRL_X0Y17       BUFG                         0.000     5.000 f  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.672     6.672    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.083     6.755 f  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.911     8.666    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y7        BUFG (Prop_bufg_I_O)         0.113     8.779 f  clocks393_i/sync_clk_i/clk1x_i/O
966 967 968 969 970
                         net (fo=1347, routed)        1.275    10.054    event_logger_i/i_imu_spi/camsync_clk
    SLICE_X70Y142        FDRE                                         r  event_logger_i/i_imu_spi/sngl_wire_r_reg[1]/C  (IS_INVERTED)
                         clock pessimism              0.334    10.388    
                         clock uncertainty           -0.075    10.313    
    SLICE_X70Y142        FDRE (Setup_fdre_C_D)       -0.004    10.309    event_logger_i/i_imu_spi/sngl_wire_r_reg[1]
971
  -------------------------------------------------------------------
972 973
                         required time                         10.309    
                         arrival time                          -6.074    
974
  -------------------------------------------------------------------
975
                         slack                                  4.234    
976 977 978 979 980 981 982





Min Delay Paths
--------------------------------------------------------------------------------------
983 984
Slack (MET) :             0.044ns  (arrival time - required time)
  Source:                 event_logger_i/i_imu_spi/miso_reg_reg[4]/C
985
                            (rising edge-triggered cell FDRE clocked by sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
986
  Destination:            i_imu_spi/odbuf0_ram_reg_0_31_0_5/RAMC/I
987 988 989 990
                            (rising edge-triggered cell RAMD32 clocked by sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             sclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sclk rise@0.000ns - sclk rise@0.000ns)
991
  Data Path Delay:        0.146ns  (logic 0.091ns (62.374%)  route 0.055ns (37.626%))
992
  Logic Levels:           0  
993 994 995 996
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.546ns
    Source Clock Delay      (SCD):    2.032ns
    Clock Pessimism Removal (CPR):    0.503ns
997 998 999 1000 1001 1002 1003 1004 1005 1006

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.657     0.657    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.050     0.707 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.771     1.478    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y7        BUFG (Prop_bufg_I_O)         0.026     1.504 r  clocks393_i/sync_clk_i/clk1x_i/O
1007 1008
                         net (fo=1347, routed)        0.528     2.032    event_logger_i/i_imu_spi/camsync_clk
    SLICE_X55Y140        FDRE                                         r  event_logger_i/i_imu_spi/miso_reg_reg[4]/C
1009
  -------------------------------------------------------------------    -------------------
1010 1011 1012
    SLICE_X55Y140        FDRE (Prop_fdre_C_Q)         0.091     2.123 r  event_logger_i/i_imu_spi/miso_reg_reg[4]/Q
                         net (fo=2, routed)           0.055     2.178    i_imu_spi/odbuf0_ram_reg_0_31_0_5/DIC0
    SLICE_X54Y140        RAMD32                                       r  i_imu_spi/odbuf0_ram_reg_0_31_0_5/RAMC/I
1013 1014 1015 1016 1017 1018 1019 1020 1021
  -------------------------------------------------------------------    -------------------

                         (clock sclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.889     0.889    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.053     0.942 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.840     1.782    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y7        BUFG (Prop_bufg_I_O)         0.030     1.812 r  clocks393_i/sync_clk_i/clk1x_i/O
1022 1023 1024 1025 1026
                         net (fo=1347, routed)        0.734     2.546    i_imu_spi/odbuf0_ram_reg_0_31_0_5/WCLK
    SLICE_X54Y140        RAMD32                                       r  i_imu_spi/odbuf0_ram_reg_0_31_0_5/RAMC/CLK
                         clock pessimism             -0.503     2.043    
    SLICE_X54Y140        RAMD32 (Hold_ramd32_CLK_I)
                                                      0.091     2.134    i_imu_spi/odbuf0_ram_reg_0_31_0_5/RAMC
1027
  -------------------------------------------------------------------
1028 1029
                         required time                         -2.134    
                         arrival time                           2.178    
1030
  -------------------------------------------------------------------
1031
                         slack                                  0.044    
1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         sclk
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3 }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     BUFG/I             n/a            1.600         10.000      8.400      BUFGCTRL_X0Y7   clocks393_i/sync_clk_i/clk1x_i/I
Max Period        n/a     PLLE2_ADV/CLKOUT3  n/a            160.000       10.000      150.000    PLLE2_ADV_X0Y0  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
1047 1048
Low Pulse Width   Slow    RAMD32/CLK         n/a            0.910         5.000       4.090      SLICE_X50Y148   event_logger_i/i_buf_xclk_mclk16/fifo_4x16_ram_reg_0_3_6_11/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK         n/a            0.910         5.000       4.090      SLICE_X50Y146   event_logger_i/i_buf_xclk_mclk16/fifo_4x16_ram_reg_0_3_0_5/RAMA/CLK
1049 1050 1051 1052 1053 1054 1055



---------------------------------------------------------------------------------------------------
From Clock:  xclk
  To Clock:  xclk

1056 1057
Setup :            0  Failing Endpoints,  Worst Slack        0.079ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.033ns,  Total Violation        0.000ns
1058 1059 1060 1061 1062 1063
PW    :            0  Failing Endpoints,  Worst Slack        0.875ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
1064 1065
Slack (MET) :             0.079ns  (required time - arrival time)
  Source:                 compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[2].fifo_same_clock_i/outreg_reg[8]/C
1066
                            (rising edge-triggered cell FDRE clocked by xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
1067
  Destination:            compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[1].fifo_same_clock_i/ra_reg[2]/CE
1068 1069 1070 1071
                            (rising edge-triggered cell FDRE clocked by xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             xclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.167ns  (xclk rise@4.167ns - xclk rise@0.000ns)
1072 1073 1074 1075 1076 1077
  Data Path Delay:        3.673ns  (logic 0.651ns (17.724%)  route 3.022ns (82.276%))
  Logic Levels:           5  (LUT4=1 LUT6=4)
  Clock Path Skew:        -0.103ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.235ns = ( 9.402 - 4.167 ) 
    Source Clock Delay      (SCD):    5.595ns
    Clock Pessimism Removal (CPR):    0.257ns
1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091
  Clock Uncertainty:      0.067ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.114ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock xclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.807     1.807    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.088     1.895 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           2.009     3.904    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.120     4.024 r  clocks393_i/xclk_i/clk1x_i/O
1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107
                         net (fo=13488, routed)       1.571     5.595    compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[2].fifo_same_clock_i/xclk
    SLICE_X58Y25         FDRE                                         r  compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[2].fifo_same_clock_i/outreg_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y25         FDRE (Prop_fdre_C_Q)         0.282     5.877 r  compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[2].fifo_same_clock_i/outreg_reg[8]/Q
                         net (fo=4, routed)           0.701     6.578    compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[2].fifo_same_clock_i/outreg[8]
    SLICE_X56Y27         LUT6 (Prop_lut6_I0_O)        0.157     6.735 r  compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[2].fifo_same_clock_i/outreg[8]_i_6/O
                         net (fo=7, routed)           0.624     7.358    compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[2].fifo_same_clock_i/d_out_reg[0]
    SLICE_X56Y28         LUT6 (Prop_lut6_I1_O)        0.053     7.411 r  compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[2].fifo_same_clock_i/outreg[8]_i_4__3/O
                         net (fo=2, routed)           0.470     7.881    compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[3].fifo_same_clock_i/cry_ff_reg_4
    SLICE_X56Y28         LUT6 (Prop_lut6_I1_O)        0.053     7.934 r  compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[3].fifo_same_clock_i/outreg[8]_i_2__8/O
                         net (fo=9, routed)           0.467     8.401    compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[3].fifo_same_clock_i/bytes_out0
    SLICE_X59Y27         LUT6 (Prop_lut6_I0_O)        0.053     8.454 r  compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[3].fifo_same_clock_i/out_full_i_2__12/O
                         net (fo=2, routed)           0.361     8.815    compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[1].fifo_same_clock_i/out_full_reg_0
    SLICE_X56Y26         LUT4 (Prop_lut4_I0_O)        0.053     8.868 r  compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[1].fifo_same_clock_i/ra[1]_i_1__10/O
                         net (fo=4, routed)           0.400     9.268    compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[1].fifo_same_clock_i/ra[1]_i_1__10_n_0
    SLICE_X57Y26         FDRE                                         r  compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[1].fifo_same_clock_i/ra_reg[2]/CE
1108 1109 1110 1111 1112 1113 1114 1115 1116
  -------------------------------------------------------------------    -------------------

                         (clock xclk rise edge)       4.167     4.167 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     4.167 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.672     5.839    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.083     5.922 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           1.911     7.833    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.113     7.946 r  clocks393_i/xclk_i/clk1x_i/O
1117 1118 1119 1120 1121
                         net (fo=13488, routed)       1.456     9.402    compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[1].fifo_same_clock_i/xclk
    SLICE_X57Y26         FDRE                                         r  compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[1].fifo_same_clock_i/ra_reg[2]/C
                         clock pessimism              0.257     9.659    
                         clock uncertainty           -0.067     9.591    
    SLICE_X57Y26         FDRE (Setup_fdre_C_CE)      -0.244     9.347    compressor393_i/cmprs_channel_block[0].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[1].fifo_same_clock_i/ra_reg[2]
1122
  -------------------------------------------------------------------
1123 1124
                         required time                          9.347    
                         arrival time                          -9.268    
1125
  -------------------------------------------------------------------
1126
                         slack                                  0.079    
1127 1128 1129 1130 1131 1132 1133





Min Delay Paths
--------------------------------------------------------------------------------------
1134 1135 1136 1137
Slack (MET) :             0.033ns  (arrival time - required time)
  Source:                 compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[2].fifo_same_clock_i/inreg_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[2].fifo_same_clock_i/ram_reg_0_15_0_5/RAMC/I
1138
                            (rising edge-triggered cell RAMD32 clocked by xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
1139 1140 1141
  Path Group:             xclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (xclk rise@0.000ns - xclk rise@0.000ns)
1142
  Data Path Delay:        0.266ns  (logic 0.107ns (40.217%)  route 0.159ns (59.783%))
1143
  Logic Levels:           0  
1144 1145 1146 1147
  Clock Path Skew:        0.142ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.596ns
    Source Clock Delay      (SCD):    2.138ns
    Clock Pessimism Removal (CPR):    0.316ns
1148 1149 1150 1151 1152 1153 1154 1155 1156 1157

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock xclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.657     0.657    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.050     0.707 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           0.771     1.478    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.026     1.504 r  clocks393_i/xclk_i/clk1x_i/O
1158 1159
                         net (fo=13488, routed)       0.634     2.138    compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[2].fifo_same_clock_i/xclk
    SLICE_X22Y49         FDRE                                         r  compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[2].fifo_same_clock_i/inreg_reg[4]/C
1160
  -------------------------------------------------------------------    -------------------
1161 1162 1163
    SLICE_X22Y49         FDRE (Prop_fdre_C_Q)         0.107     2.245 r  compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[2].fifo_same_clock_i/inreg_reg[4]/Q
                         net (fo=1, routed)           0.159     2.404    compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[2].fifo_same_clock_i/ram_reg_0_15_0_5/DIC0
    SLICE_X22Y50         RAMD32                                       r  compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[2].fifo_same_clock_i/ram_reg_0_15_0_5/RAMC/I
1164 1165 1166 1167 1168 1169 1170 1171 1172
  -------------------------------------------------------------------    -------------------

                         (clock xclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.889     0.889    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.053     0.942 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           0.840     1.782    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.030     1.812 r  clocks393_i/xclk_i/clk1x_i/O
1173 1174 1175 1176 1177
                         net (fo=13488, routed)       0.784     2.596    compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[2].fifo_same_clock_i/ram_reg_0_15_0_5/WCLK
    SLICE_X22Y50         RAMD32                                       r  compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[2].fifo_same_clock_i/ram_reg_0_15_0_5/RAMC/CLK
                         clock pessimism             -0.316     2.280    
    SLICE_X22Y50         RAMD32 (Hold_ramd32_CLK_I)
                                                      0.091     2.371    compressor393_i/cmprs_channel_block[2].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[2].fifo_same_clock_i/ram_reg_0_15_0_5/RAMC
1178
  -------------------------------------------------------------------
1179 1180
                         required time                         -2.371    
                         arrival time                           2.404    
1181
  -------------------------------------------------------------------
1182
                         slack                                  0.033    
1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         xclk
Waveform(ns):       { 0.000 2.083 }
Period(ns):         4.167
Sources:            { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1 }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
1196
Min Period        n/a     DSP48E1/CLK        n/a            3.292         4.167       0.875      DSP48_X4Y0      compressor393_i/cmprs_channel_block[0].jp_channel_i/focus_sharp393_i/mult_p_r_reg/CLK
1197
Max Period        n/a     PLLE2_ADV/CLKOUT1  n/a            160.000       4.167       155.833    PLLE2_ADV_X0Y0  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
1198 1199
Low Pulse Width   Slow    RAMD32/CLK         n/a            0.910         2.083       1.173      SLICE_X90Y4     compressor393_i/cmprs_channel_block[0].jp_channel_i/dct2d8x8_chen_i/dct1d_chen_reorder_in_i/bufh_ram_reg_0_3_0_5/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK         n/a            0.910         2.083       1.173      SLICE_X6Y46     compressor393_i/cmprs_channel_block[3].jp_channel_i/huffman_stuffer_meta_i/bit_stuffer_escape_i/byte_fifo_block[2].fifo_same_clock_i/ram_reg_0_15_0_5/RAMA/CLK
1200 1201 1202 1203 1204 1205 1206



---------------------------------------------------------------------------------------------------
From Clock:  ffclk0
  To Clock:  ffclk0

1207 1208
Setup :            0  Failing Endpoints,  Worst Slack       40.950ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.233ns,  Total Violation        0.000ns
1209 1210 1211 1212 1213 1214
PW    :            0  Failing Endpoints,  Worst Slack       10.833ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
1215
Slack (MET) :             40.950ns  (required time - arrival time)
1216 1217 1218 1219 1220 1221 1222
  Source:                 clocks393_i/test_clk_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by ffclk0  {rise@0.000ns fall@20.833ns period=41.667ns})
  Destination:            clocks393_i/test_clk_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by ffclk0  {rise@0.000ns fall@20.833ns period=41.667ns})
  Path Group:             ffclk0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            41.667ns  (ffclk0 rise@41.667ns - ffclk0 rise@0.000ns)
1223
  Data Path Delay:        0.753ns  (logic 0.361ns (47.933%)  route 0.392ns (52.067%))
1224 1225
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.000ns (DCD - SCD + CPR)
1226 1227 1228
    Destination Clock Delay (DCD):    4.314ns = ( 45.981 - 41.667 ) 
    Source Clock Delay      (SCD):    4.622ns
    Clock Pessimism Removal (CPR):    0.308ns
1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ffclk0 rise edge)     0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.906     0.906 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           2.206     3.112    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.120     3.232 r  PLLE2_ADV_i_i_1__0/O
1243 1244
                         net (fo=2, routed)           1.390     4.622    clocks393_i/clk_in
    SLICE_X38Y109        FDCE                                         r  clocks393_i/test_clk_reg[1]/C
1245
  -------------------------------------------------------------------    -------------------
1246 1247 1248 1249 1250
    SLICE_X38Y109        FDCE (Prop_fdce_C_Q)         0.308     4.930 f  clocks393_i/test_clk_reg[1]/Q
                         net (fo=4, routed)           0.392     5.322    clocks393_i/test_clk_reg
    SLICE_X38Y109        LUT1 (Prop_lut1_I0_O)        0.053     5.375 r  clocks393_i/test_clk[1]_i_1/O
                         net (fo=1, routed)           0.000     5.375    clocks393_i/test_clk[1]_i_1_n_0
    SLICE_X38Y109        FDCE                                         r  clocks393_i/test_clk_reg[1]/D
1251 1252 1253 1254 1255 1256 1257 1258
  -------------------------------------------------------------------    -------------------

                         (clock ffclk0 rise edge)    41.667    41.667 r  
    Y12                                               0.000    41.667 r  ffclk0p (IN)
                         net (fo=0)                   0.000    41.667    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.827    42.494 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           2.102    44.596    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.113    44.709 r  PLLE2_ADV_i_i_1__0/O
1259 1260 1261 1262 1263
                         net (fo=2, routed)           1.272    45.981    clocks393_i/clk_in
    SLICE_X38Y109        FDCE                                         r  clocks393_i/test_clk_reg[1]/C
                         clock pessimism              0.308    46.289    
                         clock uncertainty           -0.035    46.253    
    SLICE_X38Y109        FDCE (Setup_fdce_C_D)        0.071    46.324    clocks393_i/test_clk_reg[1]
1264
  -------------------------------------------------------------------
1265 1266
                         required time                         46.324    
                         arrival time                          -5.375    
1267
  -------------------------------------------------------------------
1268
                         slack                                 40.950    
1269 1270 1271 1272 1273 1274 1275





Min Delay Paths
--------------------------------------------------------------------------------------
1276
Slack (MET) :             0.233ns  (arrival time - required time)
1277 1278 1279 1280 1281 1282 1283
  Source:                 clocks393_i/test_clk_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by ffclk0  {rise@0.000ns fall@20.833ns period=41.667ns})
  Destination:            clocks393_i/test_clk_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by ffclk0  {rise@0.000ns fall@20.833ns period=41.667ns})
  Path Group:             ffclk0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (ffclk0 rise@0.000ns - ffclk0 rise@0.000ns)
1284
  Data Path Delay:        0.320ns  (logic 0.146ns (45.605%)  route 0.174ns (54.395%))
1285 1286
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
1287 1288 1289
    Destination Clock Delay (DCD):    2.256ns
    Source Clock Delay      (SCD):    1.901ns
    Clock Pessimism Removal (CPR):    0.355ns
1290 1291 1292 1293 1294 1295 1296 1297 1298

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ffclk0 rise edge)     0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.446     0.446 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           0.896     1.342    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.026     1.368 r  PLLE2_ADV_i_i_1__0/O
1299 1300
                         net (fo=2, routed)           0.533     1.901    clocks393_i/clk_in
    SLICE_X38Y109        FDCE                                         r  clocks393_i/test_clk_reg[1]/C
1301
  -------------------------------------------------------------------    -------------------
1302 1303 1304 1305 1306
    SLICE_X38Y109        FDCE (Prop_fdce_C_Q)         0.118     2.019 f  clocks393_i/test_clk_reg[1]/Q
                         net (fo=4, routed)           0.174     2.193    clocks393_i/test_clk_reg
    SLICE_X38Y109        LUT1 (Prop_lut1_I0_O)        0.028     2.221 r  clocks393_i/test_clk[1]_i_1/O
                         net (fo=1, routed)           0.000     2.221    clocks393_i/test_clk[1]_i_1_n_0
    SLICE_X38Y109        FDCE                                         r  clocks393_i/test_clk_reg[1]/D
1307 1308 1309 1310 1311 1312 1313 1314
  -------------------------------------------------------------------    -------------------

                         (clock ffclk0 rise edge)     0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.521     0.521 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           0.967     1.488    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.030     1.518 r  PLLE2_ADV_i_i_1__0/O
1315 1316 1317 1318
                         net (fo=2, routed)           0.738     2.256    clocks393_i/clk_in
    SLICE_X38Y109        FDCE                                         r  clocks393_i/test_clk_reg[1]/C
                         clock pessimism             -0.355     1.901    
    SLICE_X38Y109        FDCE (Hold_fdce_C_D)         0.087     1.988    clocks393_i/test_clk_reg[1]
1319
  -------------------------------------------------------------------
1320 1321
                         required time                         -1.988    
                         arrival time                           2.221    
1322
  -------------------------------------------------------------------
1323
                         slack                                  0.233    
1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         ffclk0
Waveform(ns):       { 0.000 20.833 }
Period(ns):         41.667
Sources:            { ffclk0p }

Check Type        Corner  Lib Pin           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     BUFG/I            n/a            1.600         41.667      40.067     BUFGCTRL_X0Y8   PLLE2_ADV_i_i_1__0/I
Max Period        n/a     PLLE2_ADV/CLKIN1  n/a            52.633        41.667      10.966     PLLE2_ADV_X0Y1  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKIN1
Low Pulse Width   Slow    PLLE2_ADV/CLKIN1  n/a            10.000        20.833      10.833     PLLE2_ADV_X0Y1  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKIN1
High Pulse Width  Slow    PLLE2_ADV/CLKIN1  n/a            10.000        20.833      10.833     PLLE2_ADV_X0Y1  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKIN1



---------------------------------------------------------------------------------------------------
From Clock:  clkfb
  To Clock:  clkfb

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack       10.966ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clkfb
Waveform(ns):       { 0.000 20.833 }
Period(ns):         41.667
Sources:            { clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT }

Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period  n/a     PLLE2_ADV/CLKFBOUT  n/a            1.249         41.667      40.418     PLLE2_ADV_X0Y1  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT
Max Period  n/a     PLLE2_ADV/CLKFBIN   n/a            52.633        41.667      10.966     PLLE2_ADV_X0Y1  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKFBIN



---------------------------------------------------------------------------------------------------
From Clock:  pclk
  To Clock:  pclk

1371 1372
Setup :            0  Failing Endpoints,  Worst Slack       42.687ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.016ns,  Total Violation        0.000ns
1373 1374 1375 1376 1377 1378
PW    :            0  Failing Endpoints,  Worst Slack       49.090ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
1379 1380
Slack (MET) :             42.687ns  (required time - arrival time)
  Source:                 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_lepton3_i/prst_r_reg/C
1381 1382 1383 1384 1385 1386
                            (rising edge-triggered cell FDRE clocked by pclk  {rise@0.000ns fall@50.000ns period=100.001ns})
  Destination:            sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/spi_clk_i/ODDR_i/CE
                            (falling edge-triggered cell ODDR clocked by pclk  {rise@0.000ns fall@50.000ns period=100.001ns})
  Path Group:             pclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (pclk fall@50.000ns - pclk rise@0.000ns)
1387
  Data Path Delay:        6.890ns  (logic 0.334ns (4.848%)  route 6.556ns (95.152%))
1388
  Logic Levels:           1  (LUT3=1)
1389
  Clock Path Skew:        0.280ns (DCD - SCD + CPR)
1390
    Destination Clock Delay (DCD):    7.936ns = ( 57.936 - 50.000 ) 
1391 1392
    Source Clock Delay      (SCD):    8.084ns
    Clock Pessimism Removal (CPR):    0.428ns
1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410
  Clock Uncertainty:      0.166ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.324ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock pclk rise edge)       0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.906     0.906 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           2.206     3.112    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.120     3.232 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           1.609     4.841    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.088     4.929 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.633     6.562    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.120     6.682 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
1411 1412
                         net (fo=5162, routed)        1.402     8.084    sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_lepton3_i/clk1x
    SLICE_X73Y96         FDRE                                         r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_lepton3_i/prst_r_reg/C
1413
  -------------------------------------------------------------------    -------------------
1414 1415 1416 1417
    SLICE_X73Y96         FDRE (Prop_fdre_C_Q)         0.269     8.353 r  sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_lepton3_i/prst_r_reg/Q
                         net (fo=4, routed)           1.672    10.025    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/vospi_packet_80_i/prst_r
    SLICE_X106Y94        LUT3 (Prop_lut3_I0_O)        0.065    10.090 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/vospi_segment_61_i/vospi_packet_80_i/ODDR_i_i_1__0/O
                         net (fo=1, routed)           4.884    14.973    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/spi_clk_i/ce
1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431
    OLOGIC_X0Y11         ODDR                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/spi_clk_i/ODDR_i/CE
  -------------------------------------------------------------------    -------------------

                         (clock pclk fall edge)      50.000    50.000 f  
    Y12                                               0.000    50.000 f  ffclk0p (IN)
                         net (fo=0)                   0.000    50.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.827    50.827 f  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           2.102    52.929    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.113    53.042 f  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           1.476    54.518    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.083    54.601 f  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.550    56.151    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.113    56.264 f  clocks393_i/dual_clock_pclk_i/clk1x_i/O
1432
                         net (fo=5162, routed)        1.672    57.936    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/spi_clk_i/clk1x
1433
    OLOGIC_X0Y11         ODDR                                         f  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/spi_clk_i/ODDR_i/C
1434 1435 1436
                         clock pessimism              0.428    58.364    
                         clock uncertainty           -0.166    58.198    
    OLOGIC_X0Y11         ODDR (Setup_oddr_C_CE)      -0.538    57.660    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_lepton3_i/spi_clk_i/ODDR_i
1437
  -------------------------------------------------------------------
1438 1439
                         required time                         57.660    
                         arrival time                         -14.973    
1440
  -------------------------------------------------------------------
1441
                         slack                                 42.687    
1442 1443 1444 1445 1446 1447 1448





Min Delay Paths
--------------------------------------------------------------------------------------
1449 1450
Slack (MET) :             0.016ns  (arrival time - required time)
  Source:                 sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/i_fxy/dF_reg[6]/C
1451
                            (rising edge-triggered cell FDRE clocked by pclk  {rise@0.000ns fall@50.000ns period=100.001ns})
1452
  Destination:            sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/i_fxy/F_r_reg[8]/D
1453 1454 1455 1456
                            (rising edge-triggered cell FDRE clocked by pclk  {rise@0.000ns fall@50.000ns period=100.001ns})
  Path Group:             pclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (pclk rise@0.000ns - pclk rise@0.000ns)
1457 1458
  Data Path Delay:        0.385ns  (logic 0.257ns (66.672%)  route 0.128ns (33.328%))
  Logic Levels:           3  (CARRY4=2 LUT2=1)
1459
  Clock Path Skew:        0.298ns (DCD - SCD - CPR)
1460 1461
    Destination Clock Delay (DCD):    3.914ns
    Source Clock Delay      (SCD):    3.172ns
1462
    Clock Pessimism Removal (CPR):    0.444ns
1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock pclk rise edge)       0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.446     0.446 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           0.896     1.342    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.026     1.368 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           0.603     1.971    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.050     2.021 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.584     2.605    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     2.631 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490
                         net (fo=5162, routed)        0.541     3.172    sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/i_fxy/clk1x
    SLICE_X90Y149        FDRE                                         r  sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/i_fxy/dF_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y149        FDRE (Prop_fdre_C_Q)         0.118     3.290 r  sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/i_fxy/dF_reg[6]/Q
                         net (fo=3, routed)           0.128     3.417    sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/i_fxy/dF[6]
    SLICE_X91Y149        LUT2 (Prop_lut2_I0_O)        0.029     3.446 r  sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/i_fxy/F_r[7]_i_3__6/O
                         net (fo=1, routed)           0.000     3.446    sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/i_fxy/F_r[7]_i_3__6_n_0
    SLICE_X91Y149        CARRY4 (Prop_carry4_DI[2]_CO[3])
                                                      0.069     3.515 r  sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/i_fxy/F_r_reg[7]_i_1__6/CO[3]
                         net (fo=1, routed)           0.001     3.516    sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/i_fxy/F_r_reg[7]_i_1__6_n_0
    SLICE_X91Y150        CARRY4 (Prop_carry4_CI_O[0])
                                                      0.041     3.557 r  sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/i_fxy/F_r_reg[11]_i_1__6/O[0]
                         net (fo=1, routed)           0.000     3.557    sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/i_fxy/F_r_reg[11]_i_1__6_n_7
    SLICE_X91Y150        FDRE                                         r  sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/i_fxy/F_r_reg[8]/D
1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503
  -------------------------------------------------------------------    -------------------

                         (clock pclk rise edge)       0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.521     0.521 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           0.967     1.488    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.030     1.518 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           0.815     2.333    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.053     2.386 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.651     3.037    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.030     3.067 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
1504 1505 1506 1507
                         net (fo=5162, routed)        0.847     3.914    sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/i_fxy/clk1x
    SLICE_X91Y150        FDRE                                         r  sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/i_fxy/F_r_reg[8]/C
                         clock pessimism             -0.444     3.470    
    SLICE_X91Y150        FDRE (Hold_fdre_C_D)         0.071     3.541    sensors393_i/sensor_channel_block[3].sensor_channel_i/lens_flat393_i/i_fxy/F_r_reg[8]
1508
  -------------------------------------------------------------------
1509 1510
                         required time                         -3.541    
                         arrival time                           3.557    
1511
  -------------------------------------------------------------------
1512
                         slack                                  0.016    
1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pclk
Waveform(ns):       { 0.000 50.000 }
Period(ns):         100.001
Sources:            { clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
1526
Min Period        n/a     DSP48E1/CLK        n/a            3.124         100.001     96.877     DSP48_X5Y60     sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_gamma_i/table_mult/CLK
1527
Max Period        n/a     PLLE2_ADV/CLKOUT0  n/a            160.000       100.001     59.999     PLLE2_ADV_X0Y1  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
1528 1529
Low Pulse Width   Slow    RAMD32/CLK         n/a            0.910         50.000      49.090     SLICE_X88Y161   sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_histogram_0_i/hist_frame_ram_reg_0_1_0_3/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK         n/a            0.910         50.000      49.090     SLICE_X84Y161   sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/hist_frame_ram_reg_0_1_0_3/RAMA/CLK
1530 1531 1532 1533 1534 1535 1536



---------------------------------------------------------------------------------------------------
From Clock:  gtrefclk
  To Clock:  gtrefclk

1537 1538
Setup :            0  Failing Endpoints,  Worst Slack        4.119ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.262ns,  Total Violation        0.000ns
1539 1540 1541 1542 1543 1544
PW    :            0  Failing Endpoints,  Worst Slack        2.553ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
1545 1546
Slack (MET) :             4.119ns  (required time - arrival time)
  Source:                 sata_top/ahci_sata_layers_i/phy/rst_timer_reg[0]/C
1547
                            (rising edge-triggered cell FDRE clocked by gtrefclk  {rise@0.000ns fall@3.333ns period=6.666ns})
1548
  Destination:            sata_top/ahci_sata_layers_i/phy/rst_timer_reg[2]/CE
1549 1550 1551 1552
                            (rising edge-triggered cell FDRE clocked by gtrefclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Path Group:             gtrefclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (gtrefclk rise@6.666ns - gtrefclk rise@0.000ns)
1553
  Data Path Delay:        2.245ns  (logic 0.375ns (16.700%)  route 1.870ns (83.300%))
1554
  Logic Levels:           2  (LUT3=1 LUT6=1)
1555
  Clock Path Skew:        -0.022ns (DCD - SCD + CPR)
1556 1557
    Destination Clock Delay (DCD):    1.441ns = ( 8.107 - 6.666 ) 
    Source Clock Delay      (SCD):    1.565ns
1558
    Clock Pessimism Removal (CPR):    0.102ns
1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock gtrefclk rise edge)
                                                      0.000     0.000 r  
    IBUFDS_GTE2_X0Y0     IBUFDS_GTE2                  0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O
1570 1571
                         net (fo=25, routed)          1.565     1.565    sata_top/ahci_sata_layers_i/phy/gtrefclk
    SLICE_X61Y48         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/rst_timer_reg[0]/C
1572
  -------------------------------------------------------------------    -------------------
1573 1574 1575 1576 1577 1578 1579
    SLICE_X61Y48         FDRE (Prop_fdre_C_Q)         0.269     1.834 r  sata_top/ahci_sata_layers_i/phy/rst_timer_reg[0]/Q
                         net (fo=7, routed)           1.131     2.966    sata_top/ahci_sata_layers_i/phy/rst_timer_reg__0[0]
    SLICE_X61Y49         LUT6 (Prop_lut6_I2_O)        0.053     3.019 f  sata_top/ahci_sata_layers_i/phy/sata_areset_i_2/O
                         net (fo=4, routed)           0.462     3.481    sata_top/ahci_sata_layers_i/phy/sata_areset_i_2_n_0
    SLICE_X62Y48         LUT3 (Prop_lut3_I2_O)        0.053     3.534 r  sata_top/ahci_sata_layers_i/phy/rst_timer[7]_i_2/O
                         net (fo=8, routed)           0.277     3.811    sata_top/ahci_sata_layers_i/phy/rst_timer[7]_i_2_n_0
    SLICE_X61Y49         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/rst_timer_reg[2]/CE
1580 1581 1582 1583 1584
  -------------------------------------------------------------------    -------------------

                         (clock gtrefclk rise edge)
                                                      6.666     6.666 r  
    IBUFDS_GTE2_X0Y0     IBUFDS_GTE2                  0.000     6.666 r  sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O
1585 1586 1587 1588 1589
                         net (fo=25, routed)          1.441     8.107    sata_top/ahci_sata_layers_i/phy/gtrefclk
    SLICE_X61Y49         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/rst_timer_reg[2]/C
                         clock pessimism              0.102     8.209    
                         clock uncertainty           -0.035     8.174    
    SLICE_X61Y49         FDRE (Setup_fdre_C_CE)      -0.244     7.930    sata_top/ahci_sata_layers_i/phy/rst_timer_reg[2]
1590
  -------------------------------------------------------------------
1591 1592
                         required time                          7.930    
                         arrival time                          -3.811    
1593
  -------------------------------------------------------------------
1594
                         slack                                  4.119    
1595 1596 1597 1598 1599 1600 1601





Min Delay Paths
--------------------------------------------------------------------------------------
1602 1603 1604 1605
Slack (MET) :             0.262ns  (arrival time - required time)
  Source:                 sata_top/ahci_sata_layers_i/phy/rst_timer_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by gtrefclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Destination:            sata_top/ahci_sata_layers_i/phy/rst_timer_reg[5]/D
1606 1607 1608 1609
                            (rising edge-triggered cell FDRE clocked by gtrefclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Path Group:             gtrefclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (gtrefclk rise@0.000ns - gtrefclk rise@0.000ns)
1610 1611 1612
  Data Path Delay:        0.323ns  (logic 0.157ns (48.541%)  route 0.166ns (51.459%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
1613
    Destination Clock Delay (DCD):    0.655ns
1614
    Source Clock Delay      (SCD):    0.453ns
1615
    Clock Pessimism Removal (CPR):    0.202ns
1616 1617 1618 1619 1620 1621 1622

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock gtrefclk rise edge)
                                                      0.000     0.000 r  
    IBUFDS_GTE2_X0Y0     IBUFDS_GTE2                  0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O
                         net (fo=25, routed)          0.453     0.453    sata_top/ahci_sata_layers_i/phy/gtrefclk
1623
    SLICE_X61Y49         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/rst_timer_reg[4]/C
1624
  -------------------------------------------------------------------    -------------------
1625 1626 1627 1628 1629
    SLICE_X61Y49         FDRE (Prop_fdre_C_Q)         0.091     0.544 r  sata_top/ahci_sata_layers_i/phy/rst_timer_reg[4]/Q
                         net (fo=3, routed)           0.166     0.711    sata_top/ahci_sata_layers_i/phy/rst_timer_reg__0[4]
    SLICE_X61Y49         LUT6 (Prop_lut6_I5_O)        0.066     0.777 r  sata_top/ahci_sata_layers_i/phy/rst_timer[5]_i_1/O
                         net (fo=1, routed)           0.000     0.777    sata_top/ahci_sata_layers_i/phy/rst_timer0[5]
    SLICE_X61Y49         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/rst_timer_reg[5]/D
1630 1631 1632 1633 1634
  -------------------------------------------------------------------    -------------------

                         (clock gtrefclk rise edge)
                                                      0.000     0.000 r  
    IBUFDS_GTE2_X0Y0     IBUFDS_GTE2                  0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O
1635
                         net (fo=25, routed)          0.655     0.655    sata_top/ahci_sata_layers_i/phy/gtrefclk
1636 1637 1638
    SLICE_X61Y49         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/rst_timer_reg[5]/C
                         clock pessimism             -0.202     0.453    
    SLICE_X61Y49         FDRE (Hold_fdre_C_D)         0.061     0.514    sata_top/ahci_sata_layers_i/phy/rst_timer_reg[5]
1639
  -------------------------------------------------------------------
1640 1641
                         required time                         -0.514    
                         arrival time                           0.777    
1642
  -------------------------------------------------------------------
1643
                         slack                                  0.262    
1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         gtrefclk
Waveform(ns):       { 0.000 3.333 }
Period(ns):         6.666
Sources:            { sata_top/ahci_sata_layers_i/phy/ext_clock_buf/O }

Check Type        Corner  Lib Pin                  Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location            Pin
Min Period        n/a     GTXE2_CHANNEL/GTREFCLK0  n/a            1.538         6.666       5.128      GTXE2_CHANNEL_X0Y0  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/GTREFCLK0
1658 1659
Low Pulse Width   Slow    SRL16E/CLK               n/a            0.780         3.333       2.553      SLICE_X62Y46        sata_top/ahci_sata_layers_i/phy/rxreset_f_r_reg_srl2/CLK
High Pulse Width  Slow    SRL16E/CLK               n/a            0.780         3.333       2.553      SLICE_X62Y46        sata_top/ahci_sata_layers_i/phy/rxreset_f_r_reg_srl2/CLK
1660 1661 1662 1663 1664 1665 1666



---------------------------------------------------------------------------------------------------
From Clock:  rx_clk
  To Clock:  rx_clk

1667 1668
Setup :            0  Failing Endpoints,  Worst Slack        0.497ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.055ns,  Total Violation        0.000ns
1669 1670 1671 1672 1673 1674
PW    :            0  Failing Endpoints,  Worst Slack        2.423ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
1675
Slack (MET) :             0.497ns  (required time - arrival time)
1676 1677
  Source:                 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/RAMB36E1_i/CLKARDCLK
                            (rising edge-triggered cell RAMB36E1 clocked by rx_clk  {rise@0.000ns fall@3.333ns period=6.666ns})
1678
  Destination:            sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/wen_reg[1]/CE
1679 1680 1681 1682
                            (rising edge-triggered cell FDRE clocked by rx_clk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Path Group:             rx_clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (rx_clk rise@6.666ns - rx_clk rise@0.000ns)
1683
  Data Path Delay:        5.729ns  (logic 1.247ns (21.766%)  route 4.482ns (78.234%))
1684
  Logic Levels:           7  (LUT3=4 LUT6=3)
1685 1686 1687 1688
  Clock Path Skew:        -0.161ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.670ns = ( 9.336 - 6.666 ) 
    Source Clock Delay      (SCD):    2.887ns
    Clock Pessimism Removal (CPR):    0.056ns
1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock rx_clk rise edge)     0.000     0.000 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK
                         net (fo=1, routed)           1.349     1.349    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/xclk_gtx
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.120     1.469 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/clk1x_i/O
1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721
                         net (fo=327, routed)         1.418     2.887    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/CLK
    RAMB36_X3Y16         RAMB36E1                                     r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/RAMB36E1_i/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X3Y16         RAMB36E1 (Prop_ramb36e1_CLKARDCLK_DOADO[8])
                                                      0.748     3.635 f  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/RAMB36E1_i/DOADO[8]
                         net (fo=5, routed)           1.352     4.987    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/p_1_in[2]
    SLICE_X53Y107        LUT6 (Prop_lut6_I3_O)        0.053     5.040 f  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/is_prim_r[15]_i_8/O
                         net (fo=2, routed)           0.138     5.178    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/is_prim_r[15]_i_8_n_0
    SLICE_X53Y107        LUT6 (Prop_lut6_I4_O)        0.053     5.231 f  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/is_prim_r[15]_i_5/O
                         net (fo=7, routed)           0.450     5.681    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/data_in_r_reg[2]
    SLICE_X50Y106        LUT3 (Prop_lut3_I1_O)        0.062     5.743 f  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_10x8dec/decoding_table/is_prim_r[11]_i_3/O
                         net (fo=2, routed)           0.422     6.164    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/RAMB36E1_i_0
    SLICE_X53Y105        LUT6 (Prop_lut6_I5_O)        0.172     6.336 f  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/is_prim_r[16]_i_2/O
                         net (fo=4, routed)           0.363     6.700    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/is_prim_r_reg[16]
    SLICE_X55Y105        LUT3 (Prop_lut3_I2_O)        0.053     6.753 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/is_aligned_r_i_2/O
                         net (fo=5, routed)           0.477     7.230    sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/RAMB36E1_i_0
    SLICE_X51Y109        LUT3 (Prop_lut3_I1_O)        0.053     7.283 f  sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/msb_in_r_i_1/O
                         net (fo=2, routed)           0.881     8.164    sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/msb_in_r_i_1_n_0
    SLICE_X59Y127        LUT3 (Prop_lut3_I0_O)        0.053     8.217 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/xlnx_opt_LUT_wen_reg[0]_CE_cooolgate_en_gate_1451/O
                         net (fo=6, routed)           0.399     8.616    sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/wen_reg[0]_CE_cooolgate_en_sig_241
    SLICE_X59Y127        FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/wen_reg[1]/CE
1722 1723 1724 1725 1726 1727
  -------------------------------------------------------------------    -------------------

                         (clock rx_clk rise edge)     6.666     6.666 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     6.666 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK
                         net (fo=1, routed)           1.300     7.966    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/xclk_gtx
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.113     8.079 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/clk1x_i/O
1728 1729 1730 1731 1732
                         net (fo=327, routed)         1.257     9.336    sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/CLK
    SLICE_X59Y127        FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/wen_reg[1]/C
                         clock pessimism              0.056     9.392    
                         clock uncertainty           -0.035     9.357    
    SLICE_X59Y127        FDRE (Setup_fdre_C_CE)      -0.244     9.113    sata_top/ahci_sata_layers_i/phy/gtx_wrap/datascope_incoming_i/wen_reg[1]
1733
  -------------------------------------------------------------------
1734 1735
                         required time                          9.113    
                         arrival time                          -8.616    
1736
  -------------------------------------------------------------------
1737
                         slack                                  0.497    
1738 1739 1740 1741 1742 1743 1744





Min Delay Paths
--------------------------------------------------------------------------------------
1745 1746
Slack (MET) :             0.055ns  (arrival time - required time)
  Source:                 sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/data_in_r_reg[0]/C
1747
                            (rising edge-triggered cell FDRE clocked by rx_clk  {rise@0.000ns fall@3.333ns period=6.666ns})
1748
  Destination:            sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_0_5/RAMA/I
1749
                            (rising edge-triggered cell RAMD32 clocked by rx_clk  {rise@0.000ns fall@3.333ns period=6.666ns})
1750 1751 1752
  Path Group:             rx_clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (rx_clk rise@0.000ns - rx_clk rise@0.000ns)
1753
  Data Path Delay:        0.200ns  (logic 0.100ns (50.053%)  route 0.100ns (49.947%))
1754
  Logic Levels:           0  
1755 1756 1757 1758
  Clock Path Skew:        0.014ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.328ns
    Source Clock Delay      (SCD):    1.081ns
    Clock Pessimism Removal (CPR):    0.233ns
1759 1760 1761 1762 1763 1764 1765

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock rx_clk rise edge)     0.000     0.000 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK
                         net (fo=1, routed)           0.526     0.526    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/xclk_gtx
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.026     0.552 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/clk1x_i/O
1766 1767
                         net (fo=327, routed)         0.529     1.081    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/CLK
    SLICE_X53Y107        FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/data_in_r_reg[0]/C
1768
  -------------------------------------------------------------------    -------------------
1769 1770 1771
    SLICE_X53Y107        FDRE (Prop_fdre_C_Q)         0.100     1.181 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/data_in_r_reg[0]/Q
                         net (fo=2, routed)           0.100     1.281    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_0_5/DIA0
    SLICE_X52Y108        RAMD32                                       r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_0_5/RAMA/I
1772 1773 1774 1775 1776 1777
  -------------------------------------------------------------------    -------------------

                         (clock rx_clk rise edge)     0.000     0.000 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK
                         net (fo=1, routed)           0.563     0.563    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/xclk_gtx
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.030     0.593 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bug_xclk/clk1x_i/O
1778 1779 1780 1781 1782
                         net (fo=327, routed)         0.735     1.328    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_0_5/WCLK
    SLICE_X52Y108        RAMD32                                       r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_0_5/RAMA/CLK
                         clock pessimism             -0.233     1.095    
    SLICE_X52Y108        RAMD32 (Hold_ramd32_CLK_I)
                                                      0.131     1.226    sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_0_5/RAMA
1783
  -------------------------------------------------------------------
1784 1785
                         required time                         -1.226    
                         arrival time                           1.281    
1786
  -------------------------------------------------------------------
1787
                         slack                                  0.055    
1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         rx_clk
Waveform(ns):       { 0.000 3.333 }
Period(ns):         6.666
Sources:            { sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXOUTCLK }

Check Type        Corner  Lib Pin                 Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location            Pin
Min Period        n/a     GTXE2_CHANNEL/RXUSRCLK  n/a            4.000         6.666       2.666      GTXE2_CHANNEL_X0Y0  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/RXUSRCLK
1802 1803
Low Pulse Width   Fast    RAMD32/CLK              n/a            0.910         3.333       2.423      SLICE_X52Y108       sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_0_5/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK              n/a            0.910         3.333       2.423      SLICE_X52Y108       sata_top/ahci_sata_layers_i/phy/gtx_wrap/elastic1632_i/fifo_ram_reg_0_15_0_5/RAMA/CLK
1804 1805 1806 1807 1808 1809 1810



---------------------------------------------------------------------------------------------------
From Clock:  txoutclk
  To Clock:  txoutclk

1811 1812
Setup :            0  Failing Endpoints,  Worst Slack        2.153ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.123ns,  Total Violation        0.000ns
1813 1814 1815 1816 1817 1818
PW    :            0  Failing Endpoints,  Worst Slack        2.666ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
1819 1820
Slack (MET) :             2.153ns  (required time - arrival time)
  Source:                 sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_enc_in_r_reg[0]/C
1821
                            (rising edge-triggered cell FDRE clocked by txoutclk  {rise@0.000ns fall@3.333ns period=6.666ns})
1822
  Destination:            sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/RAMB36E1_i/ADDRARDADDR[5]
1823 1824 1825 1826
                            (rising edge-triggered cell RAMB36E1 clocked by txoutclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Path Group:             txoutclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (txoutclk rise@6.666ns - txoutclk rise@0.000ns)
1827
  Data Path Delay:        4.173ns  (logic 0.269ns (6.446%)  route 3.904ns (93.554%))
1828
  Logic Levels:           0  
1829 1830 1831 1832
  Clock Path Skew:        0.175ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.973ns = ( 9.639 - 6.666 ) 
    Source Clock Delay      (SCD):    2.864ns
    Clock Pessimism Removal (CPR):    0.066ns
1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock txoutclk rise edge)
                                                      0.000     0.000 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK
                         net (fo=1, routed)           1.349     1.349    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/txoutclk_gtx
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.120     1.469 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/clk1x_i/O
1846 1847
                         net (fo=136, routed)         1.395     2.864    sata_top/ahci_sata_layers_i/phy/gtx_wrap/CLK
    SLICE_X61Y97         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_enc_in_r_reg[0]/C
1848
  -------------------------------------------------------------------    -------------------
1849 1850 1851
    SLICE_X61Y97         FDRE (Prop_fdre_C_Q)         0.269     3.133 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_enc_in_r_reg[0]/Q
                         net (fo=1, routed)           3.904     7.037    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/ADDRARDADDR[0]
    RAMB36_X6Y5          RAMB36E1                                     r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/RAMB36E1_i/ADDRARDADDR[5]
1852 1853 1854 1855 1856 1857 1858
  -------------------------------------------------------------------    -------------------

                         (clock txoutclk rise edge)
                                                      6.666     6.666 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     6.666 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK
                         net (fo=1, routed)           1.300     7.966    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/txoutclk_gtx
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.113     8.079 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/clk1x_i/O
1859 1860 1861 1862 1863 1864
                         net (fo=136, routed)         1.560     9.639    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/CLK
    RAMB36_X6Y5          RAMB36E1                                     r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/RAMB36E1_i/CLKARDCLK
                         clock pessimism              0.066     9.705    
                         clock uncertainty           -0.035     9.669    
    RAMB36_X6Y5          RAMB36E1 (Setup_ramb36e1_CLKARDCLK_ADDRARDADDR[5])
                                                     -0.479     9.190    sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/encoding_table/RAMB36E1_i
1865
  -------------------------------------------------------------------
1866 1867
                         required time                          9.190    
                         arrival time                          -7.037    
1868
  -------------------------------------------------------------------
1869
                         slack                                  2.153    
1870 1871 1872 1873 1874 1875 1876





Min Delay Paths
--------------------------------------------------------------------------------------
1877 1878
Slack (MET) :             0.123ns  (arrival time - required time)
  Source:                 sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resynchro/data_out_reg[17]/C
1879
                            (rising edge-triggered cell FDCE clocked by txoutclk  {rise@0.000ns fall@3.333ns period=6.666ns})
1880
  Destination:            sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_enc_in_r_reg[1]/D
1881 1882 1883 1884
                            (rising edge-triggered cell FDRE clocked by txoutclk  {rise@0.000ns fall@3.333ns period=6.666ns})
  Path Group:             txoutclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (txoutclk rise@0.000ns - txoutclk rise@0.000ns)
1885
  Data Path Delay:        0.209ns  (logic 0.130ns (62.059%)  route 0.079ns (37.941%))
1886
  Logic Levels:           1  (LUT3=1)
1887 1888 1889 1890
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.336ns
    Source Clock Delay      (SCD):    1.095ns
    Clock Pessimism Removal (CPR):    0.230ns
1891 1892 1893 1894 1895 1896 1897 1898

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock txoutclk rise edge)
                                                      0.000     0.000 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK
                         net (fo=1, routed)           0.526     0.526    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/txoutclk_gtx
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.026     0.552 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/clk1x_i/O
1899 1900
                         net (fo=136, routed)         0.543     1.095    sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resynchro/CLK
    SLICE_X60Y97         FDCE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resynchro/data_out_reg[17]/C
1901
  -------------------------------------------------------------------    -------------------
1902 1903 1904 1905 1906
    SLICE_X60Y97         FDCE (Prop_fdce_C_Q)         0.100     1.195 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resynchro/data_out_reg[17]/Q
                         net (fo=1, routed)           0.079     1.274    sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resync_out[17]
    SLICE_X61Y97         LUT3 (Prop_lut3_I0_O)        0.030     1.304 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_enc_in_r[1]_i_1/O
                         net (fo=1, routed)           0.000     1.304    sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_enc_in_r[1]_i_1_n_0
    SLICE_X61Y97         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_enc_in_r_reg[1]/D
1907 1908 1909 1910 1911 1912 1913
  -------------------------------------------------------------------    -------------------

                         (clock txoutclk rise edge)
                                                      0.000     0.000 r  
    GTXE2_CHANNEL_X0Y0   GTXE2_CHANNEL                0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK
                         net (fo=1, routed)           0.563     0.563    sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/txoutclk_gtx
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.030     0.593 r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/bufg_txoutclk/clk1x_i/O
1914 1915 1916 1917
                         net (fo=136, routed)         0.743     1.336    sata_top/ahci_sata_layers_i/phy/gtx_wrap/CLK
    SLICE_X61Y97         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_enc_in_r_reg[1]/C
                         clock pessimism             -0.230     1.106    
    SLICE_X61Y97         FDRE (Hold_fdre_C_D)         0.075     1.181    sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_enc_in_r_reg[1]
1918
  -------------------------------------------------------------------
1919 1920
                         required time                         -1.181    
                         arrival time                           1.304    
1921
  -------------------------------------------------------------------
1922
                         slack                                  0.123    
1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         txoutclk
Waveform(ns):       { 0.000 3.333 }
Period(ns):         6.666
Sources:            { sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXOUTCLK }

Check Type        Corner  Lib Pin                 Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location            Pin
Min Period        n/a     GTXE2_CHANNEL/TXUSRCLK  n/a            4.000         6.666       2.666      GTXE2_CHANNEL_X0Y0  sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/TXUSRCLK
1937 1938
Low Pulse Width   Fast    FDRE/C                  n/a            0.400         3.333       2.933      SLICE_X105Y18       sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtx_8x10enc/outdata_l_reg[8]/C
High Pulse Width  Slow    FDCE/C                  n/a            0.350         3.333       2.983      SLICE_X62Y97        sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resynchro/data_out_reg[0]/C
1939 1940 1941 1942 1943 1944 1945



---------------------------------------------------------------------------------------------------
From Clock:  usrclk2
  To Clock:  usrclk2

1946 1947
Setup :            0  Failing Endpoints,  Worst Slack        4.057ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.063ns,  Total Violation        0.000ns
1948 1949 1950 1951 1952 1953
PW    :            0  Failing Endpoints,  Worst Slack        5.756ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
1954 1955
Slack (MET) :             4.057ns  (required time - arrival time)
  Source:                 sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[0]/C
1956
                            (rising edge-triggered cell FDCE clocked by usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
1957
  Destination:            sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/fifo_do_r_reg[51]/CE
1958
                            (rising edge-triggered cell FDRE clocked by usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
1959 1960 1961
  Path Group:             usrclk2
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            13.333ns  (usrclk2 rise@13.333ns - usrclk2 rise@0.000ns)
1962 1963 1964 1965 1966 1967
  Data Path Delay:        8.671ns  (logic 0.467ns (5.386%)  route 8.204ns (94.614%))
  Logic Levels:           3  (LUT2=1 LUT3=1 LUT4=1)
  Clock Path Skew:        -0.325ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.925ns = ( 16.258 - 13.333 ) 
    Source Clock Delay      (SCD):    3.522ns
    Clock Pessimism Removal (CPR):    0.272ns
1968 1969 1970 1971 1972 1973 1974 1975 1976
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock usrclk2 rise edge)    0.000     0.000 r  
1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991
    SLICE_X59Y49         FDRE                         0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           1.809     1.809    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y6        BUFG (Prop_bufg_I_O)         0.120     1.929 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        1.593     3.522    sata_top/ahci_sata_layers_i/phy/rxdata_reg[0]__0
    SLICE_X62Y49         FDCE                                         r  sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y49         FDCE (Prop_fdce_C_Q)         0.308     3.830 r  sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[0]/Q
                         net (fo=2, routed)           0.609     4.439    sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg_n_0_[0]
    SLICE_X62Y48         LUT3 (Prop_lut3_I0_O)        0.053     4.492 f  sata_top/ahci_sata_layers_i/phy/was_rst_i_1/O
                         net (fo=278, routed)         6.241    10.732    sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/ahci_dma_rd_stuff_i/sata_reset_done_r_reg[0]
    SLICE_X44Y138        LUT4 (Prop_lut4_I1_O)        0.053    10.785 r  sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/ahci_dma_rd_stuff_i/raddr_r[0]_i_1/O
                         net (fo=2, routed)           0.422    11.208    sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/ahci_dma_rd_stuff_i_n_10
    SLICE_X43Y138        LUT2 (Prop_lut2_I1_O)        0.053    11.261 r  sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/fifo_do_r_reg[48]_CE_cooolgate_en_gate_351/O
                         net (fo=16, routed)          0.932    12.193    sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/fifo_do_r_reg[48]_CE_cooolgate_en_sig_68
    SLICE_X41Y135        FDRE                                         r  sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/fifo_do_r_reg[51]/CE
1992 1993 1994
  -------------------------------------------------------------------    -------------------

                         (clock usrclk2 rise edge)   13.333    13.333 r  
1995 1996 1997 1998 1999 2000 2001 2002
    SLICE_X59Y49         FDRE                         0.000    13.333 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           1.544    14.877    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y6        BUFG (Prop_bufg_I_O)         0.113    14.990 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        1.268    16.258    sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/usrclk2_r_reg
    SLICE_X41Y135        FDRE                                         r  sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/fifo_do_r_reg[51]/C
                         clock pessimism              0.272    16.530    
                         clock uncertainty           -0.035    16.494    
    SLICE_X41Y135        FDRE (Setup_fdre_C_CE)      -0.244    16.250    sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/fifo_do_r_reg[51]
2003
  -------------------------------------------------------------------
2004 2005
                         required time                         16.250    
                         arrival time                         -12.193    
2006
  -------------------------------------------------------------------
2007
                         slack                                  4.057    
2008 2009 2010 2011 2012 2013 2014





Min Delay Paths
--------------------------------------------------------------------------------------
2015 2016
Slack (MET) :             0.063ns  (arrival time - required time)
  Source:                 sata_top/ahci_sata_layers_i/phy/oob_ctrl/oob/txdata_reg[4]/C
2017
                            (rising edge-triggered cell FDRE clocked by usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
2018
  Destination:            sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resynchro/ram_reg_0_7_0_5/RAMC/I
2019
                            (rising edge-triggered cell RAMD32 clocked by usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
2020 2021 2022
  Path Group:             usrclk2
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (usrclk2 rise@0.000ns - usrclk2 rise@0.000ns)
2023
  Data Path Delay:        0.206ns  (logic 0.100ns (48.529%)  route 0.106ns (51.471%))
2024
  Logic Levels:           0  
2025 2026 2027 2028
  Clock Path Skew:        0.014ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.754ns
    Source Clock Delay      (SCD):    1.407ns
    Clock Pessimism Removal (CPR):    0.333ns
2029 2030 2031 2032

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock usrclk2 rise edge)    0.000     0.000 r  
2033 2034 2035 2036 2037
    SLICE_X59Y49         FDRE                         0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           0.838     0.838    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y6        BUFG (Prop_bufg_I_O)         0.026     0.864 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        0.543     1.407    sata_top/ahci_sata_layers_i/phy/oob_ctrl/oob/usrclk2_r_reg
    SLICE_X59Y99         FDRE                                         r  sata_top/ahci_sata_layers_i/phy/oob_ctrl/oob/txdata_reg[4]/C
2038
  -------------------------------------------------------------------    -------------------
2039 2040 2041
    SLICE_X59Y99         FDRE (Prop_fdre_C_Q)         0.100     1.507 r  sata_top/ahci_sata_layers_i/phy/oob_ctrl/oob/txdata_reg[4]/Q
                         net (fo=1, routed)           0.106     1.613    sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resynchro/ram_reg_0_7_0_5/DIC0
    SLICE_X58Y97         RAMD32                                       r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resynchro/ram_reg_0_7_0_5/RAMC/I
2042 2043 2044
  -------------------------------------------------------------------    -------------------

                         (clock usrclk2 rise edge)    0.000     0.000 r  
2045 2046 2047 2048 2049 2050 2051 2052
    SLICE_X59Y49         FDRE                         0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           0.981     0.981    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y6        BUFG (Prop_bufg_I_O)         0.030     1.011 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        0.743     1.754    sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resynchro/ram_reg_0_7_0_5/WCLK
    SLICE_X58Y97         RAMD32                                       r  sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resynchro/ram_reg_0_7_0_5/RAMC/CLK
                         clock pessimism             -0.333     1.421    
    SLICE_X58Y97         RAMD32 (Hold_ramd32_CLK_I)
                                                      0.129     1.550    sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resynchro/ram_reg_0_7_0_5/RAMC
2053
  -------------------------------------------------------------------
2054 2055
                         required time                         -1.550    
                         arrival time                           1.613    
2056
  -------------------------------------------------------------------
2057
                         slack                                  0.063    
2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         usrclk2
Waveform(ns):       { 0.000 6.666 }
Period(ns):         13.333
Sources:            { sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
2071 2072 2073
Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.183         13.333      11.150     RAMB36_X2Y26   sata_top/ahci_top_i/ahci_dma_i/ct_data_ram_reg_bram_0/CLKARDCLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.910         6.667       5.757      SLICE_X34Y127  sata_top/ahci_top_i/ahci_dma_i/ahci_dma_wr_fifo_i/fifo0_ram_reg_0_7_12_17/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.910         6.666       5.756      SLICE_X62Y99   sata_top/ahci_sata_layers_i/phy/gtx_wrap/txdata_resynchro/ram_reg_0_7_12_17/RAMA/CLK
2074 2075 2076 2077 2078 2079 2080



---------------------------------------------------------------------------------------------------
From Clock:  ddr3_clk_div
  To Clock:  ddr3_clk

2081 2082
Setup :            0  Failing Endpoints,  Worst Slack        0.272ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.240ns,  Total Violation        0.000ns
2083 2084 2085 2086 2087
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
2088
Slack (MET) :             0.272ns  (required time - arrival time)
2089 2090
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/C
                            (rising edge-triggered cell FDSE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
2091
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_ba0_i/oserdes_i/oserdes_i/T1
2092 2093 2094 2095
                            (rising edge-triggered cell OSERDESE2 clocked by ddr3_clk  {rise@0.000ns fall@1.250ns period=2.500ns})
  Path Group:             ddr3_clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.500ns  (ddr3_clk rise@2.500ns - ddr3_clk_div rise@0.000ns)
2096
  Data Path Delay:        1.339ns  (logic 0.269ns (20.092%)  route 1.070ns (79.908%))
2097
  Logic Levels:           0  
2098
  Clock Path Skew:        -0.005ns (DCD - SCD + CPR)
2099
    Destination Clock Delay (DCD):    3.645ns = ( 6.145 - 2.500 ) 
2100
    Source Clock Delay      (SCD):    3.793ns
2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116
    Clock Pessimism Removal (CPR):    0.143ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_clk_div rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     1.575    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.088     1.663 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           1.106     2.769    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.377     3.146 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
2117 2118
                         net (fo=753, routed)         0.647     3.793    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/psincdec_reg
    SLICE_X115Y126       FDSE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/C
2119
  -------------------------------------------------------------------    -------------------
2120 2121 2122
    SLICE_X115Y126       FDSE (Prop_fdse_C_Q)         0.269     4.062 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/Q
                         net (fo=23, routed)          1.070     5.132    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_ba0_i/oserdes_i/in_tri_r_reg
    OLOGIC_X1Y101        OSERDESE2                                    r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_ba0_i/oserdes_i/oserdes_i/T1
2123 2124 2125 2126 2127 2128 2129 2130 2131 2132
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_clk rise edge)
                                                      2.500     2.500 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     2.500 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     3.937    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.083     4.020 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1
                         net (fo=1, routed)           1.016     5.036    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_pre
    BUFR_X1Y8            BUFR (Prop_bufr_I_O)         0.370     5.406 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_bufr_i/O
2133 2134
                         net (fo=75, routed)          0.739     6.145    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_ba0_i/oserdes_i/clk
    OLOGIC_X1Y101        OSERDESE2                                    r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_ba0_i/oserdes_i/oserdes_i/CLK
2135 2136
                         clock pessimism              0.143     6.288    
                         clock uncertainty           -0.205     6.083    
2137 2138
    OLOGIC_X1Y101        OSERDESE2 (Setup_oserdese2_CLK_T1)
                                                     -0.679     5.404    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/cmda_ba0_i/oserdes_i/oserdes_i
2139
  -------------------------------------------------------------------
2140
                         required time                          5.404    
2141
                         arrival time                          -5.132    
2142
  -------------------------------------------------------------------
2143
                         slack                                  0.272    
2144 2145 2146 2147 2148 2149 2150





Min Delay Paths
--------------------------------------------------------------------------------------
2151
Slack (MET) :             0.240ns  (arrival time - required time)
2152 2153
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/C
                            (rising edge-triggered cell FDSE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
2154
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[2].cmda_addr_i/oserdes_i/oserdes_i/T1
2155 2156 2157 2158
                            (rising edge-triggered cell OSERDESE2 clocked by ddr3_clk  {rise@0.000ns fall@1.250ns period=2.500ns})
  Path Group:             ddr3_clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (ddr3_clk rise@0.000ns - ddr3_clk_div rise@0.000ns)
2159
  Data Path Delay:        0.505ns  (logic 0.100ns (19.807%)  route 0.405ns (80.193%))
2160
  Logic Levels:           0  
2161 2162 2163
  Clock Path Skew:        0.163ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.799ns
    Source Clock Delay      (SCD):    1.417ns
2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179
    Clock Pessimism Removal (CPR):    0.219ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_clk_div rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.580     0.580    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.050     0.630 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           0.433     1.063    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.090     1.153 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
2180 2181
                         net (fo=753, routed)         0.264     1.417    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/psincdec_reg
    SLICE_X115Y126       FDSE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/C
2182
  -------------------------------------------------------------------    -------------------
2183 2184 2185
    SLICE_X115Y126       FDSE (Prop_fdse_C_Q)         0.100     1.517 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_tri_r_reg/Q
                         net (fo=23, routed)          0.405     1.922    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[2].cmda_addr_i/oserdes_i/in_tri_r_reg
    OLOGIC_X1Y109        OSERDESE2                                    r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[2].cmda_addr_i/oserdes_i/oserdes_i/T1
2186 2187 2188 2189 2190 2191 2192 2193 2194 2195
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.796     0.796    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.053     0.849 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1
                         net (fo=1, routed)           0.490     1.339    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_pre
    BUFR_X1Y8            BUFR (Prop_bufr_I_O)         0.093     1.432 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_bufr_i/O
2196 2197 2198 2199 2200 2201
                         net (fo=75, routed)          0.367     1.799    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[2].cmda_addr_i/oserdes_i/clk
    OLOGIC_X1Y109        OSERDESE2                                    r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[2].cmda_addr_i/oserdes_i/oserdes_i/CLK
                         clock pessimism             -0.219     1.580    
                         clock uncertainty            0.205     1.785    
    OLOGIC_X1Y109        OSERDESE2 (Hold_oserdese2_CLK_T1)
                                                     -0.104     1.681    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/addr_block[2].cmda_addr_i/oserdes_i/oserdes_i
2202
  -------------------------------------------------------------------
2203 2204
                         required time                         -1.681    
                         arrival time                           1.922    
2205
  -------------------------------------------------------------------
2206
                         slack                                  0.240    
2207 2208 2209 2210 2211 2212 2213 2214 2215





---------------------------------------------------------------------------------------------------
From Clock:  ddr3_mclk
  To Clock:  ddr3_clk_div

2216 2217
Setup :            0  Failing Endpoints,  Worst Slack        0.106ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        1.452ns,  Total Violation        0.000ns
2218 2219 2220 2221 2222
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
2223 2224
Slack (MET) :             0.106ns  (required time - arrival time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i/CLKARDCLK
2225
                            (rising edge-triggered cell RAMB36E1 clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
2226
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_a_r_reg[27]/D
2227 2228 2229 2230
                            (rising edge-triggered cell FDRE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             ddr3_clk_div
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.750ns  (ddr3_clk_div rise@5.000ns - ddr3_mclk rise@1.250ns)
2231
  Data Path Delay:        2.243ns  (logic 0.854ns (38.072%)  route 1.389ns (61.928%))
2232
  Logic Levels:           2  (LUT4=1 LUT6=1)
2233 2234 2235
  Clock Path Skew:        -1.231ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.526ns = ( 8.526 - 5.000 ) 
    Source Clock Delay      (SCD):    4.900ns = ( 6.150 - 1.250 ) 
2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251
    Clock Pessimism Removal (CPR):    0.143ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     2.825    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.088     2.913 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.628     4.541    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.120     4.661 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
2252 2253
                         net (fo=32762, routed)       1.489     6.150    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/CLK
    RAMB36_X7Y20         RAMB36E1                                     r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i/CLKARDCLK
2254
  -------------------------------------------------------------------    -------------------
2255 2256 2257 2258 2259 2260 2261 2262
    RAMB36_X7Y20         RAMB36E1 (Prop_ramb36e1_CLKARDCLK_DOADO[12])
                                                      0.748     6.898 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i/DOADO[12]
                         net (fo=1, routed)           0.663     7.560    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/phy_cmd0_word[12]
    SLICE_X112Y102       LUT4 (Prop_lut4_I0_O)        0.053     7.613 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/in_a_r[29]_i_2/O
                         net (fo=24, routed)          0.726     8.340    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/phy_cmd_word[12]
    SLICE_X115Y104       LUT6 (Prop_lut6_I2_O)        0.053     8.393 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/in_a_r[27]_i_1/O
                         net (fo=1, routed)           0.000     8.393    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_a[12]
    SLICE_X115Y104       FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_a_r_reg[27]/D
2263 2264 2265 2266 2267 2268 2269 2270 2271 2272
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_clk_div rise edge)
                                                      5.000     5.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     5.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     6.437    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.083     6.520 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           1.016     7.536    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.370     7.906 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
2273 2274 2275 2276 2277
                         net (fo=753, routed)         0.620     8.526    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/psincdec_reg
    SLICE_X115Y104       FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_a_r_reg[27]/C
                         clock pessimism              0.143     8.669    
                         clock uncertainty           -0.205     8.464    
    SLICE_X115Y104       FDRE (Setup_fdre_C_D)        0.035     8.499    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/in_a_r_reg[27]
2278
  -------------------------------------------------------------------
2279 2280
                         required time                          8.499    
                         arrival time                          -8.393    
2281
  -------------------------------------------------------------------
2282
                         slack                                  0.106    
2283 2284 2285 2286 2287 2288 2289





Min Delay Paths
--------------------------------------------------------------------------------------
2290 2291
Slack (MET) :             1.452ns  (arrival time - required time)
  Source:                 mcntrl393_i/memctrl16_i/ext_buf_rdata_reg[60]/C
2292
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
2293
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/din_r_reg[28]/D
2294 2295 2296 2297
                            (rising edge-triggered cell FDRE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             ddr3_clk_div
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            -1.250ns  (ddr3_clk_div rise@0.000ns - ddr3_mclk rise@1.250ns)
2298
  Data Path Delay:        0.219ns  (logic 0.118ns (53.934%)  route 0.101ns (46.066%))
2299
  Logic Levels:           0  
2300 2301 2302
  Clock Path Skew:        -0.229ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.762ns
    Source Clock Delay      (SCD):    1.772ns = ( 3.022 - 1.250 ) 
2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318
    Clock Pessimism Removal (CPR):    0.219ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.580     1.830    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.050     1.880 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.559     2.439    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.465 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
2319 2320
                         net (fo=32762, routed)       0.557     3.022    mcntrl393_i/memctrl16_i/clk
    SLICE_X106Y122       FDRE                                         r  mcntrl393_i/memctrl16_i/ext_buf_rdata_reg[60]/C
2321
  -------------------------------------------------------------------    -------------------
2322 2323 2324
    SLICE_X106Y122       FDRE (Prop_fdre_C_Q)         0.118     3.140 r  mcntrl393_i/memctrl16_i/ext_buf_rdata_reg[60]/Q
                         net (fo=1, routed)           0.101     3.241    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/ext_buf_rdata_reg[63][28]
    SLICE_X107Y122       FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/din_r_reg[28]/D
2325 2326 2327 2328 2329 2330 2331 2332 2333 2334
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_clk_div rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.796     0.796    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.053     0.849 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           0.490     1.339    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.093     1.432 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
2335 2336 2337 2338 2339
                         net (fo=753, routed)         0.330     1.762    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/psincdec_reg_0
    SLICE_X107Y122       FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/din_r_reg[28]/C
                         clock pessimism             -0.219     1.543    
                         clock uncertainty            0.205     1.748    
    SLICE_X107Y122       FDRE (Hold_fdre_C_D)         0.040     1.788    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/din_r_reg[28]
2340
  -------------------------------------------------------------------
2341 2342
                         required time                         -1.788    
                         arrival time                           3.241    
2343
  -------------------------------------------------------------------
2344
                         slack                                  1.452    
2345 2346 2347 2348 2349 2350 2351 2352 2353





---------------------------------------------------------------------------------------------------
From Clock:  ddr3_clk_div
  To Clock:  ddr3_mclk

2354 2355
Setup :            0  Failing Endpoints,  Worst Slack        2.829ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.141ns,  Total Violation        0.000ns
2356 2357 2358 2359 2360
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
2361 2362
Slack (MET) :             2.829ns  (required time - arrival time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[0].dq_i/iserdes_mem_i/iserdes_i/CLKDIV
2363
                            (rising edge-triggered cell ISERDESE2 clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
2364
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_rdata_r_reg[48]/D
2365
                            (falling edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
2366 2367
  Path Group:             ddr3_mclk
  Path Type:              Setup (Max at Slow Process Corner)
2368
  Requirement:            3.750ns  (ddr3_mclk fall@3.750ns - ddr3_clk_div rise@0.000ns)
2369
  Data Path Delay:        1.604ns  (logic 0.573ns (35.724%)  route 1.031ns (64.276%))
2370
  Logic Levels:           0  
2371 2372 2373
  Clock Path Skew:        0.918ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.565ns = ( 8.315 - 3.750 ) 
    Source Clock Delay      (SCD):    3.790ns
2374 2375 2376 2377 2378 2379 2380 2381
    Clock Pessimism Removal (CPR):    0.143ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
2382 2383 2384 2385
                         (clock ddr3_clk_div rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     1.575    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
2386
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
2387 2388 2389
                                                      0.088     1.663 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           1.106     2.769    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.377     3.146 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
2390 2391
                         net (fo=753, routed)         0.644     3.790    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[0].dq_i/iserdes_mem_i/psincdec_reg
    ILOGIC_X1Y128        ISERDESE2                                    r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[0].dq_i/iserdes_mem_i/iserdes_i/CLKDIV
2392
  -------------------------------------------------------------------    -------------------
2393 2394 2395 2396
    ILOGIC_X1Y128        ISERDESE2 (Prop_iserdese2_CLKDIV_Q2)
                                                      0.573     4.363 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[0].dq_i/iserdes_mem_i/iserdes_i/Q2
                         net (fo=1, routed)           1.031     5.394    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_rdata[48]
    SLICE_X116Y118       FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_rdata_r_reg[48]/D
2397 2398
  -------------------------------------------------------------------    -------------------

2399 2400 2401 2402
                         (clock ddr3_mclk fall edge)
                                                      3.750     3.750 f  
    BUFGCTRL_X0Y17       BUFG                         0.000     3.750 f  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     5.187    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
2403
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
2404 2405 2406
                                                      0.083     5.270 f  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.544     6.814    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.113     6.927 f  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
2407 2408 2409 2410 2411
                         net (fo=32762, routed)       1.388     8.315    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/CLK
    SLICE_X116Y118       FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_rdata_r_reg[48]/C  (IS_INVERTED)
                         clock pessimism              0.143     8.458    
                         clock uncertainty           -0.205     8.253    
    SLICE_X116Y118       FDRE (Setup_fdre_C_D)       -0.030     8.223    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_rdata_r_reg[48]
2412
  -------------------------------------------------------------------
2413 2414
                         required time                          8.223    
                         arrival time                          -5.394    
2415
  -------------------------------------------------------------------
2416
                         slack                                  2.829    
2417 2418 2419 2420 2421 2422 2423





Min Delay Paths
--------------------------------------------------------------------------------------
2424 2425
Slack (MET) :             0.141ns  (arrival time - required time)
  Source:                 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r1_reg[1]/C
2426
                            (falling edge-triggered cell FDRE clocked by ddr3_clk_div  {rise@0.000ns fall@2.500ns period=5.000ns})
2427
  Destination:            mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r2_reg[1]/D
2428 2429 2430 2431
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Path Group:             ddr3_mclk
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            -1.250ns  (ddr3_mclk rise@1.250ns - ddr3_clk_div fall@2.500ns)
2432
  Data Path Delay:        0.461ns  (logic 0.253ns (54.912%)  route 0.208ns (45.088%))
2433
  Logic Levels:           0  
2434 2435 2436
  Clock Path Skew:        1.152ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.875ns = ( 6.125 - 1.250 ) 
    Source Clock Delay      (SCD):    3.580ns = ( 6.080 - 2.500 ) 
2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452
    Clock Pessimism Removal (CPR):    0.143ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_clk_div fall edge)
                                                      2.500     2.500 f  
    BUFGCTRL_X0Y17       BUFG                         0.000     2.500 f  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     3.937    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
                                                      0.083     4.020 f  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
                         net (fo=1, routed)           1.016     5.036    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
    BUFR_X1Y9            BUFR (Prop_bufr_I_O)         0.370     5.406 f  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
2453 2454
                         net (fo=753, routed)         0.674     6.080    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/clk_div
    SLICE_X108Y100       FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r1_reg[1]/C  (IS_INVERTED)
2455
  -------------------------------------------------------------------    -------------------
2456 2457 2458
    SLICE_X108Y100       FDRE (Prop_fdre_C_Q)         0.253     6.333 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r1_reg[1]/Q
                         net (fo=1, routed)           0.208     6.541    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r1[1]
    SLICE_X108Y98        FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r2_reg[1]/D
2459 2460 2461 2462 2463 2464 2465 2466 2467 2468
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     2.825    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.088     2.913 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.628     4.541    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.120     4.661 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
2469 2470 2471 2472 2473
                         net (fo=32762, routed)       1.464     6.125    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/CLK
    SLICE_X108Y98        FDRE                                         r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r2_reg[1]/C
                         clock pessimism             -0.143     5.982    
                         clock uncertainty            0.205     6.187    
    SLICE_X108Y98        FDRE (Hold_fdre_C_D)         0.212     6.399    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/ps_out_r2_reg[1]
2474
  -------------------------------------------------------------------
2475 2476
                         required time                         -6.399    
                         arrival time                           6.541    
2477
  -------------------------------------------------------------------
2478
                         slack                                  0.141    
2479 2480 2481 2482 2483 2484 2485 2486 2487 2488





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  axihp_clk
  To Clock:  axihp_clk

2489 2490
Setup :            0  Failing Endpoints,  Worst Slack        1.752ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.588ns,  Total Violation        0.000ns
2491 2492 2493 2494 2495
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
2496
Slack (MET) :             1.752ns  (required time - arrival time)
2497 2498
  Source:                 sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
2499
  Destination:            compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_out_fifo_i/eof_written_wclk_i/in_reg_reg/CLR
2500 2501 2502 2503
                            (recovery check against rising-edge clock axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            6.667ns  (axihp_clk rise@6.667ns - axihp_clk rise@0.000ns)
2504
  Data Path Delay:        4.391ns  (logic 0.269ns (6.126%)  route 4.122ns (93.874%))
2505
  Logic Levels:           0  
2506 2507 2508
  Clock Path Skew:        -0.260ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.113ns = ( 11.780 - 6.667 ) 
    Source Clock Delay      (SCD):    5.618ns
2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524
    Clock Pessimism Removal (CPR):    0.245ns
  Clock Uncertainty:      0.071ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.124ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock axihp_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.807     1.807    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.088     1.895 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           2.009     3.904    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.120     4.024 r  clocks393_i/hclk_i/clk1x_i/O
2525 2526
                         net (fo=3868, routed)        1.594     5.618    sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/hclk
    SLICE_X27Y170        FDRE                                         r  sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
2527
  -------------------------------------------------------------------    -------------------
2528 2529 2530
    SLICE_X27Y170        FDRE (Prop_fdre_C_Q)         0.269     5.887 f  sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q
                         net (fo=335, routed)         4.122    10.009    compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_out_fifo_i/eof_written_wclk_i/rst[0]
    SLICE_X16Y74         FDCE                                         f  compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_out_fifo_i/eof_written_wclk_i/in_reg_reg/CLR
2531 2532 2533 2534 2535 2536 2537 2538 2539 2540
  -------------------------------------------------------------------    -------------------

                         (clock axihp_clk rise edge)
                                                      6.667     6.667 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     6.667 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.672     8.339    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.083     8.422 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.911    10.333    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.113    10.446 r  clocks393_i/hclk_i/clk1x_i/O
2541 2542 2543 2544 2545
                         net (fo=3868, routed)        1.334    11.780    compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_out_fifo_i/eof_written_wclk_i/hclk
    SLICE_X16Y74         FDCE                                         r  compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_out_fifo_i/eof_written_wclk_i/in_reg_reg/C
                         clock pessimism              0.245    12.025    
                         clock uncertainty           -0.071    11.953    
    SLICE_X16Y74         FDCE (Recov_fdce_C_CLR)     -0.192    11.761    compressor393_i/cmprs_channel_block[2].jp_channel_i/cmprs_out_fifo_i/eof_written_wclk_i/in_reg_reg
2546
  -------------------------------------------------------------------
2547 2548
                         required time                         11.761    
                         arrival time                         -10.009    
2549
  -------------------------------------------------------------------
2550
                         slack                                  1.752    
2551 2552 2553 2554 2555 2556 2557





Min Delay Paths
--------------------------------------------------------------------------------------
2558
Slack (MET) :             0.588ns  (arrival time - required time)
2559
  Source:                 sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
2560
                            (rising edge-triggered cell FDRE clocked by axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
2561
  Destination:            mult_saxi_wr_i/status_wr_i/in_reg_reg/CLR
2562 2563 2564 2565
                            (removal check against rising-edge clock axihp_clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (axihp_clk rise@0.000ns - axihp_clk rise@0.000ns)
2566
  Data Path Delay:        0.555ns  (logic 0.100ns (18.022%)  route 0.455ns (81.978%))
2567
  Logic Levels:           0  
2568 2569 2570 2571
  Clock Path Skew:        0.017ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.645ns
    Source Clock Delay      (SCD):    2.127ns
    Clock Pessimism Removal (CPR):    0.501ns
2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock axihp_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.657     0.657    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.050     0.707 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.771     1.478    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     1.504 r  clocks393_i/hclk_i/clk1x_i/O
2583 2584
                         net (fo=3868, routed)        0.623     2.127    sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/hclk
    SLICE_X27Y170        FDRE                                         r  sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
2585
  -------------------------------------------------------------------    -------------------
2586 2587 2588
    SLICE_X27Y170        FDRE (Prop_fdre_C_Q)         0.100     2.227 f  sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q
                         net (fo=335, routed)         0.455     2.682    mult_saxi_wr_i/status_wr_i/rst[0]
    SLICE_X38Y165        FDCE                                         f  mult_saxi_wr_i/status_wr_i/in_reg_reg/CLR
2589 2590 2591 2592 2593 2594 2595 2596 2597 2598
  -------------------------------------------------------------------    -------------------

                         (clock axihp_clk rise edge)
                                                      0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.889     0.889    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.053     0.942 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.840     1.782    clocks393_i/hclk_i/hclk_pre
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.030     1.812 r  clocks393_i/hclk_i/clk1x_i/O
2599 2600 2601 2602
                         net (fo=3868, routed)        0.833     2.645    mult_saxi_wr_i/status_wr_i/hclk
    SLICE_X38Y165        FDCE                                         r  mult_saxi_wr_i/status_wr_i/in_reg_reg/C
                         clock pessimism             -0.501     2.144    
    SLICE_X38Y165        FDCE (Remov_fdce_C_CLR)     -0.050     2.094    mult_saxi_wr_i/status_wr_i/in_reg_reg
2603
  -------------------------------------------------------------------
2604 2605
                         required time                         -2.094    
                         arrival time                           2.682    
2606
  -------------------------------------------------------------------
2607
                         slack                                  0.588    
2608 2609 2610 2611 2612 2613 2614 2615 2616 2617





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  ddr3_mclk
  To Clock:  ddr3_mclk

2618 2619
Setup :            0  Failing Endpoints,  Worst Slack        0.639ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.286ns,  Total Violation        0.000ns
2620 2621 2622 2623 2624
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
2625 2626
Slack (MET) :             0.639ns  (required time - arrival time)
  Source:                 sync_resets_i/rst_early_master_reg_replica_7/C
2627
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
2628
  Destination:            membridge_i/start_i/in_reg_reg/CLR
2629 2630 2631 2632
                            (recovery check against rising-edge clock ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (ddr3_mclk rise@6.250ns - ddr3_mclk rise@1.250ns)
2633
  Data Path Delay:        3.894ns  (logic 0.246ns (6.318%)  route 3.648ns (93.682%))
2634
  Logic Levels:           0  
2635 2636 2637 2638
  Clock Path Skew:        -0.022ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.528ns = ( 10.778 - 6.250 ) 
    Source Clock Delay      (SCD):    4.784ns = ( 6.034 - 1.250 ) 
    Clock Pessimism Removal (CPR):    0.234ns
2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653
  Clock Uncertainty:      0.085ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.156ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.575     2.825    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.088     2.913 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.628     4.541    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.120     4.661 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
2654 2655
                         net (fo=32762, routed)       1.373     6.034    sync_resets_i/mclk
    SLICE_X39Y123        FDRE                                         r  sync_resets_i/rst_early_master_reg_replica_7/C
2656
  -------------------------------------------------------------------    -------------------
2657 2658 2659
    SLICE_X39Y123        FDRE (Prop_fdre_C_Q)         0.246     6.280 f  sync_resets_i/rst_early_master_reg_replica_7/Q
                         net (fo=445, routed)         3.648     9.928    membridge_i/start_i/rst[0]_repN_7_alias
    SLICE_X19Y94         FDCE                                         f  membridge_i/start_i/in_reg_reg/CLR
2660 2661 2662 2663 2664 2665 2666 2667 2668 2669
  -------------------------------------------------------------------    -------------------

                         (clock ddr3_mclk rise edge)
                                                      6.250     6.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     6.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.437     7.687    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
                                                      0.083     7.770 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.544     9.314    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.113     9.427 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
2670 2671 2672 2673 2674
                         net (fo=32762, routed)       1.351    10.778    membridge_i/start_i/mclk
    SLICE_X19Y94         FDCE                                         r  membridge_i/start_i/in_reg_reg/C
                         clock pessimism              0.234    11.012    
                         clock uncertainty           -0.085    10.927    
    SLICE_X19Y94         FDCE (Recov_fdce_C_CLR)     -0.360    10.567    membridge_i/start_i/in_reg_reg
2675
  -------------------------------------------------------------------
2676 2677
                         required time                         10.567    
                         arrival time                          -9.928    
2678
  -------------------------------------------------------------------
2679
                         slack                                  0.639    
2680 2681 2682 2683 2684 2685 2686





Min Delay Paths
--------------------------------------------------------------------------------------
2687 2688
Slack (MET) :             0.286ns  (arrival time - required time)
  Source:                 sync_resets_i/rst_early_master_reg_replica_1/C
2689
                            (rising edge-triggered cell FDRE clocked by ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
2690
  Destination:            sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/cmd_deser_lens_i/i_cmd_deser_multi/deser_r_reg[41]/CLR
2691 2692 2693
                            (removal check against rising-edge clock ddr3_mclk  {rise@1.250ns fall@3.750ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
2694
  Requirement:            0.000ns  (ddr3_mclk rise@1.250ns - ddr3_mclk rise@1.250ns)
2695
  Data Path Delay:        0.266ns  (logic 0.100ns (37.607%)  route 0.166ns (62.393%))
2696
  Logic Levels:           0  
2697 2698 2699 2700
  Clock Path Skew:        0.030ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.270ns = ( 3.520 - 1.250 ) 
    Source Clock Delay      (SCD):    1.780ns = ( 3.030 - 1.250 ) 
    Clock Pessimism Removal (CPR):    0.460ns
2701 2702 2703

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
2704 2705 2706 2707
                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.580     1.830    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
2708
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
2709 2710 2711
                                                      0.050     1.880 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.559     2.439    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.465 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
2712 2713
                         net (fo=32762, routed)       0.565     3.030    sync_resets_i/mclk
    SLICE_X105Y137       FDRE                                         r  sync_resets_i/rst_early_master_reg_replica_1/C
2714
  -------------------------------------------------------------------    -------------------
2715 2716 2717
    SLICE_X105Y137       FDRE (Prop_fdre_C_Q)         0.100     3.130 f  sync_resets_i/rst_early_master_reg_replica_1/Q
                         net (fo=338, routed)         0.166     3.296    sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/cmd_deser_lens_i/i_cmd_deser_multi/rst[0]_repN_1_alias
    SLICE_X106Y133       FDCE                                         f  sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/cmd_deser_lens_i/i_cmd_deser_multi/deser_r_reg[41]/CLR
2718 2719
  -------------------------------------------------------------------    -------------------

2720 2721 2722 2723
                         (clock ddr3_mclk rise edge)
                                                      1.250     1.250 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     1.250 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.796     2.046    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
2724
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
2725 2726 2727
                                                      0.053     2.099 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.623     2.722    mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.030     2.752 r  mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
2728 2729 2730 2731
                         net (fo=32762, routed)       0.768     3.520    sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/cmd_deser_lens_i/i_cmd_deser_multi/mclk
    SLICE_X106Y133       FDCE                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/cmd_deser_lens_i/i_cmd_deser_multi/deser_r_reg[41]/C
                         clock pessimism             -0.460     3.060    
    SLICE_X106Y133       FDCE (Remov_fdce_C_CLR)     -0.050     3.010    sensors393_i/sensor_channel_block[1].sensor_channel_i/lens_flat393_i/cmd_deser_lens_i/i_cmd_deser_multi/deser_r_reg[41]
2732
  -------------------------------------------------------------------
2733 2734
                         required time                         -3.010    
                         arrival time                           3.296    
2735
  -------------------------------------------------------------------
2736
                         slack                                  0.286    
2737 2738 2739 2740 2741 2742 2743 2744 2745 2746





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  pclk
  To Clock:  pclk

2747 2748
Setup :            0  Failing Endpoints,  Worst Slack       92.425ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.440ns,  Total Violation        0.000ns
2749 2750 2751 2752 2753
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
2754
Slack (MET) :             92.425ns  (required time - arrival time)
2755 2756
  Source:                 sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by pclk  {rise@0.000ns fall@50.000ns period=100.001ns})
2757
  Destination:            sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_done_i/in_reg_reg/CLR
2758 2759 2760 2761
                            (recovery check against rising-edge clock pclk  {rise@0.000ns fall@50.000ns period=100.001ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            100.001ns  (pclk rise@100.001ns - pclk rise@0.000ns)
2762
  Data Path Delay:        7.126ns  (logic 0.416ns (5.838%)  route 6.710ns (94.162%))
2763
  Logic Levels:           1  (LUT2=1)
2764 2765 2766 2767
  Clock Path Skew:        0.024ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    7.670ns = ( 107.670 - 100.001 ) 
    Source Clock Delay      (SCD):    8.074ns
    Clock Pessimism Removal (CPR):    0.428ns
2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785
  Clock Uncertainty:      0.166ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.324ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock pclk rise edge)       0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.906     0.906 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           2.206     3.112    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.120     3.232 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           1.609     4.841    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.088     4.929 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.633     6.562    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.120     6.682 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
2786 2787
                         net (fo=5162, routed)        1.392     8.074    sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/CLK
    SLICE_X65Y101        FDRE                                         r  sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
2788
  -------------------------------------------------------------------    -------------------
2789 2790 2791 2792 2793
    SLICE_X65Y101        FDRE (Prop_fdre_C_Q)         0.246     8.320 f  sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q
                         net (fo=37, routed)          3.018    11.338    sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/Q[0]
    SLICE_X93Y141        LUT2 (Prop_lut2_I0_O)        0.170    11.508 f  sync_resets_i/rst_block[1].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/sr[0]_i_1__25/O
                         net (fo=100, routed)         3.692    15.200    sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_done_i/prsts_24
    SLICE_X70Y160        FDCE                                         f  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_done_i/in_reg_reg/CLR
2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806
  -------------------------------------------------------------------    -------------------

                         (clock pclk rise edge)     100.001   100.001 r  
    Y12                                               0.000   100.001 r  ffclk0p (IN)
                         net (fo=0)                   0.000   100.001    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.827   100.827 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           2.102   102.929    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.113   103.042 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           1.476   104.518    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.083   104.601 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           1.550   106.151    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.113   106.264 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
2807 2808 2809 2810 2811
                         net (fo=5162, routed)        1.406   107.670    sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_done_i/clk1x
    SLICE_X70Y160        FDCE                                         r  sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_done_i/in_reg_reg/C
                         clock pessimism              0.428   108.099    
                         clock uncertainty           -0.166   107.933    
    SLICE_X70Y160        FDCE (Recov_fdce_C_CLR)     -0.308   107.625    sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_histogram_0_i/pulse_cross_clock_hist_done_i/in_reg_reg
2812
  -------------------------------------------------------------------
2813 2814
                         required time                        107.625    
                         arrival time                         -15.200    
2815
  -------------------------------------------------------------------
2816
                         slack                                 92.425    
2817 2818 2819 2820 2821 2822 2823





Min Delay Paths
--------------------------------------------------------------------------------------
2824 2825
Slack (MET) :             0.440ns  (arrival time - required time)
  Source:                 sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_sync_i/en_pclk_reg/C
2826
                            (rising edge-triggered cell FDRE clocked by pclk  {rise@0.000ns fall@50.000ns period=100.001ns})
2827
  Destination:            sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/in_reg_reg/CLR
2828 2829 2830 2831
                            (removal check against rising-edge clock pclk  {rise@0.000ns fall@50.000ns period=100.001ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (pclk rise@0.000ns - pclk rise@0.000ns)
2832
  Data Path Delay:        0.421ns  (logic 0.155ns (36.836%)  route 0.266ns (63.164%))
2833
  Logic Levels:           1  (LUT1=1)
2834 2835 2836 2837
  Clock Path Skew:        0.031ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.821ns
    Source Clock Delay      (SCD):    3.186ns
    Clock Pessimism Removal (CPR):    0.604ns
2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock pclk rise edge)       0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.446     0.446 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           0.896     1.342    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.026     1.368 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           0.603     1.971    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.050     2.021 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.584     2.605    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     2.631 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
2852 2853
                         net (fo=5162, routed)        0.555     3.186    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_sync_i/clk1x
    SLICE_X89Y97         FDRE                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_sync_i/en_pclk_reg/C
2854
  -------------------------------------------------------------------    -------------------
2855 2856 2857 2858 2859
    SLICE_X89Y97         FDRE (Prop_fdre_C_Q)         0.091     3.277 r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_sync_i/en_pclk_reg/Q
                         net (fo=1, routed)           0.077     3.353    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/en_pclk
    SLICE_X89Y97         LUT1 (Prop_lut1_I0_O)        0.064     3.417 f  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/in_reg_i_2__2/O
                         net (fo=2, routed)           0.189     3.606    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/rst0
    SLICE_X86Y96         FDCE                                         f  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/in_reg_reg/CLR
2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 2872
  -------------------------------------------------------------------    -------------------

                         (clock pclk rise edge)       0.000     0.000 r  
    Y12                                               0.000     0.000 r  ffclk0p (IN)
                         net (fo=0)                   0.000     0.000    clocks393_i/ibufds_ibufgds0_i/ffclk0p
    Y12                  IBUFDS (Prop_ibufds_I_O)     0.521     0.521 r  clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O
                         net (fo=1, routed)           0.967     1.488    clocks393_i_n_0
    BUFGCTRL_X0Y8        BUFG (Prop_bufg_I_O)         0.030     1.518 r  PLLE2_ADV_i_i_1__0/O
                         net (fo=2, routed)           0.815     2.333    clocks393_i/dual_clock_pclk_i/pll_base_i/clk_in
    PLLE2_ADV_X0Y1       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                      0.053     2.386 r  clocks393_i/dual_clock_pclk_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
                         net (fo=1, routed)           0.651     3.037    clocks393_i/dual_clock_pclk_i/clk1x_pre
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.030     3.067 r  clocks393_i/dual_clock_pclk_i/clk1x_i/O
2873 2874 2875 2876
                         net (fo=5162, routed)        0.754     3.821    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/clk1x
    SLICE_X86Y96         FDCE                                         r  sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/in_reg_reg/C
                         clock pessimism             -0.604     3.217    
    SLICE_X86Y96         FDCE (Remov_fdce_C_CLR)     -0.050     3.167    sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_sync_i/pulse_cross_clock_sof_late_i/in_reg_reg
2877
  -------------------------------------------------------------------
2878 2879
                         required time                         -3.167    
                         arrival time                           3.606    
2880
  -------------------------------------------------------------------
2881
                         slack                                  0.440    
2882 2883 2884 2885 2886 2887 2888 2889 2890 2891





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  sclk
  To Clock:  sclk

2892 2893
Setup :            0  Failing Endpoints,  Worst Slack        7.406ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.291ns,  Total Violation        0.000ns
2894 2895 2896 2897 2898
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
2899
Slack (MET) :             7.406ns  (required time - arrival time)
2900
  Source:                 sync_resets_i/rst_block[3].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
2901
                            (rising edge-triggered cell FDRE clocked by sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
2902
  Destination:            timing393_i/camsync393_i/i_ts_stb_mclk0/in_reg_reg/CLR
2903 2904 2905 2906
                            (recovery check against rising-edge clock sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (sclk rise@10.000ns - sclk rise@0.000ns)
2907
  Data Path Delay:        2.151ns  (logic 0.399ns (18.549%)  route 1.752ns (81.451%))
2908
  Logic Levels:           1  (LUT2=1)
2909
  Clock Path Skew:        -0.113ns (DCD - SCD + CPR)
2910
    Destination Clock Delay (DCD):    5.054ns = ( 15.054 - 10.000 ) 
2911 2912
    Source Clock Delay      (SCD):    5.412ns
    Clock Pessimism Removal (CPR):    0.245ns
2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926
  Clock Uncertainty:      0.075ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.133ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.807     1.807    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.088     1.895 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           2.009     3.904    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y7        BUFG (Prop_bufg_I_O)         0.120     4.024 r  clocks393_i/sync_clk_i/clk1x_i/O
2927 2928
                         net (fo=1347, routed)        1.388     5.412    sync_resets_i/rst_block[3].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/camsync_clk
    SLICE_X69Y114        FDRE                                         r  sync_resets_i/rst_block[3].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
2929
  -------------------------------------------------------------------    -------------------
2930 2931 2932 2933 2934
    SLICE_X69Y114        FDRE (Prop_fdre_C_Q)         0.246     5.658 f  sync_resets_i/rst_block[3].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q
                         net (fo=2, routed)           0.468     6.126    sync_resets_i/rst_block[3].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/rst[0]
    SLICE_X69Y114        LUT2 (Prop_lut2_I0_O)        0.153     6.279 f  sync_resets_i/rst_block[3].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/in_reg_i_1__98/O
                         net (fo=13, routed)          1.284     7.563    timing393_i/camsync393_i/i_ts_stb_mclk0/eprst
    SLICE_X56Y96         FDCE                                         f  timing393_i/camsync393_i/i_ts_stb_mclk0/in_reg_reg/CLR
2935 2936 2937 2938 2939 2940 2941 2942 2943
  -------------------------------------------------------------------    -------------------

                         (clock sclk rise edge)      10.000    10.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000    10.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.672    11.672    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.083    11.755 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           1.911    13.666    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y7        BUFG (Prop_bufg_I_O)         0.113    13.779 r  clocks393_i/sync_clk_i/clk1x_i/O
2944 2945 2946 2947 2948
                         net (fo=1347, routed)        1.275    15.054    timing393_i/camsync393_i/i_ts_stb_mclk0/camsync_clk
    SLICE_X56Y96         FDCE                                         r  timing393_i/camsync393_i/i_ts_stb_mclk0/in_reg_reg/C
                         clock pessimism              0.245    15.299    
                         clock uncertainty           -0.075    15.224    
    SLICE_X56Y96         FDCE (Recov_fdce_C_CLR)     -0.255    14.969    timing393_i/camsync393_i/i_ts_stb_mclk0/in_reg_reg
2949
  -------------------------------------------------------------------
2950 2951
                         required time                         14.969    
                         arrival time                          -7.563    
2952
  -------------------------------------------------------------------
2953
                         slack                                  7.406    
2954 2955 2956 2957 2958 2959 2960





Min Delay Paths
--------------------------------------------------------------------------------------
2961
Slack (MET) :             0.291ns  (arrival time - required time)
2962 2963 2964 2965 2966 2967 2968
  Source:                 sync_resets_i/rst_block[4].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/busy_r_reg/CLR
                            (removal check against rising-edge clock sclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (sclk rise@0.000ns - sclk rise@0.000ns)
2969
  Data Path Delay:        0.198ns  (logic 0.091ns (45.871%)  route 0.107ns (54.129%))
2970
  Logic Levels:           0  
2971 2972 2973 2974
  Clock Path Skew:        0.014ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.550ns
    Source Clock Delay      (SCD):    2.036ns
    Clock Pessimism Removal (CPR):    0.500ns
2975 2976 2977 2978 2979 2980 2981 2982 2983 2984

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.657     0.657    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.050     0.707 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.771     1.478    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y7        BUFG (Prop_bufg_I_O)         0.026     1.504 r  clocks393_i/sync_clk_i/clk1x_i/O
2985 2986
                         net (fo=1347, routed)        0.532     2.036    sync_resets_i/rst_block[4].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/camsync_clk
    SLICE_X47Y105        FDRE                                         r  sync_resets_i/rst_block[4].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
2987
  -------------------------------------------------------------------    -------------------
2988 2989 2990
    SLICE_X47Y105        FDRE (Prop_fdre_C_Q)         0.091     2.127 f  sync_resets_i/rst_block[4].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q
                         net (fo=3, routed)           0.107     2.234    timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/rst[0]
    SLICE_X47Y106        FDCE                                         f  timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/busy_r_reg/CLR
2991 2992 2993 2994 2995 2996 2997 2998 2999
  -------------------------------------------------------------------    -------------------

                         (clock sclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.889     0.889    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
                                                      0.053     0.942 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
                         net (fo=1, routed)           0.840     1.782    clocks393_i/sync_clk_i/sync_clk_pre
    BUFGCTRL_X0Y7        BUFG (Prop_bufg_I_O)         0.030     1.812 r  clocks393_i/sync_clk_i/clk1x_i/O
3000 3001 3002 3003
                         net (fo=1347, routed)        0.738     2.550    timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/camsync_clk
    SLICE_X47Y106        FDCE                                         r  timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/busy_r_reg/C
                         clock pessimism             -0.500     2.050    
    SLICE_X47Y106        FDCE (Remov_fdce_C_CLR)     -0.107     1.943    timing393_i/timestamp_snapshot_logger_i/snap_tclk_i/busy_r_reg
3004
  -------------------------------------------------------------------
3005 3006
                         required time                         -1.943    
                         arrival time                           2.234    
3007
  -------------------------------------------------------------------
3008
                         slack                                  0.291    
3009 3010 3011 3012 3013 3014 3015 3016 3017 3018





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  usrclk2
  To Clock:  usrclk2

3019 3020
Setup :            0  Failing Endpoints,  Worst Slack        5.054ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.790ns,  Total Violation        0.000ns
3021 3022 3023 3024 3025
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
3026 3027
Slack (MET) :             5.054ns  (required time - arrival time)
  Source:                 sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[0]/C
3028
                            (rising edge-triggered cell FDCE clocked by usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
3029
  Destination:            sata_top/ahci_top_i/ahci_dma_i/ahci_dma_wr_fifo_i/init_confirm_i/in_reg_reg/CLR
3030 3031 3032 3033
                            (recovery check against rising-edge clock usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            13.333ns  (usrclk2 rise@13.333ns - usrclk2 rise@0.000ns)
3034
  Data Path Delay:        7.723ns  (logic 0.414ns (5.360%)  route 7.309ns (94.640%))
3035
  Logic Levels:           2  (LUT2=1 LUT3=1)
3036 3037 3038 3039
  Clock Path Skew:        -0.328ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.922ns = ( 16.255 - 13.333 ) 
    Source Clock Delay      (SCD):    3.522ns
    Clock Pessimism Removal (CPR):    0.272ns
3040 3041 3042 3043 3044 3045 3046 3047 3048
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock usrclk2 rise edge)    0.000     0.000 r  
3049 3050 3051 3052 3053
    SLICE_X59Y49         FDRE                         0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           1.809     1.809    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y6        BUFG (Prop_bufg_I_O)         0.120     1.929 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        1.593     3.522    sata_top/ahci_sata_layers_i/phy/rxdata_reg[0]__0
    SLICE_X62Y49         FDCE                                         r  sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[0]/C
3054
  -------------------------------------------------------------------    -------------------
3055 3056 3057 3058 3059 3060 3061
    SLICE_X62Y49         FDCE (Prop_fdce_C_Q)         0.308     3.830 r  sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg[0]/Q
                         net (fo=2, routed)           0.609     4.439    sata_top/ahci_sata_layers_i/phy/sata_reset_done_r_reg_n_0_[0]
    SLICE_X62Y48         LUT3 (Prop_lut3_I0_O)        0.053     4.492 f  sata_top/ahci_sata_layers_i/phy/was_rst_i_1/O
                         net (fo=278, routed)         5.919    10.411    sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/ahci_dma_rd_stuff_i/sata_reset_done_r_reg[0]
    SLICE_X42Y138        LUT2 (Prop_lut2_I1_O)        0.053    10.464 f  sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/ahci_dma_rd_stuff_i/dout_vld_r[1]_i_1/O
                         net (fo=15, routed)          0.781    11.245    sata_top/ahci_top_i/ahci_dma_i/ahci_dma_wr_fifo_i/init_confirm_i/SR[0]
    SLICE_X34Y131        FDCE                                         f  sata_top/ahci_top_i/ahci_dma_i/ahci_dma_wr_fifo_i/init_confirm_i/in_reg_reg/CLR
3062 3063 3064
  -------------------------------------------------------------------    -------------------

                         (clock usrclk2 rise edge)   13.333    13.333 r  
3065 3066 3067 3068 3069 3070 3071 3072
    SLICE_X59Y49         FDRE                         0.000    13.333 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           1.544    14.877    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y6        BUFG (Prop_bufg_I_O)         0.113    14.990 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        1.265    16.255    sata_top/ahci_top_i/ahci_dma_i/ahci_dma_wr_fifo_i/init_confirm_i/usrclk2_r_reg
    SLICE_X34Y131        FDCE                                         r  sata_top/ahci_top_i/ahci_dma_i/ahci_dma_wr_fifo_i/init_confirm_i/in_reg_reg/C
                         clock pessimism              0.272    16.527    
                         clock uncertainty           -0.035    16.491    
    SLICE_X34Y131        FDCE (Recov_fdce_C_CLR)     -0.192    16.299    sata_top/ahci_top_i/ahci_dma_i/ahci_dma_wr_fifo_i/init_confirm_i/in_reg_reg
3073
  -------------------------------------------------------------------
3074 3075
                         required time                         16.299    
                         arrival time                         -11.245    
3076
  -------------------------------------------------------------------
3077
                         slack                                  5.054    
3078 3079 3080 3081 3082 3083 3084





Min Delay Paths
--------------------------------------------------------------------------------------
3085
Slack (MET) :             0.790ns  (arrival time - required time)
3086 3087
  Source:                 sata_top/ahci_top_i/ahci_dma_i/abort_busy_mclk_reg/C
                            (rising edge-triggered cell FDRE clocked by usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
3088
  Destination:            sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/in_reg_reg/CLR
3089 3090 3091 3092
                            (removal check against rising-edge clock usrclk2  {rise@0.000ns fall@6.666ns period=13.333ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (usrclk2 rise@0.000ns - usrclk2 rise@0.000ns)
3093
  Data Path Delay:        0.755ns  (logic 0.128ns (16.944%)  route 0.627ns (83.056%))
3094
  Logic Levels:           1  (LUT2=1)
3095 3096 3097 3098
  Clock Path Skew:        0.034ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.743ns
    Source Clock Delay      (SCD):    1.389ns
    Clock Pessimism Removal (CPR):    0.320ns
3099 3100 3101 3102

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock usrclk2 rise edge)    0.000     0.000 r  
3103 3104 3105 3106 3107
    SLICE_X59Y49         FDRE                         0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           0.838     0.838    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y6        BUFG (Prop_bufg_I_O)         0.026     0.864 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        0.525     1.389    sata_top/ahci_top_i/ahci_dma_i/usrclk2_r_reg
    SLICE_X45Y131        FDRE                                         r  sata_top/ahci_top_i/ahci_dma_i/abort_busy_mclk_reg/C
3108
  -------------------------------------------------------------------    -------------------
3109 3110 3111 3112 3113
    SLICE_X45Y131        FDRE (Prop_fdre_C_Q)         0.100     1.489 f  sata_top/ahci_top_i/ahci_dma_i/abort_busy_mclk_reg/Q
                         net (fo=18, routed)          0.379     1.867    sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/ahci_dma_rd_stuff_i/abort_busy_mclk_reg
    SLICE_X42Y138        LUT2 (Prop_lut2_I0_O)        0.028     1.895 f  sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/ahci_dma_rd_stuff_i/dout_vld_r[1]_i_1/O
                         net (fo=15, routed)          0.248     2.144    sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/abort_busy_mclk_reg
    SLICE_X39Y133        FDCE                                         f  sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/in_reg_reg/CLR
3114 3115 3116
  -------------------------------------------------------------------    -------------------

                         (clock usrclk2 rise edge)    0.000     0.000 r  
3117 3118 3119 3120 3121 3122 3123
    SLICE_X59Y49         FDRE                         0.000     0.000 r  sata_top/ahci_sata_layers_i/phy/usrclk2_r_reg/Q
                         net (fo=2, routed)           0.981     0.981    sata_top/ahci_sata_layers_i/phy/bufg_sclk/usrclk2_r
    BUFGCTRL_X0Y6        BUFG (Prop_bufg_I_O)         0.030     1.011 r  sata_top/ahci_sata_layers_i/phy/bufg_sclk/clk1x_i/O
                         net (fo=2023, routed)        0.732     1.743    sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/usrclk2_r_reg
    SLICE_X39Y133        FDCE                                         r  sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/in_reg_reg/C
                         clock pessimism             -0.320     1.423    
    SLICE_X39Y133        FDCE (Remov_fdce_C_CLR)     -0.069     1.354    sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/done_flush_i/in_reg_reg
3124
  -------------------------------------------------------------------
3125 3126
                         required time                         -1.354    
                         arrival time                           2.144    
3127
  -------------------------------------------------------------------
3128
                         slack                                  0.790    
3129 3130 3131 3132 3133 3134 3135 3136 3137 3138





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  xclk
  To Clock:  xclk

3139 3140
Setup :            0  Failing Endpoints,  Worst Slack        0.679ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.421ns,  Total Violation        0.000ns
3141 3142 3143 3144 3145
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
3146
Slack (MET) :             0.679ns  (required time - arrival time)
3147 3148
  Source:                 sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
3149
  Destination:            compressor393_i/cmprs_channel_block[1].jp_channel_i/cmprs_frame_sync_i/frame_started_i/in_reg_reg/CLR
3150 3151 3152 3153
                            (recovery check against rising-edge clock xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            4.167ns  (xclk rise@4.167ns - xclk rise@0.000ns)
3154
  Data Path Delay:        3.265ns  (logic 0.269ns (8.239%)  route 2.996ns (91.761%))
3155
  Logic Levels:           0  
3156 3157 3158 3159
  Clock Path Skew:        0.036ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.244ns = ( 9.411 - 4.167 ) 
    Source Clock Delay      (SCD):    5.463ns
    Clock Pessimism Removal (CPR):    0.255ns
3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173
  Clock Uncertainty:      0.067ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.114ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock xclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.807     1.807    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.088     1.895 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           2.009     3.904    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.120     4.024 r  clocks393_i/xclk_i/clk1x_i/O
3174 3175
                         net (fo=13488, routed)       1.439     5.463    sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/pwrdwn_clk_reg[0]
    SLICE_X31Y71         FDRE                                         r  sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
3176
  -------------------------------------------------------------------    -------------------
3177 3178 3179
    SLICE_X31Y71         FDRE (Prop_fdre_C_Q)         0.269     5.732 f  sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q
                         net (fo=116, routed)         2.996     8.728    compressor393_i/cmprs_channel_block[1].jp_channel_i/cmprs_frame_sync_i/frame_started_i/Q[0]
    SLICE_X50Y20         FDCE                                         f  compressor393_i/cmprs_channel_block[1].jp_channel_i/cmprs_frame_sync_i/frame_started_i/in_reg_reg/CLR
3180 3181 3182 3183 3184 3185 3186 3187 3188
  -------------------------------------------------------------------    -------------------

                         (clock xclk rise edge)       4.167     4.167 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     4.167 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         1.672     5.839    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.083     5.922 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           1.911     7.833    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.113     7.946 r  clocks393_i/xclk_i/clk1x_i/O
3189 3190 3191 3192 3193
                         net (fo=13488, routed)       1.465     9.411    compressor393_i/cmprs_channel_block[1].jp_channel_i/cmprs_frame_sync_i/frame_started_i/xclk
    SLICE_X50Y20         FDCE                                         r  compressor393_i/cmprs_channel_block[1].jp_channel_i/cmprs_frame_sync_i/frame_started_i/in_reg_reg/C
                         clock pessimism              0.255     9.666    
                         clock uncertainty           -0.067     9.598    
    SLICE_X50Y20         FDCE (Recov_fdce_C_CLR)     -0.192     9.406    compressor393_i/cmprs_channel_block[1].jp_channel_i/cmprs_frame_sync_i/frame_started_i/in_reg_reg
3194
  -------------------------------------------------------------------
3195 3196
                         required time                          9.406    
                         arrival time                          -8.728    
3197
  -------------------------------------------------------------------
3198
                         slack                                  0.679    
3199 3200 3201 3202 3203 3204 3205





Min Delay Paths
--------------------------------------------------------------------------------------
3206
Slack (MET) :             0.421ns  (arrival time - required time)
3207 3208
  Source:                 sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
3209
  Destination:            compressor393_i/cmprs_channel_block[0].jp_channel_i/cmprs_out_fifo_i/wlast_rclk_i/in_reg_reg/CLR
3210 3211 3212 3213
                            (removal check against rising-edge clock xclk  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (xclk rise@0.000ns - xclk rise@0.000ns)
3214
  Data Path Delay:        0.354ns  (logic 0.100ns (28.235%)  route 0.254ns (71.765%))
3215
  Logic Levels:           0  
3216 3217 3218 3219
  Clock Path Skew:        0.002ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.550ns
    Source Clock Delay      (SCD):    2.072ns
    Clock Pessimism Removal (CPR):    0.476ns
3220 3221 3222 3223 3224 3225 3226 3227 3228 3229

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock xclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.657     0.657    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.050     0.707 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           0.771     1.478    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.026     1.504 r  clocks393_i/xclk_i/clk1x_i/O
3230 3231
                         net (fo=13488, routed)       0.568     2.072    sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/pwrdwn_clk_reg[0]
    SLICE_X31Y71         FDRE                                         r  sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
3232
  -------------------------------------------------------------------    -------------------
3233 3234 3235
    SLICE_X31Y71         FDRE (Prop_fdre_C_Q)         0.100     2.172 f  sync_resets_i/rst_block[2].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q
                         net (fo=116, routed)         0.254     2.426    compressor393_i/cmprs_channel_block[0].jp_channel_i/cmprs_out_fifo_i/wlast_rclk_i/regs_reg[1][0]
    SLICE_X33Y70         FDCE                                         f  compressor393_i/cmprs_channel_block[0].jp_channel_i/cmprs_out_fifo_i/wlast_rclk_i/in_reg_reg/CLR
3236 3237 3238 3239 3240 3241 3242 3243 3244
  -------------------------------------------------------------------    -------------------

                         (clock xclk rise edge)       0.000     0.000 r  
    BUFGCTRL_X0Y17       BUFG                         0.000     0.000 r  clocks393_i/bufg_axi_aclk_i/O
                         net (fo=738, routed)         0.889     0.889    clocks393_i/pll_base_i/axi_clk
    PLLE2_ADV_X0Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
                                                      0.053     0.942 r  clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT1
                         net (fo=1, routed)           0.840     1.782    clocks393_i/xclk_i/xclk_pre
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.030     1.812 r  clocks393_i/xclk_i/clk1x_i/O
3245 3246 3247 3248
                         net (fo=13488, routed)       0.738     2.550    compressor393_i/cmprs_channel_block[0].jp_channel_i/cmprs_out_fifo_i/wlast_rclk_i/xclk
    SLICE_X33Y70         FDCE                                         r  compressor393_i/cmprs_channel_block[0].jp_channel_i/cmprs_out_fifo_i/wlast_rclk_i/in_reg_reg/C
                         clock pessimism             -0.476     2.074    
    SLICE_X33Y70         FDCE (Remov_fdce_C_CLR)     -0.069     2.005    compressor393_i/cmprs_channel_block[0].jp_channel_i/cmprs_out_fifo_i/wlast_rclk_i/in_reg_reg
3249
  -------------------------------------------------------------------
3250 3251
                         required time                         -2.005    
                         arrival time                           2.426    
3252
  -------------------------------------------------------------------
3253
                         slack                                  0.421    
3254 3255 3256 3257 3258