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Elphel
x359
Commits
df1a3dd4
Commit
df1a3dd4
authored
Nov 28, 2017
by
Andrey Filippov
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added eclipse_project_setup
parent
13d6259d
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4
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4 changed files
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28 additions
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4 deletions
+28
-4
.gitignore
.gitignore
+6
-4
.project
eclipse_project_setup/.project
+12
-0
com.elphel.vdt.FPGA_project.prefs
...project_setup/.settings/com.elphel.vdt.FPGA_project.prefs
+7
-0
com.elphel.vdt.prefs
eclipse_project_setup/.settings/com.elphel.vdt.prefs
+3
-0
No files found.
.gitignore
View file @
df1a3dd4
...
...
@@ -21,8 +21,8 @@ IVERILOG_INCLUDE.v
debug/*
html/*
man/*
.project
.pydevproject
/
.project
/
.pydevproject
#copied from .eclipse_project_setup, can be used to import workin set to limit warnings reported
workingSet.psf
*.fst
...
...
@@ -31,6 +31,8 @@ cocotb/sim_build
cocotb/results.xml
*.directory
html.tar.gz
bitbake-logs
sysroots
/bitbake-logs
/sysroots
/image
/scripts
eclipse_project_setup/.project
0 → 100644
View file @
df1a3dd4
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>
x359
</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
</buildSpec>
<natures>
<nature>
com.elphel.vdt.veditor.HdlNature
</nature>
</natures>
</projectDescription>
eclipse_project_setup/.settings/com.elphel.vdt.FPGA_project.prefs
0 → 100644
View file @
df1a3dd4
FPGA_project_@_ImplementationTopFile=x359.v
FPGA_project_@_SimulationTopFile=x359.tf
FPGA_project_@_SimulationTopModule=testbench359
FPGA_project_@_part=xc3s1200eft256-4
com.elphel.store.context.FPGA_project=FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_part<-@\#\#@->
com.elphel.store.version.FPGA_project=1.0
eclipse.preferences.version=1
eclipse_project_setup/.settings/com.elphel.vdt.prefs
0 → 100644
View file @
df1a3dd4
com.elphel.store.context.=com.elphel.vdt.PROJECT_DESING_MENU<-@\#\#@->
com.elphel.vdt.PROJECT_DESING_MENU=MainDesignMenu
eclipse.preferences.version=1
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