Loading .gitignore +6 −4 Original line number Diff line number Diff line Loading @@ -21,8 +21,8 @@ IVERILOG_INCLUDE.v debug/* html/* man/* .project .pydevproject /.project /.pydevproject #copied from .eclipse_project_setup, can be used to import workin set to limit warnings reported workingSet.psf *.fst Loading @@ -31,6 +31,8 @@ cocotb/sim_build cocotb/results.xml *.directory html.tar.gz bitbake-logs sysroots /bitbake-logs /sysroots /image /scripts eclipse_project_setup/.project 0 → 100644 +12 −0 Original line number Diff line number Diff line <?xml version="1.0" encoding="UTF-8"?> <projectDescription> <name>x359</name> <comment></comment> <projects> </projects> <buildSpec> </buildSpec> <natures> <nature>com.elphel.vdt.veditor.HdlNature</nature> </natures> </projectDescription> eclipse_project_setup/.settings/com.elphel.vdt.FPGA_project.prefs 0 → 100644 +7 −0 Original line number Diff line number Diff line FPGA_project_@_ImplementationTopFile=x359.v FPGA_project_@_SimulationTopFile=x359.tf FPGA_project_@_SimulationTopModule=testbench359 FPGA_project_@_part=xc3s1200eft256-4 com.elphel.store.context.FPGA_project=FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_part<-@\#\#@-> com.elphel.store.version.FPGA_project=1.0 eclipse.preferences.version=1 eclipse_project_setup/.settings/com.elphel.vdt.prefs 0 → 100644 +3 −0 Original line number Diff line number Diff line com.elphel.store.context.=com.elphel.vdt.PROJECT_DESING_MENU<-@\#\#@-> com.elphel.vdt.PROJECT_DESING_MENU=MainDesignMenu eclipse.preferences.version=1 Loading
.gitignore +6 −4 Original line number Diff line number Diff line Loading @@ -21,8 +21,8 @@ IVERILOG_INCLUDE.v debug/* html/* man/* .project .pydevproject /.project /.pydevproject #copied from .eclipse_project_setup, can be used to import workin set to limit warnings reported workingSet.psf *.fst Loading @@ -31,6 +31,8 @@ cocotb/sim_build cocotb/results.xml *.directory html.tar.gz bitbake-logs sysroots /bitbake-logs /sysroots /image /scripts
eclipse_project_setup/.project 0 → 100644 +12 −0 Original line number Diff line number Diff line <?xml version="1.0" encoding="UTF-8"?> <projectDescription> <name>x359</name> <comment></comment> <projects> </projects> <buildSpec> </buildSpec> <natures> <nature>com.elphel.vdt.veditor.HdlNature</nature> </natures> </projectDescription>
eclipse_project_setup/.settings/com.elphel.vdt.FPGA_project.prefs 0 → 100644 +7 −0 Original line number Diff line number Diff line FPGA_project_@_ImplementationTopFile=x359.v FPGA_project_@_SimulationTopFile=x359.tf FPGA_project_@_SimulationTopModule=testbench359 FPGA_project_@_part=xc3s1200eft256-4 com.elphel.store.context.FPGA_project=FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_part<-@\#\#@-> com.elphel.store.version.FPGA_project=1.0 eclipse.preferences.version=1
eclipse_project_setup/.settings/com.elphel.vdt.prefs 0 → 100644 +3 −0 Original line number Diff line number Diff line com.elphel.store.context.=com.elphel.vdt.PROJECT_DESING_MENU<-@\#\#@-> com.elphel.vdt.PROJECT_DESING_MENU=MainDesignMenu eclipse.preferences.version=1