Commit ffb8037f authored by Andrey Filippov's avatar Andrey Filippov
Browse files

making design to work with XST ISE 14.7

parent fbce217a

.project

+5 −0
Original line number Diff line number Diff line
@@ -14,5 +14,10 @@ 
			<type>1</type>

			<location>/home/andrey/git/x353/ise_logs/ISEPartgen-20150725173339957.log</location>

		</link>

		<link>

			<name>ise_logs/ISExst.log</name>

			<type>1</type>

			<location>/home/andrey/git/x353/ise_logs/ISExst-20150726001950045.log</location>

		</link>

	</linkedResources>

</projectDescription>

compressor/compressor333.v

+21 −65
Original line number Diff line number Diff line
@@ -955,71 +955,27 @@ dcc_sync i_dcc_sync(//.clk(clk), 
                     );



always @ (negedge clk2x) wr_saturation_d <= wr_saturation;

   FDE_1   i_m_cb0 (.C(clk2x),.CE(wr_saturation),.D(di[ 0]),.Q(m_cb[0]));

   FDE_1   i_m_cb1 (.C(clk2x),.CE(wr_saturation),.D(di[ 1]),.Q(m_cb[1]));

   FDE_1   i_m_cb2 (.C(clk2x),.CE(wr_saturation),.D(di[ 2]),.Q(m_cb[2]));

   FDE_1   i_m_cb3 (.C(clk2x),.CE(wr_saturation),.D(di[ 3]),.Q(m_cb[3]));

   FDE_1   i_m_cb4 (.C(clk2x),.CE(wr_saturation),.D(di[ 4]),.Q(m_cb[4]));

   FDE_1   i_m_cb5 (.C(clk2x),.CE(wr_saturation),.D(di[ 5]),.Q(m_cb[5]));

   FDE_1   i_m_cb6 (.C(clk2x),.CE(wr_saturation),.D(di[ 6]),.Q(m_cb[6]));

   FDE_1   i_m_cb7 (.C(clk2x),.CE(wr_saturation),.D(di[ 7]),.Q(m_cb[7]));

   FDE_1   i_m_cb8 (.C(clk2x),.CE(wr_saturation),.D(di[ 8]),.Q(m_cb[8]));

   FDE_1   i_m_cb9 (.C(clk2x),.CE(wr_saturation),.D(di[ 9]),.Q(m_cb[9]));



   FDE_1   i_m_cr0 (.C(clk2x),.CE(wr_saturation),  .D(di[12]),.Q(m_cr[0]));

   FDE_1   i_m_cr1 (.C(clk2x),.CE(wr_saturation),  .D(di[13]),.Q(m_cr[1]));

   FDE_1   i_m_cr2 (.C(clk2x),.CE(wr_saturation),  .D(di[14]),.Q(m_cr[2]));

   FDE_1   i_m_cr3 (.C(clk2x),.CE(wr_saturation),  .D(di[15]),.Q(m_cr[3]));

   FDE_1   i_m_cr4 (.C(clk2x),.CE(wr_saturation_d),.D(di[ 0]),.Q(m_cr[4]));

   FDE_1   i_m_cr5 (.C(clk2x),.CE(wr_saturation_d),.D(di[ 1]),.Q(m_cr[5]));

   FDE_1   i_m_cr6 (.C(clk2x),.CE(wr_saturation_d),.D(di[ 2]),.Q(m_cr[6]));

   FDE_1   i_m_cr7 (.C(clk2x),.CE(wr_saturation_d),.D(di[ 3]),.Q(m_cr[7]));

   FDE_1   i_m_cr8 (.C(clk2x),.CE(wr_saturation_d),.D(di[ 4]),.Q(m_cr[8]));

   FDE_1   i_m_cr9 (.C(clk2x),.CE(wr_saturation_d),.D(di[ 5]),.Q(m_cr[9]));

//synthesis translate_off

 defparam i_m_cb0.INIT = 1'b0;  // 'h90

 defparam i_m_cb1.INIT = 1'b0;

 defparam i_m_cb2.INIT = 1'b0;

 defparam i_m_cb3.INIT = 1'b0;

 defparam i_m_cb4.INIT = 1'b1;

 defparam i_m_cb5.INIT = 1'b0;

 defparam i_m_cb6.INIT = 1'b0;

 defparam i_m_cb7.INIT = 1'b1;

 defparam i_m_cb8.INIT = 1'b0;

 defparam i_m_cb9.INIT = 1'b0;



 defparam i_m_cr0.INIT = 1'b0;  //'hb6

 defparam i_m_cr1.INIT = 1'b1;

 defparam i_m_cr2.INIT = 1'b1;

 defparam i_m_cr3.INIT = 1'b0;

 defparam i_m_cr4.INIT = 1'b1;

 defparam i_m_cr5.INIT = 1'b1;

 defparam i_m_cr6.INIT = 1'b0;

 defparam i_m_cr7.INIT = 1'b1;

 defparam i_m_cr8.INIT = 1'b0;

 defparam i_m_cr9.INIT = 1'b0;

//synthesis translate_on

//synthesis attribute INIT of i_m_cb0  is "0" 

//synthesis attribute INIT of i_m_cb1  is "0" 

//synthesis attribute INIT of i_m_cb2  is "0" 

//synthesis attribute INIT of i_m_cb3  is "0" 

//synthesis attribute INIT of i_m_cb4  is "1" 

//synthesis attribute INIT of i_m_cb5  is "0" 

//synthesis attribute INIT of i_m_cb6  is "0" 

//synthesis attribute INIT of i_m_cb7  is "1" 

//synthesis attribute INIT of i_m_cb8  is "0" 

//synthesis attribute INIT of i_m_cb9  is "0" 



//synthesis attribute INIT of i_m_cr0  is "0" 

//synthesis attribute INIT of i_m_cr1  is "1" 

//synthesis attribute INIT of i_m_cr2  is "1" 

//synthesis attribute INIT of i_m_cr3  is "0" 

//synthesis attribute INIT of i_m_cr4  is "1" 

//synthesis attribute INIT of i_m_cr5  is "1" 

//synthesis attribute INIT of i_m_cr6  is "0" 

//synthesis attribute INIT of i_m_cr7  is "1" 

//synthesis attribute INIT of i_m_cr8  is "0" 

//synthesis attribute INIT of i_m_cr9  is "0" 

   FDE_1 #(.INIT(1'b0))  i_m_cb0 (.C(clk2x),.CE(wr_saturation),.D(di[ 0]),.Q(m_cb[0]));

   FDE_1 #(.INIT(1'b0))  i_m_cb1 (.C(clk2x),.CE(wr_saturation),.D(di[ 1]),.Q(m_cb[1]));

   FDE_1 #(.INIT(1'b0))  i_m_cb2 (.C(clk2x),.CE(wr_saturation),.D(di[ 2]),.Q(m_cb[2]));

   FDE_1 #(.INIT(1'b0))  i_m_cb3 (.C(clk2x),.CE(wr_saturation),.D(di[ 3]),.Q(m_cb[3]));

   FDE_1 #(.INIT(1'b1))  i_m_cb4 (.C(clk2x),.CE(wr_saturation),.D(di[ 4]),.Q(m_cb[4]));

   FDE_1 #(.INIT(1'b0))  i_m_cb5 (.C(clk2x),.CE(wr_saturation),.D(di[ 5]),.Q(m_cb[5]));

   FDE_1 #(.INIT(1'b0))  i_m_cb6 (.C(clk2x),.CE(wr_saturation),.D(di[ 6]),.Q(m_cb[6]));

   FDE_1 #(.INIT(1'b1))  i_m_cb7 (.C(clk2x),.CE(wr_saturation),.D(di[ 7]),.Q(m_cb[7]));

   FDE_1 #(.INIT(1'b0))  i_m_cb8 (.C(clk2x),.CE(wr_saturation),.D(di[ 8]),.Q(m_cb[8]));

   FDE_1 #(.INIT(1'b0))  i_m_cb9 (.C(clk2x),.CE(wr_saturation),.D(di[ 9]),.Q(m_cb[9]));



   FDE_1 #(.INIT(1'b0))  i_m_cr0 (.C(clk2x),.CE(wr_saturation),  .D(di[12]),.Q(m_cr[0]));

   FDE_1 #(.INIT(1'b1))  i_m_cr1 (.C(clk2x),.CE(wr_saturation),  .D(di[13]),.Q(m_cr[1]));

   FDE_1 #(.INIT(1'b1))  i_m_cr2 (.C(clk2x),.CE(wr_saturation),  .D(di[14]),.Q(m_cr[2]));

   FDE_1 #(.INIT(1'b0))  i_m_cr3 (.C(clk2x),.CE(wr_saturation),  .D(di[15]),.Q(m_cr[3]));

   FDE_1 #(.INIT(1'b1))  i_m_cr4 (.C(clk2x),.CE(wr_saturation_d),.D(di[ 0]),.Q(m_cr[4]));

   FDE_1 #(.INIT(1'b1))  i_m_cr5 (.C(clk2x),.CE(wr_saturation_d),.D(di[ 1]),.Q(m_cr[5]));

   FDE_1 #(.INIT(1'b0))  i_m_cr6 (.C(clk2x),.CE(wr_saturation_d),.D(di[ 2]),.Q(m_cr[6]));

   FDE_1 #(.INIT(1'b1))  i_m_cr7 (.C(clk2x),.CE(wr_saturation_d),.D(di[ 3]),.Q(m_cr[7]));

   FDE_1 #(.INIT(1'b0))  i_m_cr8 (.C(clk2x),.CE(wr_saturation_d),.D(di[ 4]),.Q(m_cr[8]));

   FDE_1 #(.INIT(1'b0))  i_m_cr9 (.C(clk2x),.CE(wr_saturation_d),.D(di[ 5]),.Q(m_cr[9]));



//always @ (negedge clk2x) wr_quantizer_mode_d <= wr_quantizer_mode;

compressor/quantizator353.v

+6 −33
Original line number Diff line number Diff line
@@ -365,39 +365,12 @@ module zigzag (clk, 


   end



   ROM32X1 i_z0 ( .A0(rom_a[0]), .A1(rom_a[1]), .A2(rom_a[2]), .A3(rom_a[3]), .A4(rom_a[4]), .O(rom_q[0]));

   ROM32X1 i_z1 ( .A0(rom_a[0]), .A1(rom_a[1]), .A2(rom_a[2]), .A3(rom_a[3]), .A4(rom_a[4]), .O(rom_q[1]));

   ROM32X1 i_z2 ( .A0(rom_a[0]), .A1(rom_a[1]), .A2(rom_a[2]), .A3(rom_a[3]), .A4(rom_a[4]), .O(rom_q[2]));

   ROM32X1 i_z3 ( .A0(rom_a[0]), .A1(rom_a[1]), .A2(rom_a[2]), .A3(rom_a[3]), .A4(rom_a[4]), .O(rom_q[3]));

   ROM32X1 i_z4 ( .A0(rom_a[0]), .A1(rom_a[1]), .A2(rom_a[2]), .A3(rom_a[3]), .A4(rom_a[4]), .O(rom_q[4]));

   ROM32X1 i_z5 ( .A0(rom_a[0]), .A1(rom_a[1]), .A2(rom_a[2]), .A3(rom_a[3]), .A4(rom_a[4]), .O(rom_q[5]));

//C67319CC   611A7896   6357A260   4A040C18   8C983060   F0E0C080

// transposed! (old was 93D94C66   16A1A578   D0244EBC   7BF6E8F0   9C3870C0   E0C08000



//synthesis translate_off

/*    defparam i_z0.INIT = 32'h93D94C66;

    defparam i_z1.INIT = 32'h16A1A578;

    defparam i_z2.INIT = 32'hD0244EBC;

    defparam i_z3.INIT = 32'h7BF6E8F0;

    defparam i_z4.INIT = 32'h9C3870C0;

    defparam i_z5.INIT = 32'hE0C08000;

*/

    defparam i_z0.INIT = 32'hC67319CC;

    defparam i_z1.INIT = 32'h611A7896;

    defparam i_z2.INIT = 32'h6357A260;

    defparam i_z3.INIT = 32'h4A040C18;

    defparam i_z4.INIT = 32'h8C983060;

    defparam i_z5.INIT = 32'hF0E0C080;

    

    

//synthesis translate_on



//synthesis attribute INIT of i_z0  is "C67319CC" 

//synthesis attribute INIT of i_z1  is "611A7896" 

//synthesis attribute INIT of i_z2  is "6357A260" 

//synthesis attribute INIT of i_z3  is "4A040C18" 

//synthesis attribute INIT of i_z4  is "8C983060" 

//synthesis attribute INIT of i_z5  is "F0E0C080" 

   ROM32X1 #(.INIT(32'hC67319CC)) i_z0 ( .A0(rom_a[0]), .A1(rom_a[1]), .A2(rom_a[2]), .A3(rom_a[3]), .A4(rom_a[4]), .O(rom_q[0]));

   ROM32X1 #(.INIT(32'h611A7896)) i_z1 ( .A0(rom_a[0]), .A1(rom_a[1]), .A2(rom_a[2]), .A3(rom_a[3]), .A4(rom_a[4]), .O(rom_q[1]));

   ROM32X1 #(.INIT(32'h6357A260)) i_z2 ( .A0(rom_a[0]), .A1(rom_a[1]), .A2(rom_a[2]), .A3(rom_a[3]), .A4(rom_a[4]), .O(rom_q[2]));

   ROM32X1 #(.INIT(32'h4A040C18)) i_z3 ( .A0(rom_a[0]), .A1(rom_a[1]), .A2(rom_a[2]), .A3(rom_a[3]), .A4(rom_a[4]), .O(rom_q[3]));

   ROM32X1 #(.INIT(32'h8C983060)) i_z4 ( .A0(rom_a[0]), .A1(rom_a[1]), .A2(rom_a[2]), .A3(rom_a[3]), .A4(rom_a[4]), .O(rom_q[4]));

   ROM32X1 #(.INIT(32'hF0E0C080)) i_z5 ( .A0(rom_a[0]), .A1(rom_a[1]), .A2(rom_a[2]), .A3(rom_a[3]), .A4(rom_a[4]), .O(rom_q[5]));



endmodule

control/clkios353.v

+19 −187
Original line number Diff line number Diff line
@@ -54,7 +54,7 @@ module dcm333( 


  wire isdclk0, isdclk90, isdclk180, isdclk270;

  wire   ixclk;

  wire  gsdclk; //used only for the feedback

//  wire  gsdclk; //used only for the feedback

  wire  isdclk;

  reg   dcm_done;

  wire  dcm_done_dcm; // single-cycle
@@ -65,7 +65,16 @@ module dcm333( 


// second - adjustable DCM. Will be adjusted so read DQS (dependent on SDCLK) will be aligned with sclk90/270

// maybe will need some delay as there is DLL in SDRAM and responce may be slow. 

DCM i_dcm2(

DCM #(

     .CLKIN_DIVIDE_BY_2     ("FALSE"),

     .CLKIN_PERIOD          (8.33333),

     .CLK_FEEDBACK          ("1X"),

     .DESKEW_ADJUST         ("SYSTEM_SYNCHRONOUS"),

     .DLL_FREQUENCY_MODE    ("LOW"),

     .DUTY_CYCLE_CORRECTION ("TRUE"),

     .PHASE_SHIFT           (0),

     .CLKOUT_PHASE_SHIFT    ("VARIABLE")

 ) i_dcm2(

    .CLKIN (sclk),

    .CLKFB (isdclk90),

    .RST (dcm_rst),
@@ -88,28 +97,6 @@ DCM i_dcm2( 
    .STATUS (status[7:0]),

    .LOCKED (locked),

    .PSDONE (dcm_done_dcm));

// s-ynthesis attribute loc of i_dcm2 is "DCM_X1Y1"

// synthesis attribute CLK_FEEDBACK of i_dcm2 is "1X"

// synthesis attribute CLKIN_DIVIDE_BY_2 of i_dcm2 is "FALSE"

// synthesis attribute CLKIN_PERIOD of i_dcm2 is 8.33333

// synthesis attribute CLKOUT_PHASE_SHIFT of i_dcm2 is "VARIABLE"

// synthesis attribute DESKEW_ADJUST of i_dcm2 is "SYSTEM_SYNCHRONOUS"

// synthesis attribute DLL_FREQUENCY_MODE of i_dcm2 is "LOW"

// synthesis attribute DUTY_CYCLE_CORRECTION of i_dcm2 is "TRUE"



// put here default phase shift ....



// synthesis attribute PHASE_SHIFT of i_dcm2 is 0

// synthesis translate_off

 defparam i_dcm2.CLK_FEEDBACK="1X";

 defparam i_dcm2.CLKIN_DIVIDE_BY_2="FALSE";

 defparam i_dcm2.CLKIN_PERIOD=8.33333;

 defparam i_dcm2.CLKOUT_PHASE_SHIFT="VARIABLE";

 defparam i_dcm2.DESKEW_ADJUST="SYSTEM_SYNCHRONOUS";

 defparam i_dcm2.DLL_FREQUENCY_MODE="LOW";

 defparam i_dcm2.DUTY_CYCLE_CORRECTION="TRUE";

 defparam i_dcm2.PHASE_SHIFT=0;

// synthesis translate_on

// BUFG    i_gsdclk (.I(isdclk90), .O(gsdclk));



 OBUFDS  i_SDCLK  (.O(SDCLK),.OB(SDNCLK),.I(isdclk));
@@ -152,7 +139,14 @@ module clockios353( 


  IBUFG i_iclk0 (.I(CLK0), .O(iclk0));

// DCM - just 4 phases out

DCM i_dcm1(

DCM #(

     .CLKIN_DIVIDE_BY_2("FALSE"),

     .CLKIN_PERIOD(8.33333),

     .CLK_FEEDBACK("1X"),

     .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),

     .DLL_FREQUENCY_MODE("LOW"),

     .DUTY_CYCLE_CORRECTION("TRUE")

 ) i_dcm1(

    .CLKIN (iclk0),

    .CLKFB (sclk0),

    .RST (dcmrst), .PSEN (1'b0),.PSINCDEC (1'b0), .PSCLK (1'b0),.DSSEN (1'b0),
@@ -168,21 +162,6 @@ DCM i_dcm1( 
    .STATUS (status[7:0]),

    .LOCKED (locked),

    .PSDONE ());

// s- ynthesis attribute loc of i_dcm1 is "DCM_X0Y0"

// synthesis attribute CLK_FEEDBACK of i_dcm1 is "1X"

// synthesis attribute CLKIN_DIVIDE_BY_2 of i_dcm1 is "FALSE"

// synthesis attribute CLKIN_PERIOD of i_dcm1 is 8.33333

// synthesis attribute DESKEW_ADJUST of i_dcm1 is "SYSTEM_SYNCHRONOUS"

// synthesis attribute DLL_FREQUENCY_MODE of i_dcm1 is "LOW"

// synthesis attribute DUTY_CYCLE_CORRECTION of i_dcm1 is "TRUE"

// synthesis translate_off

 defparam i_dcm1.CLK_FEEDBACK="1X";

 defparam i_dcm1.CLKIN_DIVIDE_BY_2="FALSE";

 defparam i_dcm1.CLKIN_PERIOD=8.33333;

 defparam i_dcm1.DESKEW_ADJUST="SYSTEM_SYNCHRONOUS";

 defparam i_dcm1.DLL_FREQUENCY_MODE="LOW";

 defparam i_dcm1.DUTY_CYCLE_CORRECTION="TRUE";

// synthesis translate_on

 BUFG i_sclk0  (.I(isclk0),.  O(sclk0));

// s-ynthesis attribute loc of i_sclk0 is   "BUFGMUX0"

/* BUFG i_sclk90 (.I(isclk90), .O(sclk90)); */
@@ -193,152 +172,5 @@ DCM i_dcm1( 
// s-ynthesis attribute loc of i_sclk270 is "BUFGMUX3"

endmodule



/*

module clock_pclk( clk0,			// global clock (phase =0)

                   CLK1,         // external input clock

						 pclk,			// global clock, sensor pixel rate

						 clk_en,			// enable clock output to sensor

						 pclk_src,// [3:0] - source fror the pclk

						 dclk);			// clock output to sensor (sync to pclk)

  input CLK1,clk0,clk_en;

  input [3:0] pclk_src;

  output pclk,dclk;



  wire	ipclk,dclk,pclk;

 

   reg clk_en_r;



  IBUF i_iclk1 (.I(CLK1), .O(iclk1));



// and global clock (divided by 1, 1.5,2,...,8)

pclk_cntrl i_pclk_cntrl(.ext_clk(iclk1),  // external clock, may be stopped (will wait for up to 16 clk periods?)

                        .clk(clk0),      // always running global clock

				            .div(pclk_src[3:0]), // 0:      q=ext_clk

	                                          // 1:      q=clk - temporary made clk/1.5 - not to fry MI1300

							                        // 2:      q=clk/1.5

                                             //...0'hf: q=clk/8

				            .q(ipclk));          // output clock



  always @ (posedge pclk) clk_en_r<=clk_en;

  assign dclk=!clk_en_r || !ipclk;

  BUFG	i_pclk (.I(ipclk), .O(pclk));

endmodule























// switches between external clock (no divisor)

// and global clock (divided by 1, 1.5,2,...,8)

module pclk_cntrl(ext_clk,  // external clock, may be stopped (will wait for up to 16 clk periods?)

                  clk,      // always running global clock

                  div,      // 0:      q=ext_clk

                            // 1:      q=clk - temporary made clk/1.5 - not to fry MI1300

                            // 2:      q=clk/1.5

                            //...0'hf: q=clk/8

			         q);       // output clock

  input ext_clk;

  input clk;

  input [3:0] div;

  output q;



  reg       ena;

  reg       enb;

//  reg       clksel;



  wire  [3:0] div_p;

  wire       blank;

  wire       copy_div,blank_off;

  wire       a_on, a_off0,  b_on, b_off;

  reg	[3:0] da0; // from a_start to a_on

  reg	[3:0] da1; // from a_on to a_off

  reg	[3:0] db0; // from a_start to a_on

  reg	[3:0] db1; // from a_on to a_off

  reg        a_start;

  reg        b_start;

  reg        a_off;

  reg       a_singleon; // a stays on for 1 cycle;

  reg        use_b;

  wire a,b,ab;

   FDE	i_div_p0 (.C(clk),.CE(copy_div),.D(div[0]),.Q(div_p[0]));

   FDE	i_div_p1 (.C(clk),.CE(copy_div),.D(div[1]),.Q(div_p[1]));

   FDE	i_div_p2 (.C(clk),.CE(copy_div),.D(div[2]),.Q(div_p[2]));

   FDE	i_div_p3 (.C(clk),.CE(copy_div),.D(div[3]),.Q(div_p[3]));



  always @ (posedge enb or posedge ext_clk) begin

    if (enb) ena <=1'b0;

    else ena <= (div[3:0]==4'b0);

  end



  always @ (posedge clk) begin

    enb <= (div_p[3:0]!=4'b0);

    a_off <= a_singleon?a_on:a_off0;

    a_start <= blank_off || (!blank && (a_singleon?a_on:a_off0));

  end

  always @ (negedge clk) begin 

    b_start <= a_start;

    use_b <= (div_p[3:0]!=4'h0) && (div_p[1:0]!=2'h3);

  end

   FD		i_blank (.C(clk),.D((div[3:0] != div_p[3:0]) || (blank && !blank_off)),.Q(blank)); // add always blank if (div==0)? no!

	SRL16 i_copy_div (.Q(copy_div),.D((div[3:0] != div_p[3:0]) && !blank), .CLK(clk),   .A0(1'b1),  .A1(1'b1), .A2(1'b1), .A3(1'b1));	// dly=max (16)

	SRL16 i_blank_off(.Q(blank_off),.D(copy_div), .CLK(clk),   .A0(1'b1),  .A1(1'b0), .A2(1'b0), .A3(1'b0));	// 2



	SRL16   i_a_on  (.Q(a_on),  .D(a_start), .CLK(clk),   .A0(da0[0]),  .A1(da0[1]), .A2(da0[2]), .A3(da0[3]));

	SRL16   i_a_off0(.Q(a_off0),.D(a_on),   .CLK(clk),   .A0(da1[0]),  .A1(da1[1]), .A2(da1[2]), .A3(da1[3]));

	SRL16_1 i_b_on  (.Q(b_on),  .D(b_start), .CLK(clk),   .A0(db0[0]),  .A1(db0[1]), .A2(db0[2]), .A3(db0[3]));

	SRL16_1 i_b_off (.Q(b_off), .D(b_on),   .CLK(clk),   .A0(db1[0]),  .A1(db1[1]), .A2(db1[2]), .A3(db1[3]));



   FD		i_a (.C(clk),.D(enb && (a_on || (a && !a_off))),.Q(a));

   FD_1	i_b (.C(clk),.D(use_b && (b_on || (b && !b_off))),.Q(b));

	assign ab= ~(a ^ b);

   assign q= (!ena || ext_clk) && (!enb || ab);



  always @ (posedge clk) case (div_p[3:0])

    4'h0: begin  da0<=4'h0;  da1<=4'h0;  a_singleon<=1'b0; end // any, not used

//    4'h1: begin  da0<=4'h0;  da1<=4'h0;  a_singleon<=1'b1; end

    4'h1: begin  da0<=4'h0;  da1<=4'h0;  a_singleon<=1'b0; end // for safety - not higher than clk0/1.5 (50MHz for 75 MHz)

    4'h2: begin  da0<=4'h0;  da1<=4'h0;  a_singleon<=1'b0; end

    4'h3: begin  da0<=4'h0;  da1<=4'h0;  a_singleon<=1'b1; end

    4'h4: begin  da0<=4'h3;  da1<=4'h0;  a_singleon<=1'b1; end

    4'h5: begin  da0<=4'h2;  da1<=4'h1;  a_singleon<=1'b0; end

    4'h6: begin  da0<=4'h1;  da1<=4'h3;  a_singleon<=1'b0; end

    4'h7: begin  da0<=4'h1;  da1<=4'h0;  a_singleon<=1'b0; end

    4'h8: begin  da0<=4'h6;  da1<=4'h0;  a_singleon<=1'b0; end

    4'h9: begin  da0<=4'h4;  da1<=4'h3;  a_singleon<=1'b0; end

    4'ha: begin  da0<=4'h2;  da1<=4'h6;  a_singleon<=1'b0; end

    4'hb: begin  da0<=4'h2;  da1<=4'h1;  a_singleon<=1'b0; end

    4'hc: begin  da0<=4'h9;  da1<=4'h1;  a_singleon<=1'b0; end

    4'hd: begin  da0<=4'h6;  da1<=4'h5;  a_singleon<=1'b0; end

    4'he: begin  da0<=4'h3;  da1<=4'h9;  a_singleon<=1'b0; end

    4'hf: begin  da0<=4'h3;  da1<=4'h2;  a_singleon<=1'b0; end

  endcase



  always @ (negedge clk) case (div_p[3:0])

    4'h0: begin  db0<=4'h0;  db1<=4'h0;  end

//    4'h1: begin  db0<=4'h1;  db1<=4'h0;  end

    4'h1: begin  db0<=4'h0;  db1<=4'h0;  end // for safety - not higher than clk0/1.5 (50MHz for 75 MHz)

    4'h2: begin  db0<=4'h0;  db1<=4'h0;  end

    4'h3: begin  db0<=4'h0;  db1<=4'h0;  end

    4'h4: begin  db0<=4'h0;  db1<=4'h0;  end

    4'h5: begin  db0<=4'h0;  db1<=4'h2;  end

    4'h6: begin  db0<=4'h2;  db1<=4'h1;  end

    4'h7: begin  db0<=4'h0;  db1<=4'h0;  end

    4'h8: begin  db0<=4'h1;  db1<=4'h1;  end

    4'h9: begin  db0<=4'h1;  db1<=4'h4;  end

    4'ha: begin  db0<=4'h4;  db1<=4'h2;  end

    4'hb: begin  db0<=4'h0;  db1<=4'h0;  end

    4'hc: begin  db0<=4'h2;  db1<=4'h2;  end

    4'hd: begin  db0<=4'h2;  db1<=4'h6;  end

    4'he: begin  db0<=4'h6;  db1<=4'h3;  end

    4'hf: begin  db0<=4'h0;  db1<=4'h0;  end

  endcase

endmodule



*/

control/ioports353.v

+11 −47
Original line number Diff line number Diff line
@@ -400,11 +400,7 @@ module sysinterface(clk, 
   FD   i_sync_cwr_start2   (.Q(sync_cwr_start2),.C(clk),.D(sync_cwr_start1));

   FD   i_sync_cwr_on       (.Q(sync_cwr_on),    .C(clk),.D(sync_cwr_start1 || (sync_cwr_on && !sync1)));



   LUT4 i_dataouten ( .I0(1'b1), .I1(ice1), .I2(ice), .I3(ioe), .O(t));

//synthesis translate_off

    defparam i_dataouten.INIT = 16'hAA80;

//synthesis translate_on

//synthesis attribute INIT of i_dataouten  is "AA80" 

   LUT4 #(.INIT(16'hAA80)) i_dataouten ( .I0(1'b1), .I1(ice1), .I2(ice), .I3(ioe), .O(t));

 dpads32 i_dmapads32(.c(cwr),.t(t),.d(iod[31:0]),.q(id0[31:0]),.dq(d[31:0]));

endmodule
@@ -520,18 +516,10 @@ module sddrio0(c0,/*c90,*/c270,d,t,q,dq); // made for CL=2.5, LSB first - c0 fal 
  FD_1 i_q0  (.C(c0),.D(q00),.Q(q[0]));  //regular FF, not IOB

  IOBUF i_dq (.I(dr), .T(tr),.O(qp), .IO(dq));

  FDDRCPE i_dr (.Q(dr),.C0(c270),.C1(!c270),.D0(d0[0]),.D1(d1d),.CE(1'b1),.CLR(1'b0),.PRE(1'b0));

  FD_1 i_t0 (.C(c0), .D(t), .Q(t0));

  FD i_t1 (.C(c0), .D(t0), .Q(t1));

  FD i_tr (.C(c270), .D(t1), .Q(tr));

  FD_1 #(.INIT(1'b1)) i_t0 (.C(c0), .D(t), .Q(t0));

  FD  #(.INIT(1'b1))  i_t1 (.C(c0), .D(t0), .Q(t1));

  FD  #(.INIT(1'b1))  i_tr (.C(c270), .D(t1), .Q(tr));

  IDDR2 i_qq(.Q0(q00),.Q1(q[1]),.C0(c0),.C1(!c0),.CE(1'b1), .D(qp), .R(1'b0), .S(1'b0) );	 

// synthesis translate_off

    defparam i_t0.INIT = 1'b1;

    defparam i_t1.INIT = 1'b1;

    defparam i_tr.INIT = 1'b1;

// synthesis translate_on

// synthesis attribute INIT of i_t0 is "1" 

// synthesis attribute INIT of i_t1 is "1" 

// synthesis attribute INIT of i_tr is "1" 



// synthesis attribute IOB of i_dr is "TRUE"

// synthesis attribute IOB of i_tr is "TRUE"
@@ -552,25 +540,9 @@ module dqs2 (c0,/*c90,*/c270, 
    inout UDQS, LDQS;

    output udqsr90,ldqsr90,udqsr270,ldqsr270;

    wire  t0,t1,t2,tr;

    FD_1    i_t0 (.C(c0),.D(t),.Q(t0));

    FD      i_t1 (.C(c0),.D(t0),.Q(t1));

    FD      i_t2 (.C(c270),.D(t0),.Q(t2));

//    FDDRCPE i_tr (.Q(tr),.C0(c0),.C1(c270),.D0(t),.D1(t | t0),.CE(1'b1),.CLR(1'b0),.PRE(1'b0));

//    FDDRCPE i_tr (.Q(tr),.C0(c0),.C1(c270),.D0(t0),.D1(t0 | t1),.CE(1'b1),.CLR(1'b0),.PRE(1'b0));

//    assign tr= t1 || t2;   // ************** try this later if delays will be too high ***********************

    assign tr= t1;

    dqs2_0 i_dqsu(.c0(c0),/*.c90(c90),*/.c270(c270),.t(tr),.q({udqsr270,udqsr90}),.dq(UDQS));

    dqs2_0 i_dqsl(.c0(c0),/*.c90(c90),*/.c270(c270),.t(tr),.q({ldqsr270,ldqsr90}),.dq(LDQS));

// synthesis translate_off

    defparam i_t0.INIT = 1'b1;

    defparam i_t1.INIT = 1'b1;

    defparam i_t2.INIT = 1'b1;

// synthesis translate_on

// synthesis attribute INIT of i_t0 is "1" 

// synthesis attribute INIT of i_t1 is "1" 

// synthesis attribute INIT of i_t2 is "1" 

// s---ynthesis attribute KEEP_HIERARCHY of i_t0 is "TRUE"

// s---ynthesis attribute KEEP_HIERARCHY of i_tr is "TRUE"

    FD_1    #(.INIT(1'b1)) i_t0 (.C(c0),.D(t),.Q(t0));

    FD      #(.INIT(1'b1)) i_t1 (.C(c0),.D(t0),.Q(t1));

    FD      #(.INIT(1'b1)) i_t2 (.C(c270),.D(t0),.Q(t2));

endmodule



module dqs2_0(c0,/*c90,*/c270,t,q,dq);
@@ -591,11 +563,8 @@ module dqs2_0(c0,/*c90,*/c270,t,q,dq); 




// as in  IFDDRCPE.v

//    FDCPE i_q0 (.C(c90), .CE(1'b1),.CLR(1'b0),.D(qp),.PRE(1'b0),.Q(q[0]));

    FDCPE_1 i_q0 (.C(c270), .CE(1'b1),.CLR(1'b0),.D(qp),.PRE(1'b0),.Q(q[0]));

    defparam i_q0.INIT = 1'b0;

    FDCPE_1  #(.INIT(1'b1)) i_q0 (.C(c270), .CE(1'b1),.CLR(1'b0),.D(qp),.PRE(1'b0),.Q(q[0]));

    FDCPE                   i_q1 (.C(c270),.CE(1'b1),.CLR(1'b0),.D(qp),.PRE(1'b0),.Q(q[1]));

//    defparam i_q1.INIT = 1'b0;

// synthesis attribute IOB of i_q0 is "TRUE"

// synthesis attribute IOB of i_q1 is "TRUE"

// synthesis attribute FAST of i_dq is "TRUE"
@@ -669,15 +638,10 @@ module sdo0_2(c,d,q); // input at rising edge, resyncs to falling, initializes t 
    output q;

wire d0, dr;

OBUF i_q  (.I(dr), .O(q));

FD i_d0   (.C(c), .D(d), .Q(d0));

FD   #(.INIT(1'b1)) i_d0   (.C(c), .D(d), .Q(d0));

//FD_1 i_dr (.C(c), .D(d), .Q(dr));

FD_1 i_dr (.C(c), .D(d0), .Q(dr));

//synthesis translate_off

 defparam i_dr.INIT = 1'b1;

//synthesis translate_on

//synthesis attribute INIT of i_dr is "1" 

FD_1 #(.INIT(1'b1)) i_dr (.C(c), .D(d0), .Q(dr));

// synthesis attribute IOB of i_dr is "TRUE"

//synthesis attribute INIT of i_d0 is "1" 



endmodule