Commit fbce217a authored by Andrey Filippov's avatar Andrey Filippov

minor code fixes to make it simulate with iverilog

parent 63198817
...@@ -8,4 +8,11 @@ ...@@ -8,4 +8,11 @@
</buildSpec> </buildSpec>
<natures> <natures>
</natures> </natures>
<linkedResources>
<link>
<name>ise_logs/ISEPartgen.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISEPartgen-20150725173339957.log</location>
</link>
</linkedResources>
</projectDescription> </projectDescription>
...@@ -246,8 +246,8 @@ module camsync (sclk, // @negedge ...@@ -246,8 +246,8 @@ module camsync (sclk, // @negedge
if (set_period) rep_en <= !high_zero; if (set_period) rep_en <= !high_zero;
end end
MSRL16 i_start_pclk16 (.Q(start_pclk16), .A('hf), .CLK(pclk), .D(start_pclk[2])); MSRL16 i_start_pclk16 (.Q(start_pclk16), .A(4'hf), .CLK(pclk), .D(start_pclk[2]));
MSRL16 i_strigger1_dly16(.Q(trigger1_dly16), .A('hf), .CLK(pclk), .D(trigger1)); MSRL16 i_strigger1_dly16(.Q(trigger1_dly16), .A(4'hf), .CLK(pclk), .D(trigger1));
//! synchronize start from sclk to pclk //! synchronize start from sclk to pclk
//! Generating repetition (period should be exactly N, not N+/-1) and output pulse //! Generating repetition (period should be exactly N, not N+/-1) and output pulse
......
...@@ -225,7 +225,7 @@ module ddr (Dq, Dqs, Addr, Ba, Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Dm); ...@@ -225,7 +225,7 @@ module ddr (Dq, Dqs, Addr, Ba, Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Dm);
assign Dq = Dq_out; assign Dq = Dq_out;
// Debug message // Debug message
wire Debug = 1'b1; // wire Debug = 1'b1;
// Timing Check // Timing Check
time MRD_chk; time MRD_chk;
......
...@@ -311,6 +311,7 @@ imu_timestamps i_imu_timestamps ( ...@@ -311,6 +311,7 @@ imu_timestamps i_imu_timestamps (
.ts_ackn(timestamp_ackn[3:0]), // timestamp for this channel is stored .ts_ackn(timestamp_ackn[3:0]), // timestamp for this channel is stored
.ra({channel[1:0],timestamp_sel[1:0]}), // read address (2 MSBs - channel number, 2 LSBs - usec_low, (usec_high ORed with channel <<24), sec_low, sec_high .ra({channel[1:0],timestamp_sel[1:0]}), // read address (2 MSBs - channel number, 2 LSBs - usec_low, (usec_high ORed with channel <<24), sec_low, sec_high
.dout(timestamps_rdata[15:0]));// output data .dout(timestamps_rdata[15:0]));// output data
wire [0:0] debug_state_unused;
rs232_rcv i_rs232_rcv (.xclk(xclk), // half frequency (80 MHz nominal) rs232_rcv i_rs232_rcv (.xclk(xclk), // half frequency (80 MHz nominal)
.bitHalfPeriod(bitHalfPeriod[15:0]), // half of the serial bit duration, in xclk cycles .bitHalfPeriod(bitHalfPeriod[15:0]), // half of the serial bit duration, in xclk cycles
.ser_di(ser_di), // rs232 (ttl) serial data in .ser_di(ser_di), // rs232 (ttl) serial data in
...@@ -322,7 +323,7 @@ rs232_rcv i_rs232_rcv (.xclk(xclk), // half frequency (80 MHz nominal) ...@@ -322,7 +323,7 @@ rs232_rcv i_rs232_rcv (.xclk(xclk), // half frequency (80 MHz nominal)
.ser_do(ser_do), // serial data out(@posedge xclk) LSB first! .ser_do(ser_do), // serial data out(@posedge xclk) LSB first!
.ser_do_stb(ser_do_stb), // output data strobe (@posedge xclk), first cycle after ser_do becomes valid .ser_do_stb(ser_do_stb), // output data strobe (@posedge xclk), first cycle after ser_do becomes valid
// .debug(debug_state[4:0]), // .debug(debug_state[4:0]),
.debug(debug_state[15:12]), .debug({debug_state_unused,debug_state[15:12]}),
.bit_dur_cntr(debug_state[31:16]), .bit_dur_cntr(debug_state[31:16]),
.bit_cntr(debug_state[11:7]) .bit_cntr(debug_state[11:7])
); );
......
...@@ -497,16 +497,18 @@ myRAM_WxD_D #( .DATA_WIDTH(22),.DATA_DEPTH(2)) ...@@ -497,16 +497,18 @@ myRAM_WxD_D #( .DATA_WIDTH(22),.DATA_DEPTH(2))
reg [15:0] linAddr; reg [15:0] linAddr;
// wire [15:0] linAddr; //replacing with latches to ease timing // wire [15:0] linAddr; //replacing with latches to ease timing
wire [15:0] linAddr_input; wire [15:0] linAddr_input;
// assign linAddr_input[15:0] = (padlen[4:0]*{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]}) +{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]}; // Result MSB not used wire [4:0] descr_stat_inc=descr_stat[8:4]+1;
assign linAddr_input[15:0] = padlen[4:0]*{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]}; assign linAddr_input[15:0] = padlen[4:0]*{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]};
always @ (negedge clk) if (stepsEn[1]) begin // address should be 1 always @ (negedge clk) if (stepsEn[1]) begin // address should be 1
//memctrl353/descrproc353.v:504: error: Concatenation operand "((descr_dyn['sd4:'sd0])==(descr_stat['sd13:'sd9]))?((descr_stat['sd8:'sd4])+('sd1)):(5'd0)" has indefinite width.
// seq_par[5:0] <= mode?({1'b0,descr_stat[13:9]}+((descr_stat[8:4]==5'h1f)?2'h2:2'h1)): //fixed bug with pages where number of hor. tiles is multiple of 0x10
// ({1'b0,(descr_dyn[4:0]==descr_stat[13:9])?(descr_stat[8:4]+1):5'b0});
seq_par[5:0] <= mode?({1'b0,descr_stat[13:9]}+((descr_stat[8:4]==5'h1f)?2'h2:2'h1)): //fixed bug with pages where number of hor. tiles is multiple of 0x10 seq_par[5:0] <= mode?({1'b0,descr_stat[13:9]}+((descr_stat[8:4]==5'h1f)?2'h2:2'h1)): //fixed bug with pages where number of hor. tiles is multiple of 0x10
({1'b0,(descr_dyn[4:0]==descr_stat[13:9])?(descr_stat[8:4]+1):5'b0}); ({1'b0,(descr_dyn[4:0]==descr_stat[13:9])?(descr_stat_inc):5'b0});
sa[7:3] <= mode?descr_dyn[4:0]:5'b0; sa[7:3] <= mode?descr_dyn[4:0]:5'b0;
linAddr[15:0] <= linAddr_input[15:0]; linAddr[15:0] <= linAddr_input[15:0];
// linAddr[15:0] <= (padlen[4:0]*{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]})+{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]}; // Result MSB not used
nxtTL <= nxtTLw; nxtTL <= nxtTLw;
tileX[ 9:0] <= nxtTLw? 10'b0 : (descr_dyn[9:0]+1); // bits [9:5] are garbage if (mode==0) tileX[ 9:0] <= nxtTLw? 10'b0 : (descr_dyn[9:0]+1); // bits [9:5] are garbage if (mode==0)
......
...@@ -174,14 +174,14 @@ module lens_flat (sclk, /// system clock @negedge ...@@ -174,14 +174,14 @@ module lens_flat (sclk, /// system clock @negedge
// .A(FXY[17]?18'h1ffff:FXY[17:0]), // 18-bit multiplier input // .A(FXY[17]?18'h1ffff:FXY[17:0]), // 18-bit multiplier input
.A((FXY[18]==FXY[17])?FXY[17:0]:(FXY[18]?18'h20000:18'h1ffff)), // 18-bit multiplier input .A((FXY[18]==FXY[17])?FXY[17:0]:(FXY[18]?18'h20000:18'h1ffff)), // 18-bit multiplier input
.B({1'b0,scales[~color[1:0]]}), // 18-bit multiplier input .B({1'b0,scales[~color[1:0]]}), // 18-bit multiplier input
.BCIN(0), // 18-bit cascade input .BCIN(18'b0), // 18-bit cascade input
.CEA(lens_corr_out[0]), // Clock enable input for the A port .CEA(lens_corr_out[0]), // Clock enable input for the A port
.CEB(lens_corr_out[0]), // Clock enable input for the B port .CEB(lens_corr_out[0]), // Clock enable input for the B port
.CEP(lens_corr_out[1]), // Clock enable input for the P port .CEP(lens_corr_out[1]), // Clock enable input for the P port
.CLK(pclk), // Clock input .CLK(pclk), // Clock input
.RSTA(0), // Synchronous reset input for the A port .RSTA(1'b0), // Synchronous reset input for the A port
.RSTB(0), // Synchronous reset input for the B port .RSTB(1'b0), // Synchronous reset input for the B port
.RSTP(0) // Synchronous reset input for the P port .RSTP(1'b0) // Synchronous reset input for the P port
); );
...@@ -195,14 +195,14 @@ module lens_flat (sclk, /// system clock @negedge ...@@ -195,14 +195,14 @@ module lens_flat (sclk, /// system clock @negedge
.P(mult_second_res[35:0]), // 36-bit multiplier output .P(mult_second_res[35:0]), // 36-bit multiplier output
.A(pix_zero[17:0]), // 18-bit multiplier input .A(pix_zero[17:0]), // 18-bit multiplier input
.B(mult_first_scaled[17:0]), // 18-bit multiplier input - always positive .B(mult_first_scaled[17:0]), // 18-bit multiplier input - always positive
.BCIN(0), // 18-bit cascade input .BCIN(18'b0), // 18-bit cascade input
.CEA(lens_corr_out[2]), // Clock enable input for the A port .CEA(lens_corr_out[2]), // Clock enable input for the A port
.CEB(lens_corr_out[0]), // Clock enable input for the B port .CEB(lens_corr_out[0]), // Clock enable input for the B port
.CEP(lens_corr_out[3]), // Clock enable input for the P port .CEP(lens_corr_out[3]), // Clock enable input for the P port
.CLK(pclk), // Clock input .CLK(pclk), // Clock input
.RSTA(0), // Synchronous reset input for the A port .RSTA(1'b0), // Synchronous reset input for the A port
.RSTB(0), // Synchronous reset input for the B port .RSTB(1'b0), // Synchronous reset input for the B port
.RSTP(0) // Synchronous reset input for the P port .RSTP(1'b0) // Synchronous reset input for the P port
); );
...@@ -216,7 +216,7 @@ lens_flat_line #(.F_WIDTH(19), /// number of bits in the output result (signed) ...@@ -216,7 +216,7 @@ lens_flat_line #(.F_WIDTH(19), /// number of bits in the output result (signed)
.first(fstart), /// initialize running parameters from the inputs (first column). Should be at least 1-cycle gap between "first" and first "next" .first(fstart), /// initialize running parameters from the inputs (first column). Should be at least 1-cycle gap between "first" and first "next"
.next(newline), /// calcualte next pixel .next(newline), /// calcualte next pixel
.F0(C[18:0]), /// value of the output in the first column (before saturation), 18 bit, unsigned .F0(C[18:0]), /// value of the output in the first column (before saturation), 18 bit, unsigned
.ERR0(0), /// initial value of the running error (-2.0<err<+2.0), scaled by 2^22, so 24 bits .ERR0(24'b0), /// initial value of the running error (-2.0<err<+2.0), scaled by 2^22, so 24 bits
.A0(AY[18:0]), /// Ay .A0(AY[18:0]), /// Ay
.B0(BY[20:0]), /// By, signed .B0(BY[20:0]), /// By, signed
.F(FY[18:0]), .F(FY[18:0]),
......
...@@ -72,10 +72,11 @@ NET "hact_length*" TIG; ...@@ -72,10 +72,11 @@ NET "hact_length*" TIG;
*/ */
parameter MIN_VACT_PERIOD=130; // 3-130, to increase maximal value (130) - chnge counter width parameter MIN_VACT_PERIOD=130; // 3-130, to increase maximal value (130) - chnge counter width
`ifdef IVERILOG
parameter IS_SIMUL=0;
//synthesis translate_off
parameter IS_SIMUL=1; parameter IS_SIMUL=1;
`else
parameter IS_SIMUL=0;
`endif
//synthesis translate_on //synthesis translate_on
input cclk; // command clock (posedge, invert on input if needed) input cclk; // command clock (posedge, invert on input if needed)
......
...@@ -533,20 +533,20 @@ wire sensor_trigger; // signal to start CMOS sensor in sync mode ...@@ -533,20 +533,20 @@ wire sensor_trigger; // signal to start CMOS sensor in sync mode
wire confirmFrame2Compressor; // pulse to start reading a new frame to buffer for compressor (generated at start of each frame by the compressor) wire confirmFrame2Compressor; // pulse to start reading a new frame to buffer for compressor (generated at start of each frame by the compressor)
// mcontr will stop to read to channel FIFO at the end of frame, wait for confirmation // mcontr will stop to read to channel FIFO at the end of frame, wait for confirmation
`ifdef debug_compressor `ifdef debug_compressor
wire [31:0] printk_compressor; wire [31:0] printk_compressor;
`endif `endif
//ia //ia
`ifdef debug_stuffer `ifdef debug_stuffer
wire [7:0] testwire; wire [7:0] testwire;
//wire [31:0] printk; //wire [31:0] printk;
wire [3:0] tst_stuf_etrax; wire [3:0] tst_stuf_etrax;
reg [3:0] tst_cmd_cntr; reg [3:0] tst_cmd_cntr;
reg tst_rdy_after_eot; reg tst_rdy_after_eot;
// ,.test1( test_fifo[3:0]) // ,.test1( test_fifo[3:0])
// ,.test2( test_dma_wcntr[3:0]) // ,.test2( test_dma_wcntr[3:0])
wire dma0_enabled; // just for debug wire dma0_enabled; // just for debug
wire dma1_enabled; // just for debug wire dma1_enabled; // just for debug
`endif `endif
`ifdef debug_dma_count `ifdef debug_dma_count
wire [31:0] printk; wire [31:0] printk;
......
...@@ -40,6 +40,13 @@ module testbench353(); ...@@ -40,6 +40,13 @@ module testbench353();
parameter CLK1_PER = 10.4; //96MHz parameter CLK1_PER = 10.4; //96MHz
parameter CLK3_PER = 83.33; //12MHz parameter CLK3_PER = 83.33; //12MHz
parameter CPU_PER=10.4; parameter CPU_PER=10.4;
`ifdef IVERILOG
initial $display("IVERILOG is defined");
`include "IVERILOG_INCLUDE.v"
`else
initial $display("IVERILOG is not defined");
parameter lxtname = "x353_1.lxt";
`endif
`ifdef SYNC_COMPRESS `ifdef SYNC_COMPRESS
parameter DEPEND=1'b1; parameter DEPEND=1'b1;
...@@ -552,7 +559,8 @@ defparam i_sensor12bits.trigdly = TRIG_LINES; // delay between trigger input a ...@@ -552,7 +559,8 @@ defparam i_sensor12bits.trigdly = TRIG_LINES; // delay between trigger input a
initial begin initial begin
$dumpfile("x353.lxt"); // $dumpfile("x353.lxt");
$dumpfile(lxtname);
$dumpvars(0,testbench353); $dumpvars(0,testbench353);
TTRIG = 1; TTRIG = 1;
CLK3 = 0; CLK3 = 0;
...@@ -598,7 +606,7 @@ defparam i_sensor12bits.trigdly = TRIG_LINES; // delay between trigger input a ...@@ -598,7 +606,7 @@ defparam i_sensor12bits.trigdly = TRIG_LINES; // delay between trigger input a
wait (IMU_CS); // wait IMU inactive wait (IMU_CS); // wait IMU inactive
IMU_103695REVA = 1'b1; // switch to revision "A" IMU_103695REVA <= 1'b1; // switch to revision "A"
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
cpu_wr(X313_WA_IMU_DATA, 'h5c0000); // set debug_config to 4'h7 cpu_wr(X313_WA_IMU_DATA, 'h5c0000); // set debug_config to 4'h7
...@@ -768,6 +776,7 @@ $finish; ...@@ -768,6 +776,7 @@ $finish;
//#250000; //#250000;
// dma_en(0,1); // dma_en(0,1);
//#480000; //#480000;
dma_en(0,1); dma_en(0,1);
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
...@@ -778,7 +787,7 @@ $finish; ...@@ -778,7 +787,7 @@ $finish;
wait (IMU_CS); // wait IMU inactive wait (IMU_CS); // wait IMU inactive
IMU_103695REVA = 1'b1; // switch to revision "A" IMU_103695REVA <= 1'b1; // switch to revision "A"
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
cpu_wr(X313_WA_IMU_DATA, 'h5c0000); // set debug_config to 4'h7 cpu_wr(X313_WA_IMU_DATA, 'h5c0000); // set debug_config to 4'h7
......
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