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Commit f5c2e000 authored by Andrey Filippov's avatar Andrey Filippov
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generated working bitsteram file for NC353 with ISE 14.7

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.project
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......@@ -12,62 +12,67 @@
<link>
<name>ise_logs/ISEBitgen.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISEBitgen-20150727202331879.log</location>
<location>/home/andrey/git/x353/ise_logs/ISEBitgen-20150728154046694.log</location>
</link>
<link>
<name>ise_logs/ISEMap.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISEMap-20150727201724222.log</location>
<location>/home/andrey/git/x353/ise_logs/ISEMap-20150728154015412.log</location>
</link>
<link>
<name>ise_logs/ISENGDBuild.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISENGDBuild-20150727201724222.log</location>
<location>/home/andrey/git/x353/ise_logs/ISENGDBuild-20150728152925685.log</location>
</link>
<link>
<name>ise_logs/ISEPAR.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISEPAR-20150727202331879.log</location>
<location>/home/andrey/git/x353/ise_logs/ISEPAR-20150728154046694.log</location>
</link>
<link>
<name>ise_logs/ISEPartgen.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISEPartgen-20150726172041010.log</location>
</link>
<link>
<name>ise_logs/ISEReportGen.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISEReportGen-20150728154526166.log</location>
</link>
<link>
<name>ise_logs/ISETraceMap.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISETraceMap-20150727201724222.log</location>
<location>/home/andrey/git/x353/ise_logs/ISETraceMap-20150728154015412.log</location>
</link>
<link>
<name>ise_logs/ISETracePAR.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISETracePAR-20150727202331879.log</location>
<location>/home/andrey/git/x353/ise_logs/ISETracePAR-20150728154046694.log</location>
</link>
<link>
<name>ise_logs/ISExst.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISExst-20150727201317048.log</location>
<location>/home/andrey/git/x353/ise_logs/ISExst-20150728152838290.log</location>
</link>
<link>
<name>ise_state/x353-map.tgz</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_state/x353-map-20150727201724222.tgz</location>
<location>/home/andrey/git/x353/ise_state/x353-map-20150728154015412.tgz</location>
</link>
<link>
<name>ise_state/x353-ngdbuild.tgz</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_state/x353-ngdbuild-20150727201724222.tgz</location>
<location>/home/andrey/git/x353/ise_state/x353-ngdbuild-20150728152925685.tgz</location>
</link>
<link>
<name>ise_state/x353-par.tgz</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_state/x353-par-20150727202331879.tgz</location>
<location>/home/andrey/git/x353/ise_state/x353-par-20150728154046694.tgz</location>
</link>
<link>
<name>ise_state/x353-synth.tgz</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_state/x353-synth-20150727201317048.tgz</location>
<location>/home/andrey/git/x353/ise_state/x353-synth-20150728152838290.tgz</location>
</link>
</linkedResources>
</projectDescription>
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Release 14.7 - Bitgen P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '3s1200e.nph' in environment
/opt/Xilinx/14.7/ISE_DS/ISE/.
"x353" is an NCD, version 3.2, device xc3s1200e, package ft256, speed -4
Opened constraints file x353.pcf.
Tue Jul 28 15:43:52 2015
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/bitgen -w x353.ncd x353.bit x353.pcf
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name | Current Setting |
+----------------------+----------------------+
| Compress | (Not Specified)* |
+----------------------+----------------------+
| Readback | (Not Specified)* |
+----------------------+----------------------+
| CRC | Enable* |
+----------------------+----------------------+
| DebugBitstream | No* |
+----------------------+----------------------+
| ConfigRate | 1* |
+----------------------+----------------------+
| StartupClk | Cclk* |
+----------------------+----------------------+
| DCMShutdown | Disable* |
+----------------------+----------------------+
| DonePin | Pullup* |
+----------------------+----------------------+
| ProgPin | Pullup* |
+----------------------+----------------------+
| TckPin | Pullup* |
+----------------------+----------------------+
| TdiPin | Pullup* |
+----------------------+----------------------+
| TdoPin | Pullup* |
+----------------------+----------------------+
| TmsPin | Pullup* |
+----------------------+----------------------+
| UnusedPin | Pulldown* |
+----------------------+----------------------+
| GWE_cycle | 6* |
+----------------------+----------------------+
| GTS_cycle | 5* |
+----------------------+----------------------+
| LCK_cycle | NoWait* |
+----------------------+----------------------+
| DONE_cycle | 4* |
+----------------------+----------------------+
| Persist | No* |
+----------------------+----------------------+
| DriveDone | No* |
+----------------------+----------------------+
| DonePipe | No* |
+----------------------+----------------------+
| Security | None* |
+----------------------+----------------------+
| UserID | 0xFFFFFFFF* |
+----------------------+----------------------+
| MultiBootMode | No* |
+----------------------+----------------------+
| ActivateGclk | No* |
+----------------------+----------------------+
| ActiveReconfig | No* |
+----------------------+----------------------+
| PartialMask0 | (Not Specified)* |
+----------------------+----------------------+
| PartialMask1 | (Not Specified)* |
+----------------------+----------------------+
| PartialMask2 | (Not Specified)* |
+----------------------+----------------------+
| PartialGclk | (Not Specified)* |
+----------------------+----------------------+
| PartialLeft | (Not Specified)* |
+----------------------+----------------------+
| PartialRight | (Not Specified)* |
+----------------------+----------------------+
| TimeStamp | Default* |
+----------------------+----------------------+
| IEEE1532 | No* |
+----------------------+----------------------+
| Binary | No* |
+----------------------+----------------------+
* Default setting.
** The specified setting matches the default setting.
There were 0 CONFIG constraint(s) processed from x353.pcf.
Running DRC.
WARNING:PhysDesignRules:372 - Gated clock. Clock net i_sensorpads/fifo_clkin is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cb_xt_pol_virt_trig_MUX_728_o is sourced by a combinatorial pin. This is not
good design practice. Use the CE pin to control the loading of data into the
flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net compressor_eot is sourced
by a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:1063 - Issue with pin connections and/or configuration
on block:<i_compressor/i_color_proc/i_y_buff.A>:<RAMB16_RAMB16A>. The block
is configured to use an input parity pins. There is a dangling output parity
pin.
WARNING:PhysDesignRules:1067 - Issue with pin connections and/or configuration
on block:<i_sensorpix/i_cstableh.B>:<RAMB16_RAMB16B>. The block is
configured to use an input parity pin. There is a dangling output parity pin.
WARNING:PhysDesignRules:1067 - Issue with pin connections and/or configuration
on block:<i_sensorpix/i_cstablel.B>:<RAMB16_RAMB16B>. The block is
configured to use an input parity pin. There is a dangling output parity pin.
WARNING:PhysDesignRules:1063 - Issue with pin connections and/or configuration
on block:<i_compressor/i_color_proc/i_CrCb_buff.A>:<RAMB16_RAMB16A>. The
block is configured to use an input parity pins. There is a dangling output
parity pin.
DRC detected 0 errors and 7 warnings. Please see the previously displayed
individual error or warning messages for more details.
Creating bit map...
Saving bit stream in "x353.bit".
Bitstream generation is complete.
ISE_14_7_results/x353.bld 0 → 100644
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Release 14.7 ngdbuild P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Command Line: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -p
xc3s1200eft256-4 x353.ngc x353.ngd
Reading NGO file "/home/xilinx/vdt_ise/x353/x353.ngc" ...
Gathering constraint information from source properties...
Done.
Resolving constraint associations...
Checking Constraint Associations...
WARNING:ConstraintSystem - For the pattern match
'LATCHES('i_compressor/i_huffman/i_stuffer_was_rdy_early')', no signals were
found to match the pattern 'i_compressor/i_huffman/i_stuffer_was_rdy_early'.
This patern match is used in the following groups and/or specifications:
<TIMEGRP TG_STUFFER_WAS_READY_EARLY =
LATCHES("i_compressor/i_huffman/i_stuffer_was_rdy_early");>
Since no appropriate elements were found for the group
'LATCHES('i_compressor/i_huffman/i_stuffer_was_rdy_early')', this group has
been removed from the design. Note that patterns for TIMEGRP will match only
signals driven by the given type of element, not instance names. To create a
group using an instance name pattern, use the INST keyword to attach a TNM.
WARNING:ConstraintSystem - TNM : TNM_PCLK was distributed to a DCM but new TNM
constraints were not derived. This TNM is used in the following user groups
or specifications:
<TIMESPEC TS_PCLK_GCLK_IDATA = FROM "TNM_PCLK" TO "TNM_GCLK_IDATA" TIG;>
<TIMESPEC TS_GCLK_IDATA_PCLK = FROM "TNM_GCLK_IDATA" TO "TNM_PCLK" TIG;>
<TIMESPEC TS_PCLK_PCLK2X = FROM "TNM_PCLK" TO "TNM_PCLK2X" TIG;>
WARNING:ConstraintSystem:56 - Constraint <TIMESPEC
TS_i_sensorpads_i_sensor_phase_dcm_out0 = PERIOD
"i_sensorpads_i_sensor_phase_dcm_out0" TS_CLK1 HIGH 50%>: Unable to find an
active 'TNM' constraint named 'i_sensorpads_i_sensor_phase_dcm_out0'.
INFO:ConstraintSystem:178 - TNM 'CLK0', used in period specification 'TS_CLK0',
was traced into DCM_SP instance i_iclockios/i_dcm1. The following new TNM
groups and period specifications were generated at the DCM_SP output(s):
CLK0: <TIMESPEC TS_i_iclockios_isclk0 = PERIOD "i_iclockios_isclk0" TS_CLK0
HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'CLK0', used in period specification 'TS_CLK0',
was traced into DCM_SP instance i_iclockios/i_dcm1. The following new TNM
groups and period specifications were generated at the DCM_SP output(s):
CLK270: <TIMESPEC TS_i_iclockios_isclk270 = PERIOD "i_iclockios_isclk270"
TS_CLK0 PHASE 5325 ps HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'CLK1', used in period specification 'TS_CLK1',
was traced into DCM_SP instance i_sensorpads/i_dcm4. The following new TNM
groups and period specifications were generated at the DCM_SP output(s):
CLK2X: <TIMESPEC TS_i_sensorpads_pclk2xi = PERIOD "i_sensorpads_pclk2xi"
TS_CLK1 / 2 HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'CLK1', used in period specification 'TS_CLK1',
was traced into DCM_SP instance i_sensorpads/i_sensor_phase/i_dcm_sensor. The
following new TNM groups and period specifications were generated at the
DCM_SP output(s):
CLK90: <TIMESPEC TS_i_sensorpads_i_sensor_phase_pre_pre_en_idata = PERIOD
"i_sensorpads_i_sensor_phase_pre_pre_en_idata" TS_CLK1 PHASE 2600 ps HIGH
50%>
INFO:ConstraintSystem:178 - TNM 'CLK1', used in period specification 'TS_CLK1',
was traced into DCM_SP instance i_sensorpads/i_sensor_phase/i_dcm_sensor. The
following new TNM groups and period specifications were generated at the
DCM_SP output(s):
CLK180: <TIMESPEC TS_i_sensorpads_i_sensor_phase_pre_pre_en_idata90 = PERIOD
"i_sensorpads_i_sensor_phase_pre_pre_en_idata90" TS_CLK1 PHASE 5200 ps HIGH
50%>
INFO:ConstraintSystem:178 - TNM 'CLK1', used in period specification 'TS_CLK1',
was traced into DCM_SP instance i_sensorpads/i_sensor_phase/i_dcm_sensor. The
following new TNM groups and period specifications were generated at the
DCM_SP output(s):
CLK2X: <TIMESPEC TS_i_sensorpads_i_sensor_phase_dcm2x = PERIOD
"i_sensorpads_i_sensor_phase_dcm2x" TS_CLK1 / 2 HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'CLK1', used in period specification 'TS_CLK1',
was traced into DCM_SP instance i_sensorpads/i_sensor_phase/i_dcm_sensor. The
following new TNM groups and period specifications were generated at the
DCM_SP output(s):
CLK2X180: <TIMESPEC TS_i_sensorpads_i_sensor_phase_dcm2x180 = PERIOD
"i_sensorpads_i_sensor_phase_dcm2x180" TS_CLK1 / 2 PHASE 2600 ps HIGH 50%>
Done...
WARNING:NgdBuild:1212 - User specified non-default attribute value (8.333330)
was detected for the CLKIN_PERIOD attribute on DCM "i_iclockios/i_dcm1".
This does not match the PERIOD constraint value (7100 ps.). The uncertainty
calculation will use the non-default attribute value. This could result in
incorrect uncertainty calculated for DCM output clocks.
INFO:NgdBuild:1222 - Setting CLKIN_PERIOD attribute associated with DCM instance
i_sensorpads/i_dcm4 to 10.400000 ns based on the period specification
(<TIMESPEC TS_CLK1 = PERIOD "CLK1" 10400.000000 pS HIGH 50.000000 %;>).
INFO:NgdBuild:1222 - Setting CLKIN_PERIOD attribute associated with DCM instance
i_sensorpads/i_sensor_phase/i_dcm_sensor to 10.400000 ns based on the period
specification (<TIMESPEC TS_CLK1 = PERIOD "CLK1" 10400.000000 pS HIGH
50.000000 %;>).
WARNING:NgdBuild:1212 - User specified non-default attribute value (8.333330)
was detected for the CLKIN_PERIOD attribute on DCM "i_dcm333/i_dcm2". This
does not match the PERIOD constraint value (7100 ps.). The uncertainty
calculation will use the non-default attribute value. This could result in
incorrect uncertainty calculated for DCM output clocks.
Checking expanded design ...
WARNING:NgdBuild:446 - LATCH primitive 'i_sysinterface/i_a12/i_q/i_qr' has
unconnected output pin
WARNING:NgdBuild:446 - LATCH primitive 'i_sysinterface/i_a11/i_q/i_qr' has
unconnected output pin
WARNING:NgdBuild:446 - LATCH primitive 'i_sysinterface/i_a10/i_q/i_qr' has
unconnected output pin
WARNING:NgdBuild:446 - LATCH primitive 'i_sysinterface/i_a9/i_q/i_qr' has
unconnected output pin
WARNING:NgdBuild:446 - LATCH primitive 'i_sysinterface/i_a8/i_q/i_qr' has
unconnected output pin
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 10
Total memory usage is 465840 kilobytes
Writing NGD file "x353.ngd" ...
Total REAL time to NGDBUILD completion: 8 sec
Total CPU time to NGDBUILD completion: 8 sec
Writing NGDBUILD log file "x353.bld"...
ISE_14_7_results/x353.drc 0 → 100644
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Release 14.7 Drc P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Tue Jul 28 15:43:52 2015
drc -z x353.ncd x353.pcf
WARNING:PhysDesignRules:372 - Gated clock. Clock net i_sensorpads/fifo_clkin is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cb_xt_pol_virt_trig_MUX_728_o is sourced by a combinatorial pin. This is not
good design practice. Use the CE pin to control the loading of data into the
flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net compressor_eot is sourced
by a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:1063 - Issue with pin connections and/or configuration
on block:<i_compressor/i_color_proc/i_y_buff.A>:<RAMB16_RAMB16A>. The block
is configured to use an input parity pins. There is a dangling output parity
pin.
WARNING:PhysDesignRules:1067 - Issue with pin connections and/or configuration
on block:<i_sensorpix/i_cstableh.B>:<RAMB16_RAMB16B>. The block is
configured to use an input parity pin. There is a dangling output parity pin.
WARNING:PhysDesignRules:1067 - Issue with pin connections and/or configuration
on block:<i_sensorpix/i_cstablel.B>:<RAMB16_RAMB16B>. The block is
configured to use an input parity pin. There is a dangling output parity pin.
WARNING:PhysDesignRules:1063 - Issue with pin connections and/or configuration
on block:<i_compressor/i_color_proc/i_CrCb_buff.A>:<RAMB16_RAMB16A>. The
block is configured to use an input parity pins. There is a dangling output
parity pin.
DRC detected 0 errors and 7 warnings. Please see the previously displayed
individual error or warning messages for more details.
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<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="lin64" product="ISE" version="14.7">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
</document>
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DesignSummary rev="3">
<CmdHistory>
</CmdHistory>
</DesignSummary>
ISE_14_7_results/x353_usage.xml 0 → 100644
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control/dma_fifo353.v
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......@@ -84,6 +84,10 @@ module dma_fifo_sync ( clk, // system clock, 120MHz? (currentle negedge used)
reg firstclk; // generated 1-clk_long pulse as a source for swclk
reg written_burst; // 16 of 16-bit words are just written to FIFO
wire mem_re; // memory RE signal (alo increments counters)
//AF2015: Could not find any iob=true for this register, but it is still duplicated
// OK, it has only sync inputs, so no risk to have different values here and in the IOB
//FlipFlop i_dma_fifo0/dreq has been replicated 1 time(s) to handle iob=true attribute.
//FlipFlop i_dma_fifo1/dreq has been replicated 1 time(s) to handle iob=true attribute.
reg dreq;
reg [1:0] burst_start_sync; // 1 clk long pulse (clk-sync) after start of the DMA burst
reg [1:0] dack_r; // synchronize to clk, dual to prevent metastability
......
sensor/sensor_phase353.v
View file @ f5c2e000
......@@ -293,6 +293,10 @@ BUFGMUX i_pclk (.O(gclk_idata), .I0(dcm2x), .I1(dcm2x180), .S(inv_gclk_idata))
.IBUF_DELAY_VALUE (IBUF_DELAY_SENSOR_VHACT),
.IFD_DELAY_VALUE (IFD_DELAY_SENSOR_VHACT)
) i_vact (.I(VACT), .O(ivact));
// synthesis attribute IOB of i_hact is "TRUE"
// synthesis attribute IOB of i_vact is "TRUE"
always @ (posedge gclk_idata) begin
hact_q1 <= ihact00;
vact_q1 <= ivact00;
......@@ -333,6 +337,20 @@ BUFGMUX i_pclk (.O(gclk_idata), .I0(dcm2x), .I1(dcm2x180), .S(inv_gclk_idata))
FDCE i_idi_9 (.Q(idi[ 9]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 9]));
FDCE i_idi_10 (.Q(idi[10]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[10]));
FDCE i_idi_11 (.Q(idi[11]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[11]));
// are they still needed - seems yes
// synthesis attribute IOB of i_sync_alt_d0 is "TRUE"
// synthesis attribute IOB of i_idi_0 is "TRUE"
// synthesis attribute IOB of i_idi_1 is "TRUE"
// synthesis attribute IOB of i_idi_2 is "TRUE"
// synthesis attribute IOB of i_idi_3 is "TRUE"
// synthesis attribute IOB of i_idi_4 is "TRUE"
// synthesis attribute IOB of i_idi_5 is "TRUE"
// synthesis attribute IOB of i_idi_6 is "TRUE"
// synthesis attribute IOB of i_idi_7 is "TRUE"
// synthesis attribute IOB of i_idi_8 is "TRUE"
// synthesis attribute IOB of i_idi_9 is "TRUE"
// synthesis attribute IOB of i_idi_10 is "TRUE"
// synthesis attribute IOB of i_idi_11 is "TRUE"
reg [1:0] shact_zero; // shact was zero (inactive), sync to gclk_data
always @ (posedge gclk_idata) if (en_idata) begin
......
x353.v
View file @ f5c2e000
......@@ -71,8 +71,8 @@ module x353 #(
parameter SLEW_SENSOR_CLK = "SLOW",
parameter DRIVE_SENSOR_CLK = 4,
parameter IFD_DELAY_SENSOR_PXD = "0",
parameter IFD_DELAY_SENSOR_VHACT ="0",
parameter IFD_DELAY_SENSOR_PXD = "AUTO",
parameter IFD_DELAY_SENSOR_VHACT ="AUTO",
parameter IBUF_DELAY_SENSOR_PXD = "0",
parameter IBUF_DELAY_SENSOR_VHACT ="0",
......@@ -143,7 +143,8 @@ module x353 #(
output BG,
input BRIN,
output BROUT);
parameter MODELREV=32'h0353402b; // adding more bits to motors positions
parameter MODELREV=32'h03535000; // Trying ISE 14.7
// parameter MODELREV=32'h0353402b; // adding more bits to motors positions
// parameter MODELREV=32'h0353402a; // IMU restart after ready (DIO2)
// parameter MODELREV=32'h03534029; // working on IMU
// parameter MODELREV=32'h03534028; // DMA for logging, changing DMA control (neds drivers update)
......
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