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Commit f5c2e000 authored by Andrey Filippov's avatar Andrey Filippov
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generated working bitsteram file for NC353 with ISE 14.7

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.project
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......@@ -12,62 +12,67 @@
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ISE_14_7_results/x353-map.twr 0 → 100644
View file @ f5c2e000
--------------------------------------------------------------------------------
Release 14.7 Trace (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -o x353-map.twr -xml
x353-map.twx x353.ncd x353.pcf
Design file: x353.ncd
Physical constraint file: x353.pcf
Device,package,speed: xc3s1200e,ft256,-4 (PRODUCTION 1.27 2013-10-13)
Report level: summary report, limited to 0 items per constraint
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more
information, see the TSI report. Please consult the Xilinx Command Line
Tools User Guide for information on generating a TSI report.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3284 - This timing report was generated using estimated delay
information. For accurate numbers, please refer to the post Place and Route
timing report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
INFO:Timing:3390 - This architecture does not support a default System Jitter
value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
Uncertainty calculation.
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
'Phase Error' calculations, these terms will be zero in the Clock
Uncertainty calculation. Please make appropriate modification to
SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase
Error.
Number of Timing Constraints that were not applied: 4
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_CLK1 = PERIOD TIMEGRP "CLK1" 10.4 ns H | SETUP | 0.593ns| 9.807ns| 0| 0
IGH 50% | HOLD | 0.424ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_i_sensorpads_pclk2xi = PERIOD TIMEGRP | SETUP | 0.723ns| 4.477ns| 0| 0
"i_sensorpads_pclk2xi" TS_CLK1 / 2 | HOLD | 0.439ns| | 0| 0
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_i_iclockios_isclk0 = PERIOD TIMEGRP "i | SETUP | 0.910ns| 6.190ns| 0| 0
_iclockios_isclk0" TS_CLK0 HIGH 50% | HOLD | 0.380ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_HUFFLATCHESI = MAXDELAY FROM TIMEGRP " | SETUP | 1.212ns| 3.136ns| 0| 0
TG_HUFFFFS" TO TIMEGRP "TG_HUFFLA | | | | |
TCHES" TS_CLK0 * 0.6125 | | | | |
----------------------------------------------------------------------------------------------------------
TS_HUFFLATCHES = MAXDELAY FROM TIMEGRP "T | SETUP | 1.216ns| 3.221ns| 0| 0
G_HUFFLATCHES" TO TIMEGRP "TG_HUF | | | | |
FFFS" TS_CLK0 * 0.625 | | | | |
----------------------------------------------------------------------------------------------------------
TS_i_sensorpads_i_sensor_phase_dcm2x180 = | SETUP | 1.550ns| 2.868ns| 0| 0
PERIOD TIMEGRP "i_sensorpads_i_s | HOLD | 0.451ns| | 0| 0
ensor_phase_dcm2x180" TS_CLK1 / 2 PHASE 2 | MINLOWPULSE | 2.008ns| 3.192ns| 0| 0
.6 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_i_sensorpads_i_sensor_phase_dcm2x = PE | MINLOWPULSE | 2.008ns| 3.192ns| 0| 0
RIOD TIMEGRP "i_sensorpads_i_sens | | | | |
or_phase_dcm2x" TS_CLK1 / 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_i_iclockios_isclk270 = PERIOD TIMEGRP | SETUP | 2.213ns| 2.674ns| 0| 0
"i_iclockios_isclk270" TS_CLK0 PHASE | HOLD | 1.022ns| | 0| 0
5.325 ns HIGH 50% | MINLOWPULSE | 3.908ns| 3.192ns| 0| 0
----------------------------------------------------------------------------------------------------------
TS_HUFFRAMS = MAXDELAY FROM TIMEGRP "TG_H | SETUP | 2.285ns| 3.749ns| 0| 0
UFFRAMS" TO TIMEGRP "TG_HUFFLATCHES" | | | | |
TS_CLK0 * 0.85 | | | | |
----------------------------------------------------------------------------------------------------------
TS_CLK0 = PERIOD TIMEGRP "CLK0" 7.1 ns HI | MINLOWPULSE | 2.300ns| 4.800ns| 0| 0
GH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_HUFFRAMSA = MAXDELAY FROM TIMEGRP "TG_ | SETUP | 4.577ns| 1.546ns| 0| 0
HUFFLATCHES" TO TIMEGRP "TG_HUFFRAMS" | | | | |
TS_CLK0 * 0.8625 | | | | |
----------------------------------------------------------------------------------------------------------
TS_HIST_DOUBLECYC2 = MAXDELAY FROM TIMEGR | SETUP | 5.607ns| 4.793ns| 0| 0
P "TG_HIST_DOUBLE2_SRC" TO TIMEGRP | | | | |
"TG_HIST_DOUBLE2_DST" TS_CLK1 | | | | |
----------------------------------------------------------------------------------------------------------
TS_DOUBLECYCS3 = MAXDELAY FROM TIMEGRP "T | SETUP | 5.752ns| 8.448ns| 0| 0
G_SLOW_SRC3" TO TIMEGRP "TG_DOUBL | | | | |
EDEST3" TS_CLK0 * 2 | | | | |
----------------------------------------------------------------------------------------------------------
TS_OE_TO_DATA = MAXDELAY FROM TIMEGRP "OE | MAXDELAY | 6.110ns| 5.890ns| 0| 0
" TO TIMEGRP "CPU_DATA" 12 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_WR_DATA = MAXDELAY FROM TIMEGRP "CPU_D | SETUP | 6.460ns| 2.540ns| 0| 0
ATA" TO TIMEGRP "TG_CWRDEST" 9 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_AXIS_READ = MAXDELAY FROM TIMEGRP "CPU | MAXDELAY | 6.769ns| 10.231ns| 0| 0
_ADDRCE" TO TIMEGRP "CPU_DATA" 17 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_WE = MAXDELAY FROM TIMEGRP "WE" TO TIM | MAXDELAY | 7.313ns| 4.187ns| 0| 0
EGRP "TNM_CWR" 11.5 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_DOUBLECYC_IDATA = MAXDELAY FROM TIMEGR | SETUP | 8.068ns| 2.332ns| 0| 0
P "TNM_EN_IDATA" TO TIMEGRP "TNM_ | | | | |
EN_IDATA" TS_CLK1 | | | | |
----------------------------------------------------------------------------------------------------------
TS_DACK0 = MAXDELAY FROM TIMEGRP "DACK" T | MAXDELAY | 8.416ns| 8.584ns| 0| 0
O TIMEGRP "ALLPADS" 17 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_DOUBLECYCS2 = MAXDELAY FROM TIMEGRP "T | SETUP | 8.759ns| 5.441ns| 0| 0
G_DOUBLECYCS2" TO TIMEGRP "TG_ALL | | | | |
_SYNC" TS_CLK0 * 2 | | | | |
----------------------------------------------------------------------------------------------------------
TS_i_sensorpads_i_sensor_phase_pre_pre_en | MINPERIOD | 8.804ns| 1.596ns| 0| 0
_idata = PERIOD TIMEGRP "i_sensor | | | | |
pads_i_sensor_phase_pre_pre_en_idata" TS_ | | | | |
CLK1 PHASE 2.6 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_i_sensorpads_i_sensor_phase_pre_pre_en | MINPERIOD | 8.804ns| 1.596ns| 0| 0
_idata90 = PERIOD TIMEGRP "i_sens | | | | |
orpads_i_sensor_phase_pre_pre_en_idata90" | | | | |
TS_CLK1 PHASE 5.2 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
PATH "TS_PCLK_PCLK2X_path" TIG | SETUP | N/A| 1.528ns| N/A| 0
----------------------------------------------------------------------------------------------------------
PATH "TS_GCLK_IDATA_PCLK_path" TIG | SETUP | N/A| 6.317ns| N/A| 0
----------------------------------------------------------------------------------------------------------
PATH "TS_PCLK_GCLK_IDATA_path" TIG | SETUP | N/A| 5.796ns| N/A| 0
----------------------------------------------------------------------------------------------------------
Derived Constraint Report
Derived Constraints for TS_CLK0
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_CLK0 | 7.100ns| 4.800ns| 6.190ns| 0| 0| 0| 34422|
| TS_DOUBLECYCS2 | 14.200ns| 5.441ns| N/A| 0| 0| 457| 0|
| TS_DOUBLECYCS3 | 14.200ns| 8.448ns| N/A| 0| 0| 9051| 0|
| TS_HUFFRAMS | 6.035ns| 3.749ns| N/A| 0| 0| 36| 0|
| TS_HUFFLATCHES | 4.438ns| 3.221ns| N/A| 0| 0| 109| 0|
| TS_HUFFRAMSA | 6.124ns| 1.546ns| N/A| 0| 0| 21| 0|
| TS_HUFFLATCHESI | 4.349ns| 3.136ns| N/A| 0| 0| 105| 0|
| TS_i_iclockios_isclk0 | 7.100ns| 6.190ns| N/A| 0| 0| 24555| 0|
| TS_i_iclockios_isclk270 | 7.100ns| 3.192ns| N/A| 0| 0| 88| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_CLK1
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_CLK1 | 10.400ns| 9.807ns| 8.954ns| 0| 0| 66829| 1872|
| TS_DOUBLECYC_IDATA | 10.400ns| 2.332ns| N/A| 0| 0| 242| 0|
| TS_HIST_DOUBLECYC2 | 10.400ns| 4.793ns| N/A| 0| 0| 117| 0|
| TS_i_sensorpads_pclk2xi | 5.200ns| 4.477ns| N/A| 0| 0| 1393| 0|
| TS_i_sensorpads_i_sensor_phase| 10.400ns| 1.596ns| N/A| 0| 0| 0| 0|
| _pre_pre_en_idata | | | | | | | |
| TS_i_sensorpads_i_sensor_phase| 10.400ns| 1.596ns| N/A| 0| 0| 0| 0|
| _pre_pre_en_idata90 | | | | | | | |
| TS_i_sensorpads_i_sensor_phase| 5.200ns| 3.192ns| N/A| 0| 0| 0| 0|
| _dcm2x | | | | | | | |
| TS_i_sensorpads_i_sensor_phase| 5.200ns| 3.192ns| N/A| 0| 0| 120| 0|
| _dcm2x180 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock BPF
------------+------------+------------+--------------------------------------+--------+
|Max Setup to|Max Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+--------------------------------------+--------+
DCLK | 0.127(R)| 4.639(R)|i_sensorpads/i_sensor_phase/gclk_idata| 2.600|
------------+------------+------------+--------------------------------------+--------+
Setup/Hold to clock CE
------------+------------+------------+------------------+--------+
|Max Setup to|Max Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
D<0> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<1> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<2> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<3> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<4> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<5> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<6> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<7> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<8> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<9> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<10> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<11> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<12> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<13> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<14> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<15> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<16> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<17> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<18> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<19> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<20> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<21> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<22> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<23> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<24> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<25> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<26> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<27> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<28> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<29> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<30> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<31> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock CE1
------------+------------+------------+------------------+--------+
|Max Setup to|Max Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
D<0> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<1> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<2> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<3> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<4> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<5> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<6> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<7> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<8> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<9> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<10> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<11> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<12> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<13> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<14> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<15> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<16> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<17> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<18> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<19> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<20> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<21> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<22> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<23> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<24> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<25> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<26> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<27> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<28> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<29> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<30> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<31> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock CLK1
------------+------------+------------+--------------------------------------+--------+
|Max Setup to|Max Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+--------------------------------------+--------+
DCLK | -1.565(R)| 5.065(R)|i_sensorpads/i_sensor_phase/gclk_idata| 2.600|
------------+------------+------------+--------------------------------------+--------+
Setup/Hold to clock OE
------------+------------+------------+------------------+--------+
|Max Setup to|Max Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
D<0> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<1> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<2> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<3> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<4> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<5> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<6> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<7> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<8> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<9> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<10> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<11> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<12> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<13> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<14> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<15> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<16> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<17> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<18> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<19> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<20> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<21> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<22> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<23> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<24> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<25> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<26> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<27> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<28> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<29> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<30> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<31> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock WE
------------+------------+------------+------------------+--------+
|Max Setup to|Max Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
D<0> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<1> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<2> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<3> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<4> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<5> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<6> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<7> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<8> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<9> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<10> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<11> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<12> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<13> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<14> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<15> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<16> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<17> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<18> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<19> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<20> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<21> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<22> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<23> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<24> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<25> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<26> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<27> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<28> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<29> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<30> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
D<31> | -0.955(R)| 2.949(R)|i_sysinterface/cwr| 0.000|
------------+------------+------------+------------------+--------+
Clock DACK0 to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
D<0> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
D<1> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
D<2> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
D<3> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
D<4> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
D<5> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
D<6> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
D<7> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
D<8> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
D<9> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
D<10> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
D<11> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
D<12> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
D<13> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
D<14> | 12.609(R)|i_dma_fifo0/swclk | 0.000|
D<15> | 12.609(R)|i_dma_fifo0/swclk | 0.000|
D<16> | 12.609(R)|i_dma_fifo0/swclk | 0.000|
D<17> | 12.609(R)|i_dma_fifo0/swclk | 0.000|
D<18> | 12.609(R)|i_dma_fifo0/swclk | 0.000|
D<19> | 12.609(R)|i_dma_fifo0/swclk | 0.000|
D<20> | 12.609(R)|i_dma_fifo0/swclk | 0.000|
D<21> | 12.609(R)|i_dma_fifo0/swclk | 0.000|
D<22> | 12.609(R)|i_dma_fifo0/swclk | 0.000|
D<23> | 12.609(R)|i_dma_fifo0/swclk | 0.000|
D<24> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
D<25> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
D<26> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
D<27> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
D<28> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
D<29> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
D<30> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
D<31> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
------------+------------+------------------+--------+
Clock DACK1 to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
D<0> | 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<1> | 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<2> | 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<3> | 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<4> | 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<5> | 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<6> | 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<7> | 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<8> | 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<9> | 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<10> | 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<11> | 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<12> | 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<13> | 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<14> | 12.609(R)|i_dma_fifo1/swclk | 0.000|
D<15> | 12.609(R)|i_dma_fifo1/swclk | 0.000|
D<16> | 12.609(R)|i_dma_fifo1/swclk | 0.000|
D<17> | 12.609(R)|i_dma_fifo1/swclk | 0.000|
D<18> | 12.609(R)|i_dma_fifo1/swclk | 0.000|
D<19> | 12.609(R)|i_dma_fifo1/swclk | 0.000|
D<20> | 12.609(R)|i_dma_fifo1/swclk | 0.000|
D<21> | 12.609(R)|i_dma_fifo1/swclk | 0.000|
D<22> | 12.609(R)|i_dma_fifo1/swclk | 0.000|
D<23> | 12.609(R)|i_dma_fifo1/swclk | 0.000|
D<24> | 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<25> | 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<26> | 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<27> | 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<28> | 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<29> | 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<30> | 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<31> | 13.092(R)|i_dma_fifo1/swclk | 0.000|
------------+------------+------------------+--------+
Clock OE to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
D<0> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
| 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<1> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
| 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<2> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
| 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<3> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
| 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<4> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
| 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<5> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
| 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<6> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
| 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<7> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
| 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<8> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
| 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<9> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
| 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<10> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
| 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<11> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
| 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<12> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
| 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<13> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
| 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<14> | 12.609(R)|i_dma_fifo0/swclk | 0.000|
| 12.609(R)|i_dma_fifo1/swclk | 0.000|
D<15> | 12.609(R)|i_dma_fifo0/swclk | 0.000|
| 12.609(R)|i_dma_fifo1/swclk | 0.000|
D<16> | 12.609(R)|i_dma_fifo0/swclk | 0.000|
| 12.609(R)|i_dma_fifo1/swclk | 0.000|
D<17> | 12.609(R)|i_dma_fifo0/swclk | 0.000|
| 12.609(R)|i_dma_fifo1/swclk | 0.000|
D<18> | 12.609(R)|i_dma_fifo0/swclk | 0.000|
| 12.609(R)|i_dma_fifo1/swclk | 0.000|
D<19> | 12.609(R)|i_dma_fifo0/swclk | 0.000|
| 12.609(R)|i_dma_fifo1/swclk | 0.000|
D<20> | 12.609(R)|i_dma_fifo0/swclk | 0.000|
| 12.609(R)|i_dma_fifo1/swclk | 0.000|
D<21> | 12.609(R)|i_dma_fifo0/swclk | 0.000|
| 12.609(R)|i_dma_fifo1/swclk | 0.000|
D<22> | 12.609(R)|i_dma_fifo0/swclk | 0.000|
| 12.609(R)|i_dma_fifo1/swclk | 0.000|
D<23> | 12.609(R)|i_dma_fifo0/swclk | 0.000|
| 12.609(R)|i_dma_fifo1/swclk | 0.000|
D<24> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
| 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<25> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
| 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<26> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
| 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<27> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
| 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<28> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
| 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<29> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
| 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<30> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
| 13.092(R)|i_dma_fifo1/swclk | 0.000|
D<31> | 13.092(R)|i_dma_fifo0/swclk | 0.000|
| 13.092(R)|i_dma_fifo1/swclk | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock BPF
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
BPF | 9.807| 1.050| | |
CLK1 | 9.807| 1.050| | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock CE
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
WE | | | -0.955| -0.955|
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock CE1
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
WE | | | -0.955| -0.955|
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock CLK0
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK0 | 5.940| 2.332| 3.221| 8.448|
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock CLK1
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
BPF | 9.807| 1.050| | |
CLK1 | 9.807| 1.050| | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock OE
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
WE | | | -0.955| -0.955|
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock WE
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
WE | | | -0.955| -0.955|
---------------+---------+---------+---------+---------+
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
A<0> |D<0> | 9.910|
A<0> |D<1> | 9.910|
A<0> |D<2> | 9.910|
A<0> |D<3> | 9.910|
A<0> |D<4> | 9.910|
A<0> |D<5> | 9.161|
A<0> |D<6> | 9.161|
A<0> |D<7> | 9.910|
A<0> |D<8> | 9.910|
A<0> |D<9> | 10.231|
A<0> |D<10> | 9.910|
A<0> |D<11> | 9.161|
A<0> |D<12> | 9.427|
A<0> |D<13> | 9.910|
A<0> |D<14> | 8.678|
A<0> |D<15> | 8.678|
A<0> |D<16> | 8.944|
A<0> |D<17> | 8.944|
A<0> |D<18> | 8.623|
A<0> |D<19> | 8.623|
A<0> |D<20> | 8.944|
A<0> |D<21> | 9.427|
A<0> |D<22> | 8.944|
A<0> |D<23> | 9.427|
A<0> |D<24> | 9.106|
A<0> |D<25> | 9.427|
A<0> |D<26> | 9.910|
A<0> |D<27> | 10.231|
A<0> |D<28> | 9.910|
A<0> |D<29> | 9.945|
A<0> |D<30> | 9.910|
A<0> |D<31> | 9.106|
A<1> |D<0> | 9.910|
A<1> |D<1> | 9.910|
A<1> |D<2> | 9.910|
A<1> |D<3> | 9.910|
A<1> |D<4> | 9.910|
A<1> |D<5> | 9.910|
A<1> |D<6> | 9.910|
A<1> |D<7> | 9.910|
A<1> |D<8> | 9.910|
A<1> |D<9> | 10.231|
A<1> |D<10> | 9.910|
A<1> |D<11> | 9.910|
A<1> |D<12> | 9.427|
A<1> |D<13> | 9.910|
A<1> |D<14> | 8.678|
A<1> |D<15> | 8.678|
A<1> |D<16> | 8.944|
A<1> |D<17> | 9.427|
A<1> |D<18> | 9.427|
A<1> |D<19> | 9.427|
A<1> |D<20> | 8.944|
A<1> |D<21> | 9.427|
A<1> |D<22> | 8.944|
A<1> |D<23> | 9.427|
A<1> |D<24> | 9.106|
A<1> |D<25> | 9.427|
A<1> |D<26> | 9.910|
A<1> |D<27> | 10.231|
A<1> |D<28> | 9.910|
A<1> |D<29> | 9.945|
A<1> |D<30> | 9.910|
A<1> |D<31> | 9.106|
A<2> |D<0> | 9.910|
A<2> |D<1> | 9.910|
A<2> |D<2> | 9.910|
A<2> |D<3> | 9.910|
A<2> |D<4> | 9.910|
A<2> |D<5> | 9.910|
A<2> |D<6> | 9.910|
A<2> |D<7> | 9.910|
A<2> |D<8> | 9.910|
A<2> |D<9> | 10.231|
A<2> |D<10> | 9.910|
A<2> |D<11> | 9.910|
A<2> |D<12> | 9.427|
A<2> |D<13> | 9.910|
A<2> |D<14> | 9.427|
A<2> |D<15> | 9.427|
A<2> |D<16> | 8.944|
A<2> |D<17> | 9.427|
A<2> |D<18> | 9.427|
A<2> |D<19> | 9.427|
A<2> |D<20> | 9.427|
A<2> |D<21> | 9.427|
A<2> |D<22> | 9.427|
A<2> |D<23> | 9.427|
A<2> |D<24> | 9.910|
A<2> |D<25> | 9.910|
A<2> |D<26> | 9.910|
A<2> |D<27> | 10.231|
A<2> |D<28> | 9.910|
A<2> |D<29> | 9.945|
A<2> |D<30> | 9.910|
A<2> |D<31> | 9.910|
A<3> |D<0> | 9.161|
A<3> |D<1> | 9.161|
A<3> |D<2> | 9.161|
A<3> |D<3> | 9.161|
A<3> |D<4> | 9.161|
A<3> |D<5> | 9.161|
A<3> |D<6> | 9.161|
A<3> |D<7> | 9.161|
A<3> |D<8> | 9.161|
A<3> |D<9> | 9.161|
A<3> |D<10> | 9.161|
A<3> |D<11> | 9.161|
A<3> |D<12> | 9.161|
A<3> |D<13> | 9.161|
A<3> |D<14> | 9.427|
A<3> |D<15> | 9.427|
A<3> |D<16> | 8.944|
A<3> |D<17> | 9.427|
A<3> |D<18> | 9.427|
A<3> |D<19> | 9.427|
A<3> |D<20> | 9.427|
A<3> |D<21> | 9.427|
A<3> |D<22> | 9.427|
A<3> |D<23> | 9.427|
A<3> |D<24> | 9.910|
A<3> |D<25> | 9.910|
A<3> |D<26> | 9.910|
A<3> |D<27> | 9.161|
A<3> |D<28> | 9.910|
A<3> |D<29> | 9.161|
A<3> |D<30> | 9.106|
A<3> |D<31> | 9.910|
A<4> |D<0> | 8.302|
A<4> |D<1> | 8.302|
A<4> |D<2> | 8.302|
A<4> |D<3> | 8.302|
A<4> |D<4> | 8.302|
A<4> |D<5> | 8.302|
A<4> |D<6> | 8.302|
A<4> |D<7> | 8.302|
A<4> |D<8> | 8.302|
A<4> |D<9> | 8.302|
A<4> |D<10> | 8.302|
A<4> |D<11> | 8.302|
A<4> |D<12> | 8.302|
A<4> |D<13> | 8.302|
A<4> |D<14> | 8.623|
A<4> |D<15> | 8.623|
A<4> |D<16> | 8.944|
A<4> |D<17> | 7.819|
A<4> |D<18> | 8.623|
A<4> |D<19> | 8.623|
A<4> |D<20> | 8.623|
A<4> |D<21> | 8.623|
A<4> |D<22> | 8.623|
A<4> |D<23> | 8.623|
A<4> |D<24> | 9.106|
A<4> |D<25> | 9.106|
A<4> |D<26> | 9.106|
A<4> |D<27> | 8.623|
A<4> |D<28> | 9.106|
A<4> |D<29> | 8.623|
A<4> |D<30> | 8.302|
A<4> |D<31> | 9.106|
A<5> |D<0> | 8.302|
A<5> |D<1> | 8.302|
A<5> |D<2> | 8.302|
A<5> |D<3> | 8.302|
A<5> |D<4> | 8.302|
A<5> |D<5> | 8.302|
A<5> |D<6> | 8.302|
A<5> |D<7> | 8.302|
A<5> |D<8> | 8.302|
A<5> |D<9> | 8.302|
A<5> |D<10> | 8.302|
A<5> |D<11> | 8.302|
A<5> |D<12> | 8.302|
A<5> |D<13> | 8.302|
A<5> |D<14> | 7.819|
A<5> |D<15> | 7.819|
A<5> |D<16> | 8.944|
A<5> |D<17> | 7.819|
A<5> |D<18> | 7.819|
A<5> |D<19> | 7.819|
A<5> |D<20> | 7.819|
A<5> |D<21> | 7.819|
A<5> |D<22> | 7.819|
A<5> |D<23> | 7.819|
A<5> |D<24> | 8.302|
A<5> |D<25> | 8.302|
A<5> |D<26> | 8.302|
A<5> |D<27> | 8.623|
A<5> |D<28> | 8.302|
A<5> |D<29> | 8.623|
A<5> |D<30> | 7.819|
A<5> |D<31> | 8.302|
A<6> |D<0> | 6.694|
A<6> |D<1> | 6.694|
A<6> |D<2> | 6.694|
A<6> |D<3> | 6.694|
A<6> |D<4> | 6.694|
A<6> |D<5> | 5.890|
A<6> |D<6> | 5.890|
A<6> |D<7> | 6.694|
A<6> |D<8> | 6.694|
A<6> |D<9> | 6.694|
A<6> |D<10> | 6.694|
A<6> |D<11> | 6.694|
A<6> |D<12> | 6.694|
A<6> |D<13> | 6.694|
A<6> |D<14> | 5.925|
A<6> |D<15> | 5.925|
A<6> |D<16> | 6.211|
A<6> |D<17> | 5.925|
A<6> |D<18> | 5.925|
A<6> |D<19> | 5.925|
A<6> |D<20> | 5.925|
A<6> |D<21> | 5.925|
A<6> |D<22> | 5.925|
A<6> |D<23> | 5.925|
A<6> |D<24> | 7.819|
A<6> |D<25> | 7.819|
A<6> |D<26> | 7.819|
A<6> |D<27> | 8.302|
A<6> |D<28> | 7.819|
A<6> |D<29> | 8.302|
A<6> |D<30> | 6.729|
A<6> |D<31> | 7.498|
CE |D<0> | 5.890|
CE |D<1> | 5.890|
CE |D<2> | 5.890|
CE |D<3> | 5.890|
CE |D<4> | 5.890|
CE |D<5> | 5.890|
CE |D<6> | 5.890|
CE |D<7> | 5.890|
CE |D<8> | 5.890|
CE |D<9> | 5.890|
CE |D<10> | 5.890|
CE |D<11> | 5.890|
CE |D<12> | 5.890|
CE |D<13> | 5.890|
CE |D<14> | 5.890|
CE |D<15> | 5.890|
CE |D<16> | 5.890|
CE |D<17> | 5.890|
CE |D<18> | 5.890|
CE |D<19> | 5.890|
CE |D<20> | 5.890|
CE |D<21> | 5.890|
CE |D<22> | 5.890|
CE |D<23> | 5.890|
CE |D<24> | 5.890|
CE |D<25> | 5.890|
CE |D<26> | 5.890|
CE |D<27> | 5.890|
CE |D<28> | 5.890|
CE |D<29> | 5.890|
CE |D<30> | 5.890|
CE |D<31> | 5.890|
CE1 |D<0> | 5.890|
CE1 |D<1> | 5.890|
CE1 |D<2> | 5.890|
CE1 |D<3> | 5.890|
CE1 |D<4> | 5.890|
CE1 |D<5> | 5.890|
CE1 |D<6> | 5.890|
CE1 |D<7> | 5.890|
CE1 |D<8> | 5.890|
CE1 |D<9> | 5.890|
CE1 |D<10> | 5.890|
CE1 |D<11> | 5.890|
CE1 |D<12> | 5.890|
CE1 |D<13> | 5.890|
CE1 |D<14> | 5.890|
CE1 |D<15> | 5.890|
CE1 |D<16> | 5.890|
CE1 |D<17> | 5.890|
CE1 |D<18> | 5.890|
CE1 |D<19> | 5.890|
CE1 |D<20> | 5.890|
CE1 |D<21> | 5.890|
CE1 |D<22> | 5.890|
CE1 |D<23> | 5.890|
CE1 |D<24> | 5.890|
CE1 |D<25> | 5.890|
CE1 |D<26> | 5.890|
CE1 |D<27> | 5.890|
CE1 |D<28> | 5.890|
CE1 |D<29> | 5.890|
CE1 |D<30> | 5.890|
CE1 |D<31> | 5.890|
OE |D<0> | 5.890|
OE |D<1> | 5.890|
OE |D<2> | 5.890|
OE |D<3> | 5.890|
OE |D<4> | 5.890|
OE |D<5> | 5.890|
OE |D<6> | 5.890|
OE |D<7> | 5.890|
OE |D<8> | 5.890|
OE |D<9> | 5.890|
OE |D<10> | 5.890|
OE |D<11> | 5.890|
OE |D<12> | 5.890|
OE |D<13> | 5.890|
OE |D<14> | 5.890|
OE |D<15> | 5.890|
OE |D<16> | 5.890|
OE |D<17> | 5.890|
OE |D<18> | 5.890|
OE |D<19> | 5.890|
OE |D<20> | 5.890|
OE |D<21> | 5.890|
OE |D<22> | 5.890|
OE |D<23> | 5.890|
OE |D<24> | 5.890|
OE |D<25> | 5.890|
OE |D<26> | 5.890|
OE |D<27> | 5.890|
OE |D<28> | 5.890|
OE |D<29> | 5.890|
OE |D<30> | 5.890|
OE |D<31> | 5.890|
---------------+---------------+---------+
Timing summary:
---------------
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
Constraints cover 105126 paths, 0 nets, and 23485 connections
Design statistics:
Minimum period: 9.807ns (Maximum frequency: 101.968MHz)
Maximum path delay from/to any node: 10.231ns
Analysis completed Tue Jul 28 15:40:52 2015
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 507 MB
ISE_14_7_results/x353-map.twx 0 → 100644
View file @ f5c2e000
This source diff could not be displayed because it is too large. You can view the blob instead.
ISE_14_7_results/x353-par.twr 0 → 100644
View file @ f5c2e000
--------------------------------------------------------------------------------
Release 14.7 Trace (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -o x353-par.twr -xml
x353-par.twx x353.ncd x353.pcf
Design file: x353.ncd
Physical constraint file: x353.pcf
Device,package,speed: xc3s1200e,ft256,-4 (PRODUCTION 1.27 2013-10-13)
Report level: summary report, limited to 0 items per constraint
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more
information, see the TSI report. Please consult the Xilinx Command Line
Tools User Guide for information on generating a TSI report.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
INFO:Timing:3390 - This architecture does not support a default System Jitter
value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
Uncertainty calculation.
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
'Phase Error' calculations, these terms will be zero in the Clock
Uncertainty calculation. Please make appropriate modification to
SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase
Error.
Number of Timing Constraints that were not applied: 4
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
* TS_i_iclockios_isclk0 = PERIOD TIMEGRP "i | SETUP | -1.165ns| 8.265ns| 7| 3419
_iclockios_isclk0" TS_CLK0 HIGH 50% | HOLD | 0.676ns| | 0| 0
----------------------------------------------------------------------------------------------------------
* TS_HUFFLATCHESI = MAXDELAY FROM TIMEGRP " | SETUP | -0.225ns| 4.573ns| 2| 385
TG_HUFFFFS" TO TIMEGRP "TG_HUFFLA | | | | |
TCHES" TS_CLK0 * 0.6125 | | | | |
----------------------------------------------------------------------------------------------------------
* TS_i_sensorpads_pclk2xi = PERIOD TIMEGRP | SETUP | -0.140ns| 5.340ns| 18| 1848
"i_sensorpads_pclk2xi" TS_CLK1 / 2 | HOLD | 0.756ns| | 0| 0
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_CLK1 = PERIOD TIMEGRP "CLK1" 10.4 ns H | SETUP | 0.051ns| 10.349ns| 0| 0
IGH 50% | HOLD | 0.674ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_HUFFLATCHES = MAXDELAY FROM TIMEGRP "T | SETUP | 0.121ns| 4.316ns| 0| 0
G_HUFFLATCHES" TO TIMEGRP "TG_HUF | | | | |
FFFS" TS_CLK0 * 0.625 | | | | |
----------------------------------------------------------------------------------------------------------
TS_AXIS_READ = MAXDELAY FROM TIMEGRP "CPU | MAXDELAY | 0.123ns| 16.877ns| 0| 0
_ADDRCE" TO TIMEGRP "CPU_DATA" 17 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_i_iclockios_isclk270 = PERIOD TIMEGRP | SETUP | 0.180ns| 6.860ns| 0| 0
"i_iclockios_isclk270" TS_CLK0 PHASE | HOLD | 1.325ns| | 0| 0
5.325 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_i_sensorpads_i_sensor_phase_dcm2x180 = | SETUP | 0.186ns| 5.014ns| 0| 0
PERIOD TIMEGRP "i_sensorpads_i_s | HOLD | 1.046ns| | 0| 0
ensor_phase_dcm2x180" TS_CLK1 / 2 PHASE 2 | | | | |
.6 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_OE_TO_DATA = MAXDELAY FROM TIMEGRP "OE | MAXDELAY | 0.186ns| 11.814ns| 0| 0
" TO TIMEGRP "CPU_DATA" 12 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_HUFFRAMS = MAXDELAY FROM TIMEGRP "TG_H | SETUP | 0.241ns| 5.793ns| 0| 0
UFFRAMS" TO TIMEGRP "TG_HUFFLATCHES" | | | | |
TS_CLK0 * 0.85 | | | | |
----------------------------------------------------------------------------------------------------------
TS_DOUBLECYCS3 = MAXDELAY FROM TIMEGRP "T | SETUP | 0.321ns| 13.879ns| 0| 0
G_SLOW_SRC3" TO TIMEGRP "TG_DOUBL | | | | |
EDEST3" TS_CLK0 * 2 | | | | |
----------------------------------------------------------------------------------------------------------
TS_WE = MAXDELAY FROM TIMEGRP "WE" TO TIM | MAXDELAY | 0.519ns| 10.981ns| 0| 0
EGRP "TNM_CWR" 11.5 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_DACK0 = MAXDELAY FROM TIMEGRP "DACK" T | MAXDELAY | 0.937ns| 16.063ns| 0| 0
O TIMEGRP "ALLPADS" 17 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_HUFFRAMSA = MAXDELAY FROM TIMEGRP "TG_ | SETUP | 1.945ns| 4.178ns| 0| 0
HUFFLATCHES" TO TIMEGRP "TG_HUFFRAMS" | | | | |
TS_CLK0 * 0.8625 | | | | |
----------------------------------------------------------------------------------------------------------
TS_i_sensorpads_i_sensor_phase_dcm2x = PE | MINLOWPULSE | 2.008ns| 3.192ns| 0| 0
RIOD TIMEGRP "i_sensorpads_i_sens | | | | |
or_phase_dcm2x" TS_CLK1 / 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_CLK0 = PERIOD TIMEGRP "CLK0" 7.1 ns HI | MINLOWPULSE | 2.300ns| 4.800ns| 0| 0
GH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_HIST_DOUBLECYC2 = MAXDELAY FROM TIMEGR | SETUP | 3.411ns| 6.989ns| 0| 0
P "TG_HIST_DOUBLE2_SRC" TO TIMEGRP | | | | |
"TG_HIST_DOUBLE2_DST" TS_CLK1 | | | | |
----------------------------------------------------------------------------------------------------------
TS_DOUBLECYC_IDATA = MAXDELAY FROM TIMEGR | SETUP | 5.493ns| 4.907ns| 0| 0
P "TNM_EN_IDATA" TO TIMEGRP "TNM_ | | | | |
EN_IDATA" TS_CLK1 | | | | |
----------------------------------------------------------------------------------------------------------
TS_DOUBLECYCS2 = MAXDELAY FROM TIMEGRP "T | SETUP | 5.987ns| 8.213ns| 0| 0
G_DOUBLECYCS2" TO TIMEGRP "TG_ALL | | | | |
_SYNC" TS_CLK0 * 2 | | | | |
----------------------------------------------------------------------------------------------------------
TS_WR_DATA = MAXDELAY FROM TIMEGRP "CPU_D | SETUP | 6.460ns| 2.540ns| 0| 0
ATA" TO TIMEGRP "TG_CWRDEST" 9 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_i_sensorpads_i_sensor_phase_pre_pre_en | MINPERIOD | 8.748ns| 1.652ns| 0| 0
_idata = PERIOD TIMEGRP "i_sensor | | | | |
pads_i_sensor_phase_pre_pre_en_idata" TS_ | | | | |
CLK1 PHASE 2.6 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_i_sensorpads_i_sensor_phase_pre_pre_en | MINPERIOD | 8.748ns| 1.652ns| 0| 0
_idata90 = PERIOD TIMEGRP "i_sens | | | | |
orpads_i_sensor_phase_pre_pre_en_idata90" | | | | |
TS_CLK1 PHASE 5.2 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
PATH "TS_PCLK_PCLK2X_path" TIG | SETUP | N/A| 4.840ns| N/A| 0
----------------------------------------------------------------------------------------------------------
PATH "TS_GCLK_IDATA_PCLK_path" TIG | SETUP | N/A| 14.944ns| N/A| 0
----------------------------------------------------------------------------------------------------------
PATH "TS_PCLK_GCLK_IDATA_path" TIG | SETUP | N/A| 5.796ns| N/A| 0
----------------------------------------------------------------------------------------------------------
Derived Constraint Report
Derived Constraints for TS_CLK0
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_CLK0 | 7.100ns| 4.800ns| 8.265ns| 0| 9| 0| 34422|
| TS_DOUBLECYCS2 | 14.200ns| 8.213ns| N/A| 0| 0| 457| 0|
| TS_DOUBLECYCS3 | 14.200ns| 13.879ns| N/A| 0| 0| 9051| 0|
| TS_HUFFRAMS | 6.035ns| 5.793ns| N/A| 0| 0| 36| 0|
| TS_HUFFLATCHES | 4.438ns| 4.316ns| N/A| 0| 0| 109| 0|
| TS_HUFFRAMSA | 6.124ns| 4.178ns| N/A| 0| 0| 21| 0|
| TS_HUFFLATCHESI | 4.349ns| 4.573ns| N/A| 2| 0| 105| 0|
| TS_i_iclockios_isclk0 | 7.100ns| 8.265ns| N/A| 7| 0| 24555| 0|
| TS_i_iclockios_isclk270 | 7.100ns| 6.860ns| N/A| 0| 0| 88| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_CLK1
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_CLK1 | 10.400ns| 10.349ns| 10.680ns| 0| 18| 66829| 1872|
| TS_DOUBLECYC_IDATA | 10.400ns| 4.907ns| N/A| 0| 0| 242| 0|
| TS_HIST_DOUBLECYC2 | 10.400ns| 6.989ns| N/A| 0| 0| 117| 0|
| TS_i_sensorpads_pclk2xi | 5.200ns| 5.340ns| N/A| 18| 0| 1393| 0|
| TS_i_sensorpads_i_sensor_phase| 10.400ns| 1.652ns| N/A| 0| 0| 0| 0|
| _pre_pre_en_idata | | | | | | | |
| TS_i_sensorpads_i_sensor_phase| 10.400ns| 1.652ns| N/A| 0| 0| 0| 0|
| _pre_pre_en_idata90 | | | | | | | |
| TS_i_sensorpads_i_sensor_phase| 5.200ns| 3.192ns| N/A| 0| 0| 0| 0|
| _dcm2x | | | | | | | |
| TS_i_sensorpads_i_sensor_phase| 5.200ns| 5.014ns| N/A| 0| 0| 120| 0|
| _dcm2x180 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
3 constraints not met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock BPF
------------+------------+------------+--------------------------------------+--------+
|Max Setup to|Max Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+--------------------------------------+--------+
DCLK | -2.547(R)| 17.029(R)|i_sensorpads/i_sensor_phase/gclk_idata| 2.600|
------------+------------+------------+--------------------------------------+--------+
Setup/Hold to clock CE
------------+------------+------------+------------------+--------+
|Max Setup to|Max Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
D<0> | -5.094(R)| 8.178(R)|i_sysinterface/cwr| 0.000|
D<1> | -5.144(R)| 8.237(R)|i_sysinterface/cwr| 0.000|
D<2> | -5.094(R)| 8.178(R)|i_sysinterface/cwr| 0.000|
D<3> | -5.092(R)| 8.176(R)|i_sysinterface/cwr| 0.000|
D<4> | -5.149(R)| 8.243(R)|i_sysinterface/cwr| 0.000|
D<5> | -5.144(R)| 8.237(R)|i_sysinterface/cwr| 0.000|
D<6> | -5.152(R)| 8.246(R)|i_sysinterface/cwr| 0.000|
D<7> | -5.149(R)| 8.243(R)|i_sysinterface/cwr| 0.000|
D<8> | -5.152(R)| 8.246(R)|i_sysinterface/cwr| 0.000|
D<9> | -5.092(R)| 8.176(R)|i_sysinterface/cwr| 0.000|
D<10> | -5.069(R)| 8.149(R)|i_sysinterface/cwr| 0.000|
D<11> | -5.131(R)| 8.222(R)|i_sysinterface/cwr| 0.000|
D<12> | -5.069(R)| 8.149(R)|i_sysinterface/cwr| 0.000|
D<13> | -5.082(R)| 8.164(R)|i_sysinterface/cwr| 0.000|
D<14> | -5.060(R)| 8.138(R)|i_sysinterface/cwr| 0.000|
D<15> | -5.126(R)| 8.215(R)|i_sysinterface/cwr| 0.000|
D<16> | -5.079(R)| 8.161(R)|i_sysinterface/cwr| 0.000|
D<17> | -5.081(R)| 8.162(R)|i_sysinterface/cwr| 0.000|
D<18> | -5.080(R)| 8.161(R)|i_sysinterface/cwr| 0.000|
D<19> | -5.131(R)| 8.222(R)|i_sysinterface/cwr| 0.000|
D<20> | -5.080(R)| 8.161(R)|i_sysinterface/cwr| 0.000|
D<21> | -5.150(R)| 8.244(R)|i_sysinterface/cwr| 0.000|
D<22> | -5.091(R)| 8.175(R)|i_sysinterface/cwr| 0.000|
D<23> | -5.069(R)| 8.148(R)|i_sysinterface/cwr| 0.000|
D<24> | -5.086(R)| 8.168(R)|i_sysinterface/cwr| 0.000|
D<25> | -5.059(R)| 8.136(R)|i_sysinterface/cwr| 0.000|
D<26> | -5.086(R)| 8.168(R)|i_sysinterface/cwr| 0.000|
D<27> | -5.088(R)| 8.171(R)|i_sysinterface/cwr| 0.000|
D<28> | -5.088(R)| 8.171(R)|i_sysinterface/cwr| 0.000|
D<29> | -5.081(R)| 8.162(R)|i_sysinterface/cwr| 0.000|
D<30> | -5.082(R)| 8.164(R)|i_sysinterface/cwr| 0.000|
D<31> | -5.082(R)| 8.164(R)|i_sysinterface/cwr| 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock CE1
------------+------------+------------+------------------+--------+
|Max Setup to|Max Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
D<0> | -5.472(R)| 8.651(R)|i_sysinterface/cwr| 0.000|
D<1> | -5.522(R)| 8.710(R)|i_sysinterface/cwr| 0.000|
D<2> | -5.472(R)| 8.651(R)|i_sysinterface/cwr| 0.000|
D<3> | -5.470(R)| 8.649(R)|i_sysinterface/cwr| 0.000|
D<4> | -5.527(R)| 8.716(R)|i_sysinterface/cwr| 0.000|
D<5> | -5.522(R)| 8.710(R)|i_sysinterface/cwr| 0.000|
D<6> | -5.530(R)| 8.719(R)|i_sysinterface/cwr| 0.000|
D<7> | -5.527(R)| 8.716(R)|i_sysinterface/cwr| 0.000|
D<8> | -5.530(R)| 8.719(R)|i_sysinterface/cwr| 0.000|
D<9> | -5.470(R)| 8.649(R)|i_sysinterface/cwr| 0.000|
D<10> | -5.447(R)| 8.622(R)|i_sysinterface/cwr| 0.000|
D<11> | -5.509(R)| 8.695(R)|i_sysinterface/cwr| 0.000|
D<12> | -5.447(R)| 8.622(R)|i_sysinterface/cwr| 0.000|
D<13> | -5.460(R)| 8.637(R)|i_sysinterface/cwr| 0.000|
D<14> | -5.438(R)| 8.611(R)|i_sysinterface/cwr| 0.000|
D<15> | -5.504(R)| 8.688(R)|i_sysinterface/cwr| 0.000|
D<16> | -5.457(R)| 8.634(R)|i_sysinterface/cwr| 0.000|
D<17> | -5.459(R)| 8.635(R)|i_sysinterface/cwr| 0.000|
D<18> | -5.458(R)| 8.634(R)|i_sysinterface/cwr| 0.000|
D<19> | -5.509(R)| 8.695(R)|i_sysinterface/cwr| 0.000|
D<20> | -5.458(R)| 8.634(R)|i_sysinterface/cwr| 0.000|
D<21> | -5.528(R)| 8.717(R)|i_sysinterface/cwr| 0.000|
D<22> | -5.469(R)| 8.648(R)|i_sysinterface/cwr| 0.000|
D<23> | -5.447(R)| 8.621(R)|i_sysinterface/cwr| 0.000|
D<24> | -5.464(R)| 8.641(R)|i_sysinterface/cwr| 0.000|
D<25> | -5.437(R)| 8.609(R)|i_sysinterface/cwr| 0.000|
D<26> | -5.464(R)| 8.641(R)|i_sysinterface/cwr| 0.000|
D<27> | -5.466(R)| 8.644(R)|i_sysinterface/cwr| 0.000|
D<28> | -5.466(R)| 8.644(R)|i_sysinterface/cwr| 0.000|
D<29> | -5.459(R)| 8.635(R)|i_sysinterface/cwr| 0.000|
D<30> | -5.460(R)| 8.637(R)|i_sysinterface/cwr| 0.000|
D<31> | -5.460(R)| 8.637(R)|i_sysinterface/cwr| 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock CLK1
------------+------------+------------+--------------------------------------+--------+
|Max Setup to|Max Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+--------------------------------------+--------+
DCLK | -7.313(R)| 12.036(R)|i_sensorpads/i_sensor_phase/gclk_idata| 2.600|
------------+------------+------------+--------------------------------------+--------+
Setup/Hold to clock OE
------------+------------+------------+------------------+--------+
|Max Setup to|Max Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
D<0> | -6.281(R)| 9.662(R)|i_sysinterface/cwr| 0.000|
D<1> | -6.331(R)| 9.721(R)|i_sysinterface/cwr| 0.000|
D<2> | -6.281(R)| 9.662(R)|i_sysinterface/cwr| 0.000|
D<3> | -6.279(R)| 9.660(R)|i_sysinterface/cwr| 0.000|
D<4> | -6.336(R)| 9.727(R)|i_sysinterface/cwr| 0.000|
D<5> | -6.331(R)| 9.721(R)|i_sysinterface/cwr| 0.000|
D<6> | -6.339(R)| 9.730(R)|i_sysinterface/cwr| 0.000|
D<7> | -6.336(R)| 9.727(R)|i_sysinterface/cwr| 0.000|
D<8> | -6.339(R)| 9.730(R)|i_sysinterface/cwr| 0.000|
D<9> | -6.279(R)| 9.660(R)|i_sysinterface/cwr| 0.000|
D<10> | -6.256(R)| 9.633(R)|i_sysinterface/cwr| 0.000|
D<11> | -6.318(R)| 9.706(R)|i_sysinterface/cwr| 0.000|
D<12> | -6.256(R)| 9.633(R)|i_sysinterface/cwr| 0.000|
D<13> | -6.269(R)| 9.648(R)|i_sysinterface/cwr| 0.000|
D<14> | -6.247(R)| 9.622(R)|i_sysinterface/cwr| 0.000|
D<15> | -6.313(R)| 9.699(R)|i_sysinterface/cwr| 0.000|
D<16> | -6.266(R)| 9.645(R)|i_sysinterface/cwr| 0.000|
D<17> | -6.268(R)| 9.646(R)|i_sysinterface/cwr| 0.000|
D<18> | -6.267(R)| 9.645(R)|i_sysinterface/cwr| 0.000|
D<19> | -6.318(R)| 9.706(R)|i_sysinterface/cwr| 0.000|
D<20> | -6.267(R)| 9.645(R)|i_sysinterface/cwr| 0.000|
D<21> | -6.337(R)| 9.728(R)|i_sysinterface/cwr| 0.000|
D<22> | -6.278(R)| 9.659(R)|i_sysinterface/cwr| 0.000|
D<23> | -6.256(R)| 9.632(R)|i_sysinterface/cwr| 0.000|
D<24> | -6.273(R)| 9.652(R)|i_sysinterface/cwr| 0.000|
D<25> | -6.246(R)| 9.620(R)|i_sysinterface/cwr| 0.000|
D<26> | -6.273(R)| 9.652(R)|i_sysinterface/cwr| 0.000|
D<27> | -6.275(R)| 9.655(R)|i_sysinterface/cwr| 0.000|
D<28> | -6.275(R)| 9.655(R)|i_sysinterface/cwr| 0.000|
D<29> | -6.268(R)| 9.646(R)|i_sysinterface/cwr| 0.000|
D<30> | -6.269(R)| 9.648(R)|i_sysinterface/cwr| 0.000|
D<31> | -6.269(R)| 9.648(R)|i_sysinterface/cwr| 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock WE
------------+------------+------------+------------------+--------+
|Max Setup to|Max Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
D<0> | -6.289(R)| 9.673(R)|i_sysinterface/cwr| 0.000|
D<1> | -6.339(R)| 9.732(R)|i_sysinterface/cwr| 0.000|
D<2> | -6.289(R)| 9.673(R)|i_sysinterface/cwr| 0.000|
D<3> | -6.287(R)| 9.671(R)|i_sysinterface/cwr| 0.000|
D<4> | -6.344(R)| 9.738(R)|i_sysinterface/cwr| 0.000|
D<5> | -6.339(R)| 9.732(R)|i_sysinterface/cwr| 0.000|
D<6> | -6.347(R)| 9.741(R)|i_sysinterface/cwr| 0.000|
D<7> | -6.344(R)| 9.738(R)|i_sysinterface/cwr| 0.000|
D<8> | -6.347(R)| 9.741(R)|i_sysinterface/cwr| 0.000|
D<9> | -6.287(R)| 9.671(R)|i_sysinterface/cwr| 0.000|
D<10> | -6.264(R)| 9.644(R)|i_sysinterface/cwr| 0.000|
D<11> | -6.326(R)| 9.717(R)|i_sysinterface/cwr| 0.000|
D<12> | -6.264(R)| 9.644(R)|i_sysinterface/cwr| 0.000|
D<13> | -6.277(R)| 9.659(R)|i_sysinterface/cwr| 0.000|
D<14> | -6.255(R)| 9.633(R)|i_sysinterface/cwr| 0.000|
D<15> | -6.321(R)| 9.710(R)|i_sysinterface/cwr| 0.000|
D<16> | -6.274(R)| 9.656(R)|i_sysinterface/cwr| 0.000|
D<17> | -6.276(R)| 9.657(R)|i_sysinterface/cwr| 0.000|
D<18> | -6.275(R)| 9.656(R)|i_sysinterface/cwr| 0.000|
D<19> | -6.326(R)| 9.717(R)|i_sysinterface/cwr| 0.000|
D<20> | -6.275(R)| 9.656(R)|i_sysinterface/cwr| 0.000|
D<21> | -6.345(R)| 9.739(R)|i_sysinterface/cwr| 0.000|
D<22> | -6.286(R)| 9.670(R)|i_sysinterface/cwr| 0.000|
D<23> | -6.264(R)| 9.643(R)|i_sysinterface/cwr| 0.000|
D<24> | -6.281(R)| 9.663(R)|i_sysinterface/cwr| 0.000|
D<25> | -6.254(R)| 9.631(R)|i_sysinterface/cwr| 0.000|
D<26> | -6.281(R)| 9.663(R)|i_sysinterface/cwr| 0.000|
D<27> | -6.283(R)| 9.666(R)|i_sysinterface/cwr| 0.000|
D<28> | -6.283(R)| 9.666(R)|i_sysinterface/cwr| 0.000|
D<29> | -6.276(R)| 9.657(R)|i_sysinterface/cwr| 0.000|
D<30> | -6.277(R)| 9.659(R)|i_sysinterface/cwr| 0.000|
D<31> | -6.277(R)| 9.659(R)|i_sysinterface/cwr| 0.000|
------------+------------+------------+------------------+--------+
Clock DACK0 to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
D<0> | 23.588(R)|i_dma_fifo0/swclk | 0.000|
D<1> | 23.964(R)|i_dma_fifo0/swclk | 0.000|
D<2> | 23.864(R)|i_dma_fifo0/swclk | 0.000|
D<3> | 23.348(R)|i_dma_fifo0/swclk | 0.000|
D<4> | 22.955(R)|i_dma_fifo0/swclk | 0.000|
D<5> | 24.133(R)|i_dma_fifo0/swclk | 0.000|
D<6> | 24.125(R)|i_dma_fifo0/swclk | 0.000|
D<7> | 23.306(R)|i_dma_fifo0/swclk | 0.000|
D<8> | 24.399(R)|i_dma_fifo0/swclk | 0.000|
D<9> | 23.795(R)|i_dma_fifo0/swclk | 0.000|
D<10> | 21.018(R)|i_dma_fifo0/swclk | 0.000|
D<11> | 21.367(R)|i_dma_fifo0/swclk | 0.000|
D<12> | 22.455(R)|i_dma_fifo0/swclk | 0.000|
D<13> | 23.302(R)|i_dma_fifo0/swclk | 0.000|
D<14> | 22.706(R)|i_dma_fifo0/swclk | 0.000|
D<15> | 22.701(R)|i_dma_fifo0/swclk | 0.000|
D<16> | 23.587(R)|i_dma_fifo0/swclk | 0.000|
D<17> | 24.580(R)|i_dma_fifo0/swclk | 0.000|
D<18> | 21.241(R)|i_dma_fifo0/swclk | 0.000|
D<19> | 24.455(R)|i_dma_fifo0/swclk | 0.000|
D<20> | 22.169(R)|i_dma_fifo0/swclk | 0.000|
D<21> | 23.006(R)|i_dma_fifo0/swclk | 0.000|
D<22> | 22.792(R)|i_dma_fifo0/swclk | 0.000|
D<23> | 24.362(R)|i_dma_fifo0/swclk | 0.000|
D<24> | 23.445(R)|i_dma_fifo0/swclk | 0.000|
D<25> | 22.458(R)|i_dma_fifo0/swclk | 0.000|
D<26> | 22.874(R)|i_dma_fifo0/swclk | 0.000|
D<27> | 22.189(R)|i_dma_fifo0/swclk | 0.000|
D<28> | 23.855(R)|i_dma_fifo0/swclk | 0.000|
D<29> | 23.230(R)|i_dma_fifo0/swclk | 0.000|
D<30> | 21.730(R)|i_dma_fifo0/swclk | 0.000|
D<31> | 24.066(R)|i_dma_fifo0/swclk | 0.000|
------------+------------+------------------+--------+
Clock DACK1 to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
D<0> | 25.545(R)|i_dma_fifo1/swclk | 0.000|
D<1> | 25.476(R)|i_dma_fifo1/swclk | 0.000|
D<2> | 24.983(R)|i_dma_fifo1/swclk | 0.000|
D<3> | 25.086(R)|i_dma_fifo1/swclk | 0.000|
D<4> | 25.140(R)|i_dma_fifo1/swclk | 0.000|
D<5> | 25.911(R)|i_dma_fifo1/swclk | 0.000|
D<6> | 26.363(R)|i_dma_fifo1/swclk | 0.000|
D<7> | 25.297(R)|i_dma_fifo1/swclk | 0.000|
D<8> | 26.492(R)|i_dma_fifo1/swclk | 0.000|
D<9> | 25.878(R)|i_dma_fifo1/swclk | 0.000|
D<10> | 23.247(R)|i_dma_fifo1/swclk | 0.000|
D<11> | 23.588(R)|i_dma_fifo1/swclk | 0.000|
D<12> | 23.635(R)|i_dma_fifo1/swclk | 0.000|
D<13> | 24.882(R)|i_dma_fifo1/swclk | 0.000|
D<14> | 23.881(R)|i_dma_fifo1/swclk | 0.000|
D<15> | 23.997(R)|i_dma_fifo1/swclk | 0.000|
D<16> | 24.547(R)|i_dma_fifo1/swclk | 0.000|
D<17> | 25.437(R)|i_dma_fifo1/swclk | 0.000|
D<18> | 22.291(R)|i_dma_fifo1/swclk | 0.000|
D<19> | 24.927(R)|i_dma_fifo1/swclk | 0.000|
D<20> | 23.447(R)|i_dma_fifo1/swclk | 0.000|
D<21> | 25.005(R)|i_dma_fifo1/swclk | 0.000|
D<22> | 23.888(R)|i_dma_fifo1/swclk | 0.000|
D<23> | 24.965(R)|i_dma_fifo1/swclk | 0.000|
D<24> | 24.720(R)|i_dma_fifo1/swclk | 0.000|
D<25> | 24.576(R)|i_dma_fifo1/swclk | 0.000|
D<26> | 24.670(R)|i_dma_fifo1/swclk | 0.000|
D<27> | 25.871(R)|i_dma_fifo1/swclk | 0.000|
D<28> | 26.084(R)|i_dma_fifo1/swclk | 0.000|
D<29> | 24.887(R)|i_dma_fifo1/swclk | 0.000|
D<30> | 23.237(R)|i_dma_fifo1/swclk | 0.000|
D<31> | 25.604(R)|i_dma_fifo1/swclk | 0.000|
------------+------------+------------------+--------+
Clock OE to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
D<0> | 23.794(R)|i_dma_fifo0/swclk | 0.000|
| 26.958(R)|i_dma_fifo1/swclk | 0.000|
D<1> | 24.170(R)|i_dma_fifo0/swclk | 0.000|
| 26.889(R)|i_dma_fifo1/swclk | 0.000|
D<2> | 24.070(R)|i_dma_fifo0/swclk | 0.000|
| 26.396(R)|i_dma_fifo1/swclk | 0.000|
D<3> | 23.554(R)|i_dma_fifo0/swclk | 0.000|
| 26.499(R)|i_dma_fifo1/swclk | 0.000|
D<4> | 23.161(R)|i_dma_fifo0/swclk | 0.000|
| 26.553(R)|i_dma_fifo1/swclk | 0.000|
D<5> | 24.339(R)|i_dma_fifo0/swclk | 0.000|
| 27.324(R)|i_dma_fifo1/swclk | 0.000|
D<6> | 24.331(R)|i_dma_fifo0/swclk | 0.000|
| 27.776(R)|i_dma_fifo1/swclk | 0.000|
D<7> | 23.512(R)|i_dma_fifo0/swclk | 0.000|
| 26.710(R)|i_dma_fifo1/swclk | 0.000|
D<8> | 24.605(R)|i_dma_fifo0/swclk | 0.000|
| 27.905(R)|i_dma_fifo1/swclk | 0.000|
D<9> | 24.001(R)|i_dma_fifo0/swclk | 0.000|
| 27.291(R)|i_dma_fifo1/swclk | 0.000|
D<10> | 21.224(R)|i_dma_fifo0/swclk | 0.000|
| 24.660(R)|i_dma_fifo1/swclk | 0.000|
D<11> | 21.573(R)|i_dma_fifo0/swclk | 0.000|
| 25.001(R)|i_dma_fifo1/swclk | 0.000|
D<12> | 22.661(R)|i_dma_fifo0/swclk | 0.000|
| 25.048(R)|i_dma_fifo1/swclk | 0.000|
D<13> | 23.508(R)|i_dma_fifo0/swclk | 0.000|
| 26.295(R)|i_dma_fifo1/swclk | 0.000|
D<14> | 22.912(R)|i_dma_fifo0/swclk | 0.000|
| 25.294(R)|i_dma_fifo1/swclk | 0.000|
D<15> | 22.907(R)|i_dma_fifo0/swclk | 0.000|
| 25.410(R)|i_dma_fifo1/swclk | 0.000|
D<16> | 23.793(R)|i_dma_fifo0/swclk | 0.000|
| 25.960(R)|i_dma_fifo1/swclk | 0.000|
D<17> | 24.786(R)|i_dma_fifo0/swclk | 0.000|
| 26.850(R)|i_dma_fifo1/swclk | 0.000|
D<18> | 21.447(R)|i_dma_fifo0/swclk | 0.000|
| 23.704(R)|i_dma_fifo1/swclk | 0.000|
D<19> | 24.661(R)|i_dma_fifo0/swclk | 0.000|
| 26.340(R)|i_dma_fifo1/swclk | 0.000|
D<20> | 22.375(R)|i_dma_fifo0/swclk | 0.000|
| 24.860(R)|i_dma_fifo1/swclk | 0.000|
D<21> | 23.212(R)|i_dma_fifo0/swclk | 0.000|
| 26.418(R)|i_dma_fifo1/swclk | 0.000|
D<22> | 22.998(R)|i_dma_fifo0/swclk | 0.000|
| 25.301(R)|i_dma_fifo1/swclk | 0.000|
D<23> | 24.568(R)|i_dma_fifo0/swclk | 0.000|
| 26.378(R)|i_dma_fifo1/swclk | 0.000|
D<24> | 23.651(R)|i_dma_fifo0/swclk | 0.000|
| 26.133(R)|i_dma_fifo1/swclk | 0.000|
D<25> | 22.664(R)|i_dma_fifo0/swclk | 0.000|
| 25.989(R)|i_dma_fifo1/swclk | 0.000|
D<26> | 23.080(R)|i_dma_fifo0/swclk | 0.000|
| 26.083(R)|i_dma_fifo1/swclk | 0.000|
D<27> | 22.395(R)|i_dma_fifo0/swclk | 0.000|
| 27.284(R)|i_dma_fifo1/swclk | 0.000|
D<28> | 24.061(R)|i_dma_fifo0/swclk | 0.000|
| 27.497(R)|i_dma_fifo1/swclk | 0.000|
D<29> | 23.436(R)|i_dma_fifo0/swclk | 0.000|
| 26.300(R)|i_dma_fifo1/swclk | 0.000|
D<30> | 21.936(R)|i_dma_fifo0/swclk | 0.000|
| 24.650(R)|i_dma_fifo1/swclk | 0.000|
D<31> | 24.272(R)|i_dma_fifo0/swclk | 0.000|
| 27.017(R)|i_dma_fifo1/swclk | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock BPF
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
BPF | 14.944| 2.398| | |
CLK1 | 14.944| 2.398| | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock CE
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
WE | | | -5.147| -5.147|
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock CE1
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
WE | | | -5.525| -5.525|
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock CLK0
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK0 | 6.912| 4.178| 4.316| 13.879|
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock CLK1
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
BPF | 14.944| 2.398| | |
CLK1 | 14.944| 2.398| | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock OE
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
WE | | | -6.334| -6.334|
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock WE
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
WE | | | -6.342| -6.342|
---------------+---------+---------+---------+---------+
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
A<0> |D<0> | 15.995|
A<0> |D<1> | 16.877|
A<0> |D<2> | 15.870|
A<0> |D<3> | 15.102|
A<0> |D<4> | 16.696|
A<0> |D<5> | 15.628|
A<0> |D<6> | 15.547|
A<0> |D<7> | 16.835|
A<0> |D<8> | 15.909|
A<0> |D<9> | 16.154|
A<0> |D<10> | 14.572|
A<0> |D<11> | 14.137|
A<0> |D<12> | 13.567|
A<0> |D<13> | 15.422|
A<0> |D<14> | 14.365|
A<0> |D<15> | 14.249|
A<0> |D<16> | 15.589|
A<0> |D<17> | 16.227|
A<0> |D<18> | 14.589|
A<0> |D<19> | 16.759|
A<0> |D<20> | 14.694|
A<0> |D<21> | 15.608|
A<0> |D<22> | 14.874|
A<0> |D<23> | 16.591|
A<0> |D<24> | 15.014|
A<0> |D<25> | 13.859|
A<0> |D<26> | 16.095|
A<0> |D<27> | 15.678|
A<0> |D<28> | 16.060|
A<0> |D<29> | 15.661|
A<0> |D<30> | 14.945|
A<0> |D<31> | 15.190|
A<1> |D<0> | 15.793|
A<1> |D<1> | 16.563|
A<1> |D<2> | 15.897|
A<1> |D<3> | 14.696|
A<1> |D<4> | 16.290|
A<1> |D<5> | 15.641|
A<1> |D<6> | 16.111|
A<1> |D<7> | 16.429|
A<1> |D<8> | 16.151|
A<1> |D<9> | 15.748|
A<1> |D<10> | 14.472|
A<1> |D<11> | 15.400|
A<1> |D<12> | 14.336|
A<1> |D<13> | 15.356|
A<1> |D<14> | 14.167|
A<1> |D<15> | 13.653|
A<1> |D<16> | 15.717|
A<1> |D<17> | 16.273|
A<1> |D<18> | 14.347|
A<1> |D<19> | 16.470|
A<1> |D<20> | 14.480|
A<1> |D<21> | 16.385|
A<1> |D<22> | 15.528|
A<1> |D<23> | 16.682|
A<1> |D<24> | 15.620|
A<1> |D<25> | 14.468|
A<1> |D<26> | 16.701|
A<1> |D<27> | 15.599|
A<1> |D<28> | 16.047|
A<1> |D<29> | 15.418|
A<1> |D<30> | 14.845|
A<1> |D<31> | 15.078|
A<2> |D<0> | 15.803|
A<2> |D<1> | 16.052|
A<2> |D<2> | 15.960|
A<2> |D<3> | 14.706|
A<2> |D<4> | 16.300|
A<2> |D<5> | 15.612|
A<2> |D<6> | 15.726|
A<2> |D<7> | 16.439|
A<2> |D<8> | 15.827|
A<2> |D<9> | 15.758|
A<2> |D<10> | 14.482|
A<2> |D<11> | 14.709|
A<2> |D<12> | 13.984|
A<2> |D<13> | 15.332|
A<2> |D<14> | 14.336|
A<2> |D<15> | 14.561|
A<2> |D<16> | 15.614|
A<2> |D<17> | 15.365|
A<2> |D<18> | 14.173|
A<2> |D<19> | 16.441|
A<2> |D<20> | 14.708|
A<2> |D<21> | 16.356|
A<2> |D<22> | 16.696|
A<2> |D<23> | 16.653|
A<2> |D<24> | 15.649|
A<2> |D<25> | 15.681|
A<2> |D<26> | 16.730|
A<2> |D<27> | 16.081|
A<2> |D<28> | 16.076|
A<2> |D<29> | 14.949|
A<2> |D<30> | 14.918|
A<2> |D<31> | 15.595|
A<3> |D<0> | 16.800|
A<3> |D<1> | 16.316|
A<3> |D<2> | 15.345|
A<3> |D<3> | 14.857|
A<3> |D<4> | 15.578|
A<3> |D<5> | 15.013|
A<3> |D<6> | 15.827|
A<3> |D<7> | 15.499|
A<3> |D<8> | 16.056|
A<3> |D<9> | 14.766|
A<3> |D<10> | 14.370|
A<3> |D<11> | 14.280|
A<3> |D<12> | 13.250|
A<3> |D<13> | 14.788|
A<3> |D<14> | 14.285|
A<3> |D<15> | 14.124|
A<3> |D<16> | 15.013|
A<3> |D<17> | 14.894|
A<3> |D<18> | 14.074|
A<3> |D<19> | 16.133|
A<3> |D<20> | 14.657|
A<3> |D<21> | 15.353|
A<3> |D<22> | 15.365|
A<3> |D<23> | 15.122|
A<3> |D<24> | 15.598|
A<3> |D<25> | 14.357|
A<3> |D<26> | 16.679|
A<3> |D<27> | 16.110|
A<3> |D<28> | 16.025|
A<3> |D<29> | 15.485|
A<3> |D<30> | 14.867|
A<3> |D<31> | 15.056|
A<4> |D<0> | 15.187|
A<4> |D<1> | 14.625|
A<4> |D<2> | 14.614|
A<4> |D<3> | 14.217|
A<4> |D<4> | 15.154|
A<4> |D<5> | 14.861|
A<4> |D<6> | 15.349|
A<4> |D<7> | 14.321|
A<4> |D<8> | 15.688|
A<4> |D<9> | 14.108|
A<4> |D<10> | 12.449|
A<4> |D<11> | 13.468|
A<4> |D<12> | 13.689|
A<4> |D<13> | 14.289|
A<4> |D<14> | 14.282|
A<4> |D<15> | 14.420|
A<4> |D<16> | 15.217|
A<4> |D<17> | 15.256|
A<4> |D<18> | 15.060|
A<4> |D<19> | 16.437|
A<4> |D<20> | 14.431|
A<4> |D<21> | 15.127|
A<4> |D<22> | 15.129|
A<4> |D<23> | 15.079|
A<4> |D<24> | 15.458|
A<4> |D<25> | 14.217|
A<4> |D<26> | 16.539|
A<4> |D<27> | 15.777|
A<4> |D<28> | 15.885|
A<4> |D<29> | 14.804|
A<4> |D<30> | 14.460|
A<4> |D<31> | 14.916|
A<5> |D<0> | 15.925|
A<5> |D<1> | 15.441|
A<5> |D<2> | 14.633|
A<5> |D<3> | 14.221|
A<5> |D<4> | 15.158|
A<5> |D<5> | 14.865|
A<5> |D<6> | 14.991|
A<5> |D<7> | 14.325|
A<5> |D<8> | 15.707|
A<5> |D<9> | 14.127|
A<5> |D<10> | 11.751|
A<5> |D<11> | 13.175|
A<5> |D<12> | 13.708|
A<5> |D<13> | 14.225|
A<5> |D<14> | 14.301|
A<5> |D<15> | 14.439|
A<5> |D<16> | 14.800|
A<5> |D<17> | 15.275|
A<5> |D<18> | 14.012|
A<5> |D<19> | 15.389|
A<5> |D<20> | 13.378|
A<5> |D<21> | 13.954|
A<5> |D<22> | 13.671|
A<5> |D<23> | 15.098|
A<5> |D<24> | 14.007|
A<5> |D<25> | 13.096|
A<5> |D<26> | 14.500|
A<5> |D<27> | 14.848|
A<5> |D<28> | 14.185|
A<5> |D<29> | 13.875|
A<5> |D<30> | 12.652|
A<5> |D<31> | 13.738|
A<6> |D<0> | 10.054|
A<6> |D<1> | 11.518|
A<6> |D<2> | 10.446|
A<6> |D<3> | 9.759|
A<6> |D<4> | 11.149|
A<6> |D<5> | 8.744|
A<6> |D<6> | 9.957|
A<6> |D<7> | 11.886|
A<6> |D<8> | 11.097|
A<6> |D<9> | 10.960|
A<6> |D<10> | 11.703|
A<6> |D<11> | 11.653|
A<6> |D<12> | 10.897|
A<6> |D<13> | 11.759|
A<6> |D<14> | 9.612|
A<6> |D<15> | 10.524|
A<6> |D<16> | 11.819|
A<6> |D<17> | 10.498|
A<6> |D<18> | 9.861|
A<6> |D<19> | 11.901|
A<6> |D<20> | 10.507|
A<6> |D<21> | 13.000|
A<6> |D<22> | 9.304|
A<6> |D<23> | 11.279|
A<6> |D<24> | 12.782|
A<6> |D<25> | 12.193|
A<6> |D<26> | 12.636|
A<6> |D<27> | 12.880|
A<6> |D<28> | 12.093|
A<6> |D<29> | 12.131|
A<6> |D<30> | 11.621|
A<6> |D<31> | 13.979|
CE |D<0> | 9.332|
CE |D<1> | 9.333|
CE |D<2> | 9.346|
CE |D<3> | 9.239|
CE |D<4> | 9.068|
CE |D<5> | 9.280|
CE |D<6> | 9.067|
CE |D<7> | 9.335|
CE |D<8> | 9.044|
CE |D<9> | 9.352|
CE |D<10> | 8.364|
CE |D<11> | 7.266|
CE |D<12> | 7.831|
CE |D<13> | 10.306|
CE |D<14> | 8.362|
CE |D<15> | 7.723|
CE |D<16> | 8.659|
CE |D<17> | 9.043|
CE |D<18> | 10.031|
CE |D<19> | 9.394|
CE |D<20> | 10.057|
CE |D<21> | 9.199|
CE |D<22> | 9.070|
CE |D<23> | 9.080|
CE |D<24> | 8.795|
CE |D<25> | 10.065|
CE |D<26> | 8.908|
CE |D<27> | 9.603|
CE |D<28> | 8.991|
CE |D<29> | 9.404|
CE |D<30> | 8.656|
CE |D<31> | 8.460|
CE1 |D<0> | 9.842|
CE1 |D<1> | 9.843|
CE1 |D<2> | 9.856|
CE1 |D<3> | 9.749|
CE1 |D<4> | 9.578|
CE1 |D<5> | 9.790|
CE1 |D<6> | 9.577|
CE1 |D<7> | 9.845|
CE1 |D<8> | 9.554|
CE1 |D<9> | 9.862|
CE1 |D<10> | 8.874|
CE1 |D<11> | 7.776|
CE1 |D<12> | 8.341|
CE1 |D<13> | 10.816|
CE1 |D<14> | 8.872|
CE1 |D<15> | 8.233|
CE1 |D<16> | 9.169|
CE1 |D<17> | 9.553|
CE1 |D<18> | 10.541|
CE1 |D<19> | 9.904|
CE1 |D<20> | 10.567|
CE1 |D<21> | 9.709|
CE1 |D<22> | 9.580|
CE1 |D<23> | 9.590|
CE1 |D<24> | 9.305|
CE1 |D<25> | 10.575|
CE1 |D<26> | 9.418|
CE1 |D<27> | 10.113|
CE1 |D<28> | 9.501|
CE1 |D<29> | 9.914|
CE1 |D<30> | 9.166|
CE1 |D<31> | 8.970|
OE |D<0> | 10.840|
OE |D<1> | 10.841|
OE |D<2> | 10.854|
OE |D<3> | 10.747|
OE |D<4> | 10.576|
OE |D<5> | 10.788|
OE |D<6> | 10.575|
OE |D<7> | 10.843|
OE |D<8> | 10.552|
OE |D<9> | 10.860|
OE |D<10> | 9.872|
OE |D<11> | 8.774|
OE |D<12> | 9.339|
OE |D<13> | 11.814|
OE |D<14> | 9.870|
OE |D<15> | 9.231|
OE |D<16> | 10.167|
OE |D<17> | 10.551|
OE |D<18> | 11.539|
OE |D<19> | 10.902|
OE |D<20> | 11.565|
OE |D<21> | 10.707|
OE |D<22> | 10.578|
OE |D<23> | 10.588|
OE |D<24> | 10.303|
OE |D<25> | 11.573|
OE |D<26> | 10.416|
OE |D<27> | 11.111|
OE |D<28> | 10.499|
OE |D<29> | 10.912|
OE |D<30> | 10.164|
OE |D<31> | 9.968|
---------------+---------------+---------+
Timing summary:
---------------
Timing errors: 27 Score: 5652 (Setup/Max: 5652, Hold: 0)
Constraints cover 105126 paths, 0 nets, and 23485 connections
Design statistics:
Minimum period: 13.879ns (Maximum frequency: 72.051MHz)
Maximum path delay from/to any node: 16.877ns
Analysis completed Tue Jul 28 15:43:46 2015
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 518 MB
ISE_14_7_results/x353-par.twx 0 → 100644
View file @ f5c2e000
This source diff could not be displayed because it is too large. You can view the blob instead.
ISE_14_7_results/x353.bgn 0 → 100644
View file @ f5c2e000
Release 14.7 - Bitgen P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '3s1200e.nph' in environment
/opt/Xilinx/14.7/ISE_DS/ISE/.
"x353" is an NCD, version 3.2, device xc3s1200e, package ft256, speed -4
Opened constraints file x353.pcf.
Tue Jul 28 15:43:52 2015
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/bitgen -w x353.ncd x353.bit x353.pcf
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name | Current Setting |
+----------------------+----------------------+
| Compress | (Not Specified)* |
+----------------------+----------------------+
| Readback | (Not Specified)* |
+----------------------+----------------------+
| CRC | Enable* |
+----------------------+----------------------+
| DebugBitstream | No* |
+----------------------+----------------------+
| ConfigRate | 1* |
+----------------------+----------------------+
| StartupClk | Cclk* |
+----------------------+----------------------+
| DCMShutdown | Disable* |
+----------------------+----------------------+
| DonePin | Pullup* |
+----------------------+----------------------+
| ProgPin | Pullup* |
+----------------------+----------------------+
| TckPin | Pullup* |
+----------------------+----------------------+
| TdiPin | Pullup* |
+----------------------+----------------------+
| TdoPin | Pullup* |
+----------------------+----------------------+
| TmsPin | Pullup* |
+----------------------+----------------------+
| UnusedPin | Pulldown* |
+----------------------+----------------------+
| GWE_cycle | 6* |
+----------------------+----------------------+
| GTS_cycle | 5* |
+----------------------+----------------------+
| LCK_cycle | NoWait* |
+----------------------+----------------------+
| DONE_cycle | 4* |
+----------------------+----------------------+
| Persist | No* |
+----------------------+----------------------+
| DriveDone | No* |
+----------------------+----------------------+
| DonePipe | No* |
+----------------------+----------------------+
| Security | None* |
+----------------------+----------------------+
| UserID | 0xFFFFFFFF* |
+----------------------+----------------------+
| MultiBootMode | No* |
+----------------------+----------------------+
| ActivateGclk | No* |
+----------------------+----------------------+
| ActiveReconfig | No* |
+----------------------+----------------------+
| PartialMask0 | (Not Specified)* |
+----------------------+----------------------+
| PartialMask1 | (Not Specified)* |
+----------------------+----------------------+
| PartialMask2 | (Not Specified)* |
+----------------------+----------------------+
| PartialGclk | (Not Specified)* |
+----------------------+----------------------+
| PartialLeft | (Not Specified)* |
+----------------------+----------------------+
| PartialRight | (Not Specified)* |
+----------------------+----------------------+
| TimeStamp | Default* |
+----------------------+----------------------+
| IEEE1532 | No* |
+----------------------+----------------------+
| Binary | No* |
+----------------------+----------------------+
* Default setting.
** The specified setting matches the default setting.
There were 0 CONFIG constraint(s) processed from x353.pcf.
Running DRC.
WARNING:PhysDesignRules:372 - Gated clock. Clock net i_sensorpads/fifo_clkin is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cb_xt_pol_virt_trig_MUX_728_o is sourced by a combinatorial pin. This is not
good design practice. Use the CE pin to control the loading of data into the
flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net compressor_eot is sourced
by a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:1063 - Issue with pin connections and/or configuration
on block:<i_compressor/i_color_proc/i_y_buff.A>:<RAMB16_RAMB16A>. The block
is configured to use an input parity pins. There is a dangling output parity
pin.
WARNING:PhysDesignRules:1067 - Issue with pin connections and/or configuration
on block:<i_sensorpix/i_cstableh.B>:<RAMB16_RAMB16B>. The block is
configured to use an input parity pin. There is a dangling output parity pin.
WARNING:PhysDesignRules:1067 - Issue with pin connections and/or configuration
on block:<i_sensorpix/i_cstablel.B>:<RAMB16_RAMB16B>. The block is
configured to use an input parity pin. There is a dangling output parity pin.
WARNING:PhysDesignRules:1063 - Issue with pin connections and/or configuration
on block:<i_compressor/i_color_proc/i_CrCb_buff.A>:<RAMB16_RAMB16A>. The
block is configured to use an input parity pins. There is a dangling output
parity pin.
DRC detected 0 errors and 7 warnings. Please see the previously displayed
individual error or warning messages for more details.
Creating bit map...
Saving bit stream in "x353.bit".
Bitstream generation is complete.
ISE_14_7_results/x353.bld 0 → 100644
View file @ f5c2e000
Release 14.7 ngdbuild P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Command Line: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -p
xc3s1200eft256-4 x353.ngc x353.ngd
Reading NGO file "/home/xilinx/vdt_ise/x353/x353.ngc" ...
Gathering constraint information from source properties...
Done.
Resolving constraint associations...
Checking Constraint Associations...
WARNING:ConstraintSystem - For the pattern match
'LATCHES('i_compressor/i_huffman/i_stuffer_was_rdy_early')', no signals were
found to match the pattern 'i_compressor/i_huffman/i_stuffer_was_rdy_early'.
This patern match is used in the following groups and/or specifications:
<TIMEGRP TG_STUFFER_WAS_READY_EARLY =
LATCHES("i_compressor/i_huffman/i_stuffer_was_rdy_early");>
Since no appropriate elements were found for the group
'LATCHES('i_compressor/i_huffman/i_stuffer_was_rdy_early')', this group has
been removed from the design. Note that patterns for TIMEGRP will match only
signals driven by the given type of element, not instance names. To create a
group using an instance name pattern, use the INST keyword to attach a TNM.
WARNING:ConstraintSystem - TNM : TNM_PCLK was distributed to a DCM but new TNM
constraints were not derived. This TNM is used in the following user groups
or specifications:
<TIMESPEC TS_PCLK_GCLK_IDATA = FROM "TNM_PCLK" TO "TNM_GCLK_IDATA" TIG;>
<TIMESPEC TS_GCLK_IDATA_PCLK = FROM "TNM_GCLK_IDATA" TO "TNM_PCLK" TIG;>
<TIMESPEC TS_PCLK_PCLK2X = FROM "TNM_PCLK" TO "TNM_PCLK2X" TIG;>
WARNING:ConstraintSystem:56 - Constraint <TIMESPEC
TS_i_sensorpads_i_sensor_phase_dcm_out0 = PERIOD
"i_sensorpads_i_sensor_phase_dcm_out0" TS_CLK1 HIGH 50%>: Unable to find an
active 'TNM' constraint named 'i_sensorpads_i_sensor_phase_dcm_out0'.
INFO:ConstraintSystem:178 - TNM 'CLK0', used in period specification 'TS_CLK0',
was traced into DCM_SP instance i_iclockios/i_dcm1. The following new TNM
groups and period specifications were generated at the DCM_SP output(s):
CLK0: <TIMESPEC TS_i_iclockios_isclk0 = PERIOD "i_iclockios_isclk0" TS_CLK0
HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'CLK0', used in period specification 'TS_CLK0',
was traced into DCM_SP instance i_iclockios/i_dcm1. The following new TNM
groups and period specifications were generated at the DCM_SP output(s):
CLK270: <TIMESPEC TS_i_iclockios_isclk270 = PERIOD "i_iclockios_isclk270"
TS_CLK0 PHASE 5325 ps HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'CLK1', used in period specification 'TS_CLK1',
was traced into DCM_SP instance i_sensorpads/i_dcm4. The following new TNM
groups and period specifications were generated at the DCM_SP output(s):
CLK2X: <TIMESPEC TS_i_sensorpads_pclk2xi = PERIOD "i_sensorpads_pclk2xi"
TS_CLK1 / 2 HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'CLK1', used in period specification 'TS_CLK1',
was traced into DCM_SP instance i_sensorpads/i_sensor_phase/i_dcm_sensor. The
following new TNM groups and period specifications were generated at the
DCM_SP output(s):
CLK90: <TIMESPEC TS_i_sensorpads_i_sensor_phase_pre_pre_en_idata = PERIOD
"i_sensorpads_i_sensor_phase_pre_pre_en_idata" TS_CLK1 PHASE 2600 ps HIGH
50%>
INFO:ConstraintSystem:178 - TNM 'CLK1', used in period specification 'TS_CLK1',
was traced into DCM_SP instance i_sensorpads/i_sensor_phase/i_dcm_sensor. The
following new TNM groups and period specifications were generated at the
DCM_SP output(s):
CLK180: <TIMESPEC TS_i_sensorpads_i_sensor_phase_pre_pre_en_idata90 = PERIOD
"i_sensorpads_i_sensor_phase_pre_pre_en_idata90" TS_CLK1 PHASE 5200 ps HIGH
50%>
INFO:ConstraintSystem:178 - TNM 'CLK1', used in period specification 'TS_CLK1',
was traced into DCM_SP instance i_sensorpads/i_sensor_phase/i_dcm_sensor. The
following new TNM groups and period specifications were generated at the
DCM_SP output(s):
CLK2X: <TIMESPEC TS_i_sensorpads_i_sensor_phase_dcm2x = PERIOD
"i_sensorpads_i_sensor_phase_dcm2x" TS_CLK1 / 2 HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'CLK1', used in period specification 'TS_CLK1',
was traced into DCM_SP instance i_sensorpads/i_sensor_phase/i_dcm_sensor. The
following new TNM groups and period specifications were generated at the
DCM_SP output(s):
CLK2X180: <TIMESPEC TS_i_sensorpads_i_sensor_phase_dcm2x180 = PERIOD
"i_sensorpads_i_sensor_phase_dcm2x180" TS_CLK1 / 2 PHASE 2600 ps HIGH 50%>
Done...
WARNING:NgdBuild:1212 - User specified non-default attribute value (8.333330)
was detected for the CLKIN_PERIOD attribute on DCM "i_iclockios/i_dcm1".
This does not match the PERIOD constraint value (7100 ps.). The uncertainty
calculation will use the non-default attribute value. This could result in
incorrect uncertainty calculated for DCM output clocks.
INFO:NgdBuild:1222 - Setting CLKIN_PERIOD attribute associated with DCM instance
i_sensorpads/i_dcm4 to 10.400000 ns based on the period specification
(<TIMESPEC TS_CLK1 = PERIOD "CLK1" 10400.000000 pS HIGH 50.000000 %;>).
INFO:NgdBuild:1222 - Setting CLKIN_PERIOD attribute associated with DCM instance
i_sensorpads/i_sensor_phase/i_dcm_sensor to 10.400000 ns based on the period
specification (<TIMESPEC TS_CLK1 = PERIOD "CLK1" 10400.000000 pS HIGH
50.000000 %;>).
WARNING:NgdBuild:1212 - User specified non-default attribute value (8.333330)
was detected for the CLKIN_PERIOD attribute on DCM "i_dcm333/i_dcm2". This
does not match the PERIOD constraint value (7100 ps.). The uncertainty
calculation will use the non-default attribute value. This could result in
incorrect uncertainty calculated for DCM output clocks.
Checking expanded design ...
WARNING:NgdBuild:446 - LATCH primitive 'i_sysinterface/i_a12/i_q/i_qr' has
unconnected output pin
WARNING:NgdBuild:446 - LATCH primitive 'i_sysinterface/i_a11/i_q/i_qr' has
unconnected output pin
WARNING:NgdBuild:446 - LATCH primitive 'i_sysinterface/i_a10/i_q/i_qr' has
unconnected output pin
WARNING:NgdBuild:446 - LATCH primitive 'i_sysinterface/i_a9/i_q/i_qr' has
unconnected output pin
WARNING:NgdBuild:446 - LATCH primitive 'i_sysinterface/i_a8/i_q/i_qr' has
unconnected output pin
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 10
Total memory usage is 465840 kilobytes
Writing NGD file "x353.ngd" ...
Total REAL time to NGDBUILD completion: 8 sec
Total CPU time to NGDBUILD completion: 8 sec
Writing NGDBUILD log file "x353.bld"...
ISE_14_7_results/x353.drc 0 → 100644
View file @ f5c2e000
Release 14.7 Drc P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Tue Jul 28 15:43:52 2015
drc -z x353.ncd x353.pcf
WARNING:PhysDesignRules:372 - Gated clock. Clock net i_sensorpads/fifo_clkin is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cb_xt_pol_virt_trig_MUX_728_o is sourced by a combinatorial pin. This is not
good design practice. Use the CE pin to control the loading of data into the
flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net compressor_eot is sourced
by a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:1063 - Issue with pin connections and/or configuration
on block:<i_compressor/i_color_proc/i_y_buff.A>:<RAMB16_RAMB16A>. The block
is configured to use an input parity pins. There is a dangling output parity
pin.
WARNING:PhysDesignRules:1067 - Issue with pin connections and/or configuration
on block:<i_sensorpix/i_cstableh.B>:<RAMB16_RAMB16B>. The block is
configured to use an input parity pin. There is a dangling output parity pin.
WARNING:PhysDesignRules:1067 - Issue with pin connections and/or configuration
on block:<i_sensorpix/i_cstablel.B>:<RAMB16_RAMB16B>. The block is
configured to use an input parity pin. There is a dangling output parity pin.
WARNING:PhysDesignRules:1063 - Issue with pin connections and/or configuration
on block:<i_compressor/i_color_proc/i_CrCb_buff.A>:<RAMB16_RAMB16A>. The
block is configured to use an input parity pins. There is a dangling output
parity pin.
DRC detected 0 errors and 7 warnings. Please see the previously displayed
individual error or warning messages for more details.
ISE_14_7_results/x353.mrp 0 → 100644
View file @ f5c2e000
Release 14.7 Map P.20131013 (lin64)
Xilinx Mapping Report File for Design 'x353'
Design Information
------------------
Command Line : map -o x353.ncd -cm speed -ir off -ol high -p xc3s1200eft256-4
-register_duplication on -w x353.ngd x353.pcf
Target Device : xc3s1200e
Target Package : ft256
Target Speed : -4
Mapper Version : spartan3e -- $Revision: 1.55 $
Mapped Date : Tue Jul 28 15:40:31 2015
Design Summary
--------------
Number of errors: 0
Number of warnings: 20
Logic Utilization:
Total Number Slice Registers: 7,573 out of 17,344 43%
Number used as Flip Flops: 7,515
Number used as Latches: 58
Number of 4 input LUTs: 8,802 out of 17,344 50%
Logic Distribution:
Number of occupied Slices: 6,969 out of 8,672 80%
Number of Slices containing only related logic: 6,969 out of 6,969 100%
Number of Slices containing unrelated logic: 0 out of 6,969 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 9,293 out of 17,344 53%
Number used as logic: 7,833
Number used as a route-thru: 491
Number used as 16x1 RAMs: 13
Number used for Dual Port RAMs: 676
(Two LUTs used per Dual Port RAM)
Number used as Shift registers: 280
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
Number of bonded IOBs: 142 out of 190 74%
IOB Flip Flops: 66
IOB Latches: 9
IOB Master Pads: 2
IOB Slave Pads: 2
Number of IDDR2s used: 18
Number of DDR_ALIGNMENT = NONE 18
Number of DDR_ALIGNMENT = C0 0
Number of DDR_ALIGNMENT = C1 0
Number of ODDR2s used: 20
Number of DDR_ALIGNMENT = NONE 20
Number of DDR_ALIGNMENT = C0 0
Number of DDR_ALIGNMENT = C1 0
Number of RAMB16s: 22 out of 28 78%
Number of BUFGMUXs: 9 out of 24 37%
Number of DCMs: 4 out of 8 50%
Number of MULT18X18SIOs: 19 out of 28 67%
Average Fanout of Non-Clock Nets: 2.90
Peak Memory Usage: 749 MB
Total REAL time to MAP completion: 9 secs
Total CPU time to MAP completion: 9 secs
NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
WARNING:Map:122 - The command line option -ol can only be used when running in
timing mode (-timing option). The option will be ignored.
WARNING:Map:125 - The command line option -register_duplication can only be used
when running in timing mode (-timing option). The option will be ignored.
WARNING:MapLib:701 - Signal CLK2 connected to top level port CLK2 has been
removed.
WARNING:MapLib:701 - Signal CLK4 connected to top level port CLK4 has been
removed.
WARNING:MapLib:701 - Signal A<12> connected to top level port A<12> has been
removed.
WARNING:MapLib:701 - Signal A<11> connected to top level port A<11> has been
removed.
WARNING:MapLib:701 - Signal A<10> connected to top level port A<10> has been
removed.
WARNING:MapLib:701 - Signal A<9> connected to top level port A<9> has been
removed.
WARNING:MapLib:701 - Signal A<8> connected to top level port A<8> has been
removed.
WARNING:MapLib:310 - Clock Feedback Frequency cannot be determined for DCM_SP
symbol "i_sensorpads/i_sensor_phase/i_dcm_sensor" (output
signal=i_sensorpads/i_sensor_phase/dcm_out0). CLK_FEEDBACK is set to 1X by
default.
WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX
symbol "i_pclk" (output signal=pclk) has a mix of clock and non-clock loads.
The non-clock loads are:
Pin I0 of i_sensorpads/Mmux_fifo_clkin11
WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX
symbol "physical_group_sclk0/i_iclockios/i_sclk0" (output signal=sclk0) has a
mix of clock and non-clock loads. The non-clock loads are:
Pin PSCLK of physical_group_i_dcm333/isdclk180/i_dcm333/i_dcm2
Pin PSCLK of
physical_group_i_sensorpads/i_sensor_phase/pre_pre_en_idata/i_sensorpads/i_se
nsor_phase/i_dcm_sensor
WARNING:Pack:266 - The function generator
i_mcontr/i_chArbit/next_eqZero_OR_231_o failed to merge with F5 multiplexer
i_mcontr/i_chArbit/next_GND_84_o_AND_481_o_f5. There is a conflict for the
FXMUX. The design will exhibit suboptimal timing.
WARNING:PhysDesignRules:372 - Gated clock. Clock net i_sensorpads/fifo_clkin is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cb_xt_pol_virt_trig_MUX_728_o is sourced by a combinatorial pin. This is not
good design practice. Use the CE pin to control the loading of data into the
flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net compressor_eot is sourced
by a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:1063 - Issue with pin connections and/or configuration
on block:<i_compressor/i_color_proc/i_y_buff.A>:<RAMB16_RAMB16A>. The block
is configured to use an input parity pins. There is a dangling output parity
pin.
WARNING:PhysDesignRules:1067 - Issue with pin connections and/or configuration
on block:<i_sensorpix/i_cstableh.B>:<RAMB16_RAMB16B>. The block is
configured to use an input parity pin. There is a dangling output parity pin.
WARNING:PhysDesignRules:1067 - Issue with pin connections and/or configuration
on block:<i_sensorpix/i_cstablel.B>:<RAMB16_RAMB16B>. The block is
configured to use an input parity pin. There is a dangling output parity pin.
WARNING:PhysDesignRules:1063 - Issue with pin connections and/or configuration
on block:<i_compressor/i_color_proc/i_CrCb_buff.A>:<RAMB16_RAMB16A>. The
block is configured to use an input parity pins. There is a dangling output
parity pin.
Section 3 - Informational
-------------------------
INFO:LIT:243 - Logical network i_BA0/O has no load.
INFO:LIT:395 - The above info message is repeated 296 more times for the
following (max. 5 shown):
i_BA1/O,
i_SYS_SDWE/O,
i_SYS_SDCAS/O,
i_SYS_SDRAS/O,
i_SYS_SDCLK/O
To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
Section 4 - Removed Logic Summary
---------------------------------
62 block(s) removed
312 block(s) optimized away
85 signal(s) removed
Section 5 - Removed Logic
-------------------------
The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections. If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented. This
indentation will be repeated as a chain of related logic is removed.
To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).
Loadless block "i_iclk2" (BUF) removed.
The signal "CLK2" is loadless and has been removed.
Loadless block "CLK2" (PAD) removed.
Loadless block "i_iclk4" (BUF) removed.
The signal "CLK4" is loadless and has been removed.
Loadless block "CLK4" (PAD) removed.
Loadless block "i_iclockios/i_sclk180" (CKBUF) removed.
The signal "i_iclockios/isclk180" is loadless and has been removed.
Loadless block "i_sysinterface/i_a10/i_q/i_qr" (LATCH) removed.
The signal "i_sysinterface/i_a10/q" is loadless and has been removed.
Loadless block "i_sysinterface/i_a10/i_q/i_q/IBUF" (BUF) removed.
The signal "A<10>" is loadless and has been removed.
Loadless block "A<10>" (PAD) removed.
Loadless block "i_sysinterface/i_a10/i_q/i_q/OBUFT" (TRI) removed.
Loadless block "i_sysinterface/i_a11/i_q/i_qr" (LATCH) removed.
The signal "i_sysinterface/i_a11/q" is loadless and has been removed.
Loadless block "i_sysinterface/i_a11/i_q/i_q/IBUF" (BUF) removed.
The signal "A<11>" is loadless and has been removed.
Loadless block "A<11>" (PAD) removed.
Loadless block "i_sysinterface/i_a11/i_q/i_q/OBUFT" (TRI) removed.
Loadless block "i_sysinterface/i_a12/i_q/i_qr" (LATCH) removed.
The signal "i_sysinterface/i_a12/q" is loadless and has been removed.
Loadless block "i_sysinterface/i_a12/i_q/i_q/IBUF" (BUF) removed.
The signal "A<12>" is loadless and has been removed.
Loadless block "A<12>" (PAD) removed.
Loadless block "i_sysinterface/i_a12/i_q/i_q/OBUFT" (TRI) removed.
Loadless block "i_sysinterface/i_a8/i_q/i_qr" (LATCH) removed.
The signal "i_sysinterface/i_a8/q" is loadless and has been removed.
Loadless block "i_sysinterface/i_a8/i_q/i_q/IBUF" (BUF) removed.
The signal "A<8>" is loadless and has been removed.
Loadless block "A<8>" (PAD) removed.
Loadless block "i_sysinterface/i_a8/i_q/i_q/OBUFT" (TRI) removed.
Loadless block "i_sysinterface/i_a9/i_q/i_qr" (LATCH) removed.
The signal "i_sysinterface/i_a9/q" is loadless and has been removed.
Loadless block "i_sysinterface/i_a9/i_q/i_q/IBUF" (BUF) removed.
The signal "A<9>" is loadless and has been removed.
Loadless block "A<9>" (PAD) removed.
Loadless block "i_sysinterface/i_a9/i_q/i_q/OBUFT" (TRI) removed.
The signal "i_BA0/O" is sourceless and has been removed.
The signal "i_BA1/O" is sourceless and has been removed.
The signal "i_SYS_SDWE/O" is sourceless and has been removed.
The signal "i_SYS_SDCAS/O" is sourceless and has been removed.
The signal "i_SYS_SDRAS/O" is sourceless and has been removed.
The signal "i_SYS_SDCLK/O" is sourceless and has been removed.
The signal "i_BG/O" is sourceless and has been removed.
The signal "i_compressor/i_quantizator/i_hfc_en/Q" is sourceless and has been
removed.
The signal "i_compressor/i_quantizator/i_hfc_en/CE" is sourceless and has been
removed.
The signal "i_compressor/i_xdct/i_dct_stage2/i_disdv/Q" is sourceless and has
been removed.
The signal "i_compressor/i_xdct/i_dct_stage2/i_disdv/CE" is sourceless and has
been removed.
The signal "i_compressor/i_color_proc/i_csconvert18/Mshreg_pa_17_17_0/Q" is
sourceless and has been removed.
The signal "i_compressor/i_color_proc/i_csconvert18/Mshreg_pa_13_17_0/Q" is
sourceless and has been removed.
The signal "i_compressor/i_color_proc/i_csconvert18/Mshreg_pa_16_17_0/Q" is
sourceless and has been removed.
The signal "i_compressor/i_color_proc/i_csconvert18/Mshreg_pa_14_17_0/Q" is
sourceless and has been removed.
The signal "i_compressor/i_color_proc/i_csconvert18/Mshreg_pa_10_17_0/Q" is
sourceless and has been removed.
The signal "i_compressor/i_color_proc/i_csconvert18/Mshreg_pa_15_17_0/Q" is
sourceless and has been removed.
The signal "i_compressor/i_color_proc/i_csconvert18/Mshreg_pa_11_17_0/Q" is
sourceless and has been removed.
The signal "i_compressor/i_color_proc/i_csconvert18/Mshreg_pa_12_17_0/Q" is
sourceless and has been removed.
The signal "i_compressor/i_color_proc/i_csconvert18/Mshreg_pd_17_17_0/Q" is
sourceless and has been removed.
The signal "i_compressor/i_color_proc/i_csconvert18/Mshreg_pd_16_17_0/Q" is
sourceless and has been removed.
The signal "i_compressor/i_color_proc/i_csconvert18/Mshreg_pd_15_17_0/Q" is
sourceless and has been removed.
The signal "i_compressor/i_color_proc/i_csconvert18/Mshreg_pd_12_17_0/Q" is
sourceless and has been removed.
The signal "i_compressor/i_color_proc/i_csconvert18/Mshreg_pd_14_17_0/Q" is
sourceless and has been removed.
The signal "i_compressor/i_color_proc/i_csconvert18/Mshreg_pd_13_17_0/Q" is
sourceless and has been removed.
The signal "i_compressor/i_color_proc/i_csconvert18/Mshreg_pd_11_17_0/Q" is
sourceless and has been removed.
The signal "i_compressor/i_color_proc/i_csconvert18/Mshreg_pd_10_17_0/Q" is
sourceless and has been removed.
The signal "i_compressor/i_color_proc/i_csconvert18/Mshreg_pa_27_17_0/Q" is
sourceless and has been removed.
The signal "i_compressor/i_color_proc/i_csconvert18/Mshreg_pa_26_17_0/Q" is
sourceless and has been removed.
The signal "i_compressor/i_color_proc/i_csconvert18/Mshreg_pa_25_17_0/Q" is
sourceless and has been removed.
The signal "i_compressor/i_color_proc/i_csconvert18/Mshreg_pa_22_17_0/Q" is
sourceless and has been removed.
The signal "i_compressor/i_color_proc/i_csconvert18/Mshreg_pa_24_17_0/Q" is
sourceless and has been removed.
The signal "i_compressor/i_color_proc/i_csconvert18/Mshreg_pa_23_17_0/Q" is
sourceless and has been removed.
The signal "i_compressor/i_color_proc/i_csconvert18/Mshreg_pa_21_17_0/Q" is
sourceless and has been removed.
The signal "i_compressor/i_color_proc/i_csconvert18/Mshreg_pa_20_17_0/Q" is
sourceless and has been removed.
The trimmed logic reported below is either:
1. part of a cycle
2. part of disabled logic
3. a side-effect of other trimmed logic
The signal "cb_hfc_sel<2>" is unused and has been removed.
Unused block "i_control_regs/i_hfc_sel_2" (FF) removed.
The signal "i_control_regs/reg_wr[1]_d2[17]_AND_2986_o" is unused and has been
removed.
Unused block "i_control_regs/reg_wr[1]_d2[17]_AND_2986_o1" (ROM) removed.
The signal "cb_hfc_sel<1>" is unused and has been removed.
Unused block "i_control_regs/i_hfc_sel_1" (FF) removed.
The signal "cb_hfc_sel<0>" is unused and has been removed.
Unused block "i_control_regs/i_hfc_sel_0" (FF) removed.
The signal "i_SDCLKE/i_q/d0" is unused and has been removed.
The signal "i_sensortrig/sync_wr0" is unused and has been removed.
Unused block "i_sensortrig/i_sync_wr0" (FF) removed.
The signal "i_sensortrig/sync_wr" is unused and has been removed.
Unused block "i_sensortrig/i_sync_wr" (FF) removed.
The signal "i_sensortrig/sync_wr1" is unused and has been removed.
Unused block "i_sensortrig/i_sync_wr1" (FF) removed.
The signal "i_mcontr/i_descrproc/enRestart[3]_extRestartRq[3]_OR_152_o" is
unused and has been removed.
Unused block "i_mcontr/i_descrproc/enRestart[3]_extRestartRq[3]_OR_152_o1" (ROM)
removed.
The signal "i_mcontr/i_descrproc/enRestart<3>" is unused and has been removed.
Unused block "i_mcontr/i_descrproc/enRestart_3" (SFF) removed.
The signal
"i_mcontr/i_descrproc/extRestartRq1[3]_extRestartRq2[3]_and_51_OUT<3>" is unused
and has been removed.
The signal "i_mcontr/i_descrproc/extRestartRq0<3>" is unused and has been
removed.
The signal "i_interrupts_vector/irq_insb[15]_irq_insc[15]_and_34_OUT<5>" is
unused and has been removed.
The signal "i_interrupts_vector/irq_insb[15]_irq_insc[15]_and_34_OUT<9>" is
unused and has been removed.
The signal "i_interrupts_vector/irq_insb[15]_irq_insc[15]_and_34_OUT<10>" is
unused and has been removed.
The signal "i_interrupts_vector/irq_insb[15]_irq_insc[15]_and_34_OUT<11>" is
unused and has been removed.
The signal "i_interrupts_vector/irq_insb[15]_irq_insc[15]_and_34_OUT<12>" is
unused and has been removed.
The signal "i_interrupts_vector/irq_insb[15]_irq_insc[15]_and_34_OUT<13>" is
unused and has been removed.
The signal "i_interrupts_vector/irq_insb[15]_irq_insc[15]_and_34_OUT<14>" is
unused and has been removed.
The signal "i_interrupts_vector/irq_insb[15]_irq_insc[15]_and_34_OUT<15>" is
unused and has been removed.
The signal "i_interrupts_vector/irq_insa<15>" is unused and has been removed.
The signal "i_interrupts_vector/irq_insa<14>" is unused and has been removed.
The signal "i_interrupts_vector/irq_insa<13>" is unused and has been removed.
The signal "i_interrupts_vector/irq_insa<12>" is unused and has been removed.
The signal "i_interrupts_vector/irq_insa<11>" is unused and has been removed.
The signal "i_interrupts_vector/irq_insa<10>" is unused and has been removed.
The signal "i_interrupts_vector/irq_insa<9>" is unused and has been removed.
The signal "i_interrupts_vector/irq_insa<5>" is unused and has been removed.
The signal "i_compressor/i_quantizator/hfc_sel[2]_tba[5]_LessThan_78_o1" is
unused and has been removed.
Unused block "i_compressor/i_quantizator/hfc_sel[2]_tba[5]_LessThan_78_o1" (ROM)
removed.
The signal "i_compressor/i_quantizator/ctype_dcc_run_AND_2723_o" is unused and
has been removed.
Unused block "i_compressor/i_quantizator/ctype_dcc_run_AND_2723_o1" (ROM)
removed.
The signal "i_compressor/i_quantizator/dcc_run" is unused and has been removed.
Unused block "i_compressor/i_quantizator/dcc_run" (SFF) removed.
The signal "i_compressor/i_quantizator/ctype_prev<0>" is unused and has been
removed.
Unused block "i_compressor/i_quantizator/ctype_prev_0" (SFF) removed.
The signal "i_compressor/i_xdct/i_dct_stage2/n0026" is unused and has been
removed.
Unused block "i_compressor/i_xdct/i_dct_stage2/n00261" (ROM) removed.
The signal "i_compressor/i_quantizator/hfc_sel[2]_ctype_prev[0]_AND_2736_o10" is
unused and has been removed.
Unused block "i_compressor/i_quantizator/hfc_sel[2]_ctype_prev[0]_AND_2736_o10"
(ROM) removed.
The signal "i_compressor/i_quantizator/hfc_sel[2]_ctype_prev[0]_AND_2736_o28" is
unused and has been removed.
Unused block "i_compressor/i_quantizator/hfc_sel[2]_ctype_prev[0]_AND_2736_o28"
(ROM) removed.
The signal "N1684" is unused and has been removed.
Unused block
"i_compressor/i_quantizator/hfc_sel[2]_ctype_prev[0]_AND_2736_o28_SW0" (ROM)
removed.
The signal "i_compressor/i_quantizator/hfc_sel[2]_ctype_prev[0]_AND_2736_o56" is
unused and has been removed.
Unused block "i_compressor/i_quantizator/hfc_sel[2]_ctype_prev[0]_AND_2736_o56"
(ROM) removed.
Unused block "i_BA0/IBUF" (BUF) removed.
Unused block "i_BA1/IBUF" (BUF) removed.
Unused block "i_BG/IBUF" (BUF) removed.
Unused block "i_SYS_SDCAS/IBUF" (BUF) removed.
Unused block "i_SYS_SDCLK/IBUF" (BUF) removed.
Unused block "i_SYS_SDRAS/IBUF" (BUF) removed.
Unused block "i_SYS_SDWE/IBUF" (BUF) removed.
Unused block "i_compressor/i_quantizator/i_hfc_en/SRL16E" (SRLC16E) removed.
Unused block "i_compressor/i_quantizator/i_hfc_en/VCC" (ONE) removed.
Unused block "i_compressor/i_xdct/i_dct_stage2/i_disdv/SRL16E" (SRLC16E)
removed.
Unused block "i_compressor/i_xdct/i_dct_stage2/i_disdv/VCC" (ONE) removed.
Unused block "i_sysinterface/i_a0/i_q/i_q/OBUFT" (TRI) removed.
Unused block "i_sysinterface/i_a1/i_q/i_q/OBUFT" (TRI) removed.
Unused block "i_sysinterface/i_a2/i_q/i_q/OBUFT" (TRI) removed.
Unused block "i_sysinterface/i_a3/i_q/i_q/OBUFT" (TRI) removed.
Unused block "i_sysinterface/i_a4/i_q/i_q/OBUFT" (TRI) removed.
Unused block "i_sysinterface/i_a5/i_q/i_q/OBUFT" (TRI) removed.
Unused block "i_sysinterface/i_a6/i_q/i_q/OBUFT" (TRI) removed.
Unused block "i_sysinterface/i_a7/i_q/i_q/OBUFT" (TRI) removed.
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
FD i_SDCLKE/i_q/i_d0
optimized to 1
FD_1 i_SDCLKE/i_q/i_dr
optimized to 1
FDC i_interrupts_vector/i_insa_10
optimized to 0
FDC i_interrupts_vector/i_insa_11
optimized to 0
FDC i_interrupts_vector/i_insa_12
optimized to 0
FDC i_interrupts_vector/i_insa_13
optimized to 0
FDC i_interrupts_vector/i_insa_14
optimized to 0
FDC i_interrupts_vector/i_insa_15
optimized to 0
FDC i_interrupts_vector/i_insa_5
optimized to 0
FDC i_interrupts_vector/i_insa_9
optimized to 0
LUT2 i_interrupts_vector/irq_insb[15]_irq_insc[15]_and_34_OUT<10>1
optimized to 0
LUT2 i_interrupts_vector/irq_insb[15]_irq_insc[15]_and_34_OUT<11>1
optimized to 0
LUT2 i_interrupts_vector/irq_insb[15]_irq_insc[15]_and_34_OUT<12>1
optimized to 0
LUT2 i_interrupts_vector/irq_insb[15]_irq_insc[15]_and_34_OUT<13>1
optimized to 0
LUT2 i_interrupts_vector/irq_insb[15]_irq_insc[15]_and_34_OUT<14>1
optimized to 0
LUT2 i_interrupts_vector/irq_insb[15]_irq_insc[15]_and_34_OUT<15>1
optimized to 0
LUT2 i_interrupts_vector/irq_insb[15]_irq_insc[15]_and_34_OUT<5>1
optimized to 0
LUT2 i_interrupts_vector/irq_insb[15]_irq_insc[15]_and_34_OUT<9>1
optimized to 0
FDR_1 i_interrupts_vector/irq_insb_10
optimized to 0
FDR_1 i_interrupts_vector/irq_insb_11
optimized to 0
FDR_1 i_interrupts_vector/irq_insb_12
optimized to 0
FDR_1 i_interrupts_vector/irq_insb_13
optimized to 0
FDR_1 i_interrupts_vector/irq_insb_14
optimized to 0
FDR_1 i_interrupts_vector/irq_insb_15
optimized to 0
FDR_1 i_interrupts_vector/irq_insb_5
optimized to 0
FDR_1 i_interrupts_vector/irq_insb_9
optimized to 0
FDR_1 i_interrupts_vector/irq_insc_10
optimized to 0
FDR_1 i_interrupts_vector/irq_insc_11
optimized to 0
FDR_1 i_interrupts_vector/irq_insc_12
optimized to 0
FDR_1 i_interrupts_vector/irq_insc_13
optimized to 0
FDR_1 i_interrupts_vector/irq_insc_14
optimized to 0
FDR_1 i_interrupts_vector/irq_insc_15
optimized to 0
FDR_1 i_interrupts_vector/irq_insc_5
optimized to 0
FDR_1 i_interrupts_vector/irq_insc_9
optimized to 0
LUT2 i_mcontr/i_descrproc/extRestartRq1[3]_extRestartRq2[3]_and_51_OUT<3>1
optimized to 0
FD_1 i_mcontr/i_descrproc/extRestartRq1_3
optimized to 0
FD_1 i_mcontr/i_descrproc/extRestartRq2_3
optimized to 0
FD_1 i_mcontr/i_descrproc/extRestartRq_3
optimized to 0
FDCE i_mcontr/i_descrproc/i_extRestartRq0_3
optimized to 0
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Term | Strength | Rate | | | Delay |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| A<0> | IBUF | INPUT | LVCMOS33 | | | | IFF1 | | 0 / 0 |
| A<1> | IBUF | INPUT | LVCMOS33 | | | | IFF1 | | 0 / 0 |
| A<2> | IBUF | INPUT | LVCMOS33 | | | | IFF1 | | 0 / 0 |
| A<3> | IBUF | INPUT | LVCMOS33 | | | | IFF1 | | 0 / 0 |
| A<4> | IBUF | INPUT | LVCMOS33 | | | | IFF1 | | 0 / 0 |
| A<5> | IBUF | INPUT | LVCMOS33 | | | | IFF1 | | 0 / 0 |
| A<6> | IBUF | INPUT | LVCMOS33 | | | | IFF1 | | 0 / 0 |
| A<7> | IBUF | INPUT | LVCMOS33 | | | | IFF1 | | 0 / 0 |
| ALWAYS0 | IBUF | INPUT | LVCMOS25 | | | | | PULLDOWN | 0 / 0 |
| ARO | IOB | OUTPUT | LVCMOS25 | | 4 | SLOW | | | 0 / 0 |
| ARST | IOB | OUTPUT | LVCMOS25 | | 4 | SLOW | | | 0 / 0 |
| BA<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | 0 / 0 |
| BA<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | 0 / 0 |
| BG | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | 0 / 0 |
| BPF | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
| BRIN | IBUF | INPUT | LVCMOS33 | | | | | | 0 / 0 |
| BROUT | IOB | OUTPUT | LVCMOS33 | | 4 | SLOW | | | 0 / 0 |
| CE | IBUF | INPUT | LVCMOS33 | | | | | | 0 / 0 |
| CE1 | IBUF | INPUT | LVCMOS33 | | | | | | 0 / 0 |
| CLK0 | IBUF | INPUT | LVCMOS33 | | | | | | 0 / 0 |
| CLK1 | IBUF | INPUT | LVCMOS33 | | | | | | 0 / 0 |
| CLK3 | IBUF | INPUT | LVCMOS33 | | | | IFF1 | | 0 / 3 |
| CNVCLK | IOB | BIDIR | LVCMOS25 | | 4 | SLOW | IFF1 | | 0 / 3 |
| CNVSYNC | IOB | BIDIR | LVCMOS25 | | 4 | SLOW | IFF1 | | 0 / 3 |
| D<0> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<1> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<2> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<3> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<4> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<5> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<6> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<7> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<8> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<9> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<10> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<11> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<12> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<13> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<14> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<15> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<16> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<17> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<18> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<19> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<20> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<21> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<22> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<23> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<24> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<25> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<26> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<27> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<28> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<29> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<30> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| D<31> | IOB | BIDIR | LVCMOS33 | | 8 | SLOW | IFF1 | | 0 / 0 |
| DACK0 | IBUF | INPUT | LVCMOS33 | | | | | | 0 / 0 |
| DACK1 | IBUF | INPUT | LVCMOS33 | | | | | | 0 / 0 |
| DCLK | IOB | BIDIR | LVCMOS25 | | 4 | SLOW | IFF1 | | 0 / 3 |
| DREQ0 | IOB | OUTPUT | LVCMOS33 | | 4 | SLOW | OFF1 | | 0 / 0 |
| DREQ1 | IOB | OUTPUT | LVCMOS33 | | 4 | SLOW | OFF1 | | 0 / 0 |
| DUMMYVFEF | IOB | BIDIR | SSTL2_I | | | | | | 0 / 0 |
| EXT<0> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 |
| EXT<1> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 |
| EXT<2> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 |
| EXT<3> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 |
| EXT<4> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 |
| EXT<5> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 |
| EXT<6> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 |
| EXT<7> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 |
| EXT<8> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 |
| EXT<9> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 |
| EXT<10> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 |
| EXT<11> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 |
| HACT | IBUF | INPUT | LVCMOS25 | | | | IDDR2 | | 0 / 3 |
| IRQ | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | 0 / 0 |
| LDQS | IOB | BIDIR | SSTL2_I | | | | IFF1 | | 0 / 0 |
| | | | | | | | ODDR2 | | |
| MRST | IOB | BIDIR | LVCMOS25 | | 4 | SLOW | | PULLUP | 0 / 0 |
| OE | IBUF | INPUT | LVCMOS33 | | | | | | 0 / 0 |
| PXD<0> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
| PXD<1> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
| PXD<2> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
| PXD<3> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
| PXD<4> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
| PXD<5> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
| PXD<6> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
| PXD<7> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
| PXD<8> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
| PXD<9> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
| SCL0 | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | PULLUP | 0 / 0 |
| SDA0 | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| SDA<0> | IOB | OUTPUT | SSTL2_I | | | | OFF1 | | 0 / 0 |
| SDA<1> | IOB | OUTPUT | SSTL2_I | | | | OFF1 | | 0 / 0 |
| SDA<2> | IOB | OUTPUT | SSTL2_I | | | | OFF1 | | 0 / 0 |
| SDA<3> | IOB | OUTPUT | SSTL2_I | | | | OFF1 | | 0 / 0 |
| SDA<4> | IOB | OUTPUT | SSTL2_I | | | | OFF1 | | 0 / 0 |
| SDA<5> | IOB | OUTPUT | SSTL2_I | | | | OFF1 | | 0 / 0 |
| SDA<6> | IOB | OUTPUT | SSTL2_I | | | | OFF1 | | 0 / 0 |
| SDA<7> | IOB | OUTPUT | SSTL2_I | | | | OFF1 | | 0 / 0 |
| SDA<8> | IOB | OUTPUT | SSTL2_I | | | | OFF1 | | 0 / 0 |
| SDA<9> | IOB | OUTPUT | SSTL2_I | | | | OFF1 | | 0 / 0 |
| SDA<10> | IOB | OUTPUT | SSTL2_I | | | | OFF1 | | 0 / 0 |
| SDA<11> | IOB | OUTPUT | SSTL2_I | | | | OFF1 | | 0 / 0 |
| SDA<12> | IOB | OUTPUT | SSTL2_I | | | | OFF1 | | 0 / 0 |
| SDA<13> | IOB | OUTPUT | SSTL2_I | | | | OFF1 | | 0 / 0 |
| SDA<14> | IOB | OUTPUT | SSTL2_I | | | | OFF1 | | 0 / 0 |
| SDCAS | IOB | OUTPUT | SSTL2_I | | | | OFF1 | | 0 / 0 |
| SDCLK | DIFFM | OUTPUT | DIFF_SSTL2_I | | | | | | 0 / 0 |
| SDCLKE | IOB | OUTPUT | SSTL2_I | | | | | | 0 / 0 |
| SDCLK_FB | DIFFSI | INPUT | DIFF_SSTL2_I | | | | | | 0 / 0 |
| SDD<0> | IOB | BIDIR | SSTL2_I | | | | IDDR2 | | 0 / 0 |
| | | | | | | | ODDR2 | | |
| | | | | | | | TFF1 | | |
| SDD<1> | IOB | BIDIR | SSTL2_I | | | | IDDR2 | | 0 / 0 |
| | | | | | | | ODDR2 | | |
| | | | | | | | TFF1 | | |
| SDD<2> | IOB | BIDIR | SSTL2_I | | | | IDDR2 | | 0 / 0 |
| | | | | | | | ODDR2 | | |
| | | | | | | | TFF1 | | |
| SDD<3> | IOB | BIDIR | SSTL2_I | | | | IDDR2 | | 0 / 0 |
| | | | | | | | ODDR2 | | |
| | | | | | | | TFF1 | | |
| SDD<4> | IOB | BIDIR | SSTL2_I | | | | IDDR2 | | 0 / 0 |
| | | | | | | | ODDR2 | | |
| | | | | | | | TFF1 | | |
| SDD<5> | IOB | BIDIR | SSTL2_I | | | | IDDR2 | | 0 / 0 |
| | | | | | | | ODDR2 | | |
| | | | | | | | TFF1 | | |
| SDD<6> | IOB | BIDIR | SSTL2_I | | | | IDDR2 | | 0 / 0 |
| | | | | | | | ODDR2 | | |
| | | | | | | | TFF1 | | |
| SDD<7> | IOB | BIDIR | SSTL2_I | | | | IDDR2 | | 0 / 0 |
| | | | | | | | ODDR2 | | |
| | | | | | | | TFF1 | | |
| SDD<8> | IOB | BIDIR | SSTL2_I | | | | IDDR2 | | 0 / 0 |
| | | | | | | | ODDR2 | | |
| | | | | | | | TFF1 | | |
| SDD<9> | IOB | BIDIR | SSTL2_I | | | | IDDR2 | | 0 / 0 |
| | | | | | | | ODDR2 | | |
| | | | | | | | TFF1 | | |
| SDD<10> | IOB | BIDIR | SSTL2_I | | | | IDDR2 | | 0 / 0 |
| | | | | | | | ODDR2 | | |
| | | | | | | | TFF1 | | |
| SDD<11> | IOB | BIDIR | SSTL2_I | | | | IDDR2 | | 0 / 0 |
| | | | | | | | ODDR2 | | |
| | | | | | | | TFF1 | | |
| SDD<12> | IOB | BIDIR | SSTL2_I | | | | IDDR2 | | 0 / 0 |
| | | | | | | | ODDR2 | | |
| | | | | | | | TFF1 | | |
| SDD<13> | IOB | BIDIR | SSTL2_I | | | | IDDR2 | | 0 / 0 |
| | | | | | | | ODDR2 | | |
| | | | | | | | TFF1 | | |
| SDD<14> | IOB | BIDIR | SSTL2_I | | | | IDDR2 | | 0 / 0 |
| | | | | | | | ODDR2 | | |
| | | | | | | | TFF1 | | |
| SDD<15> | IOB | BIDIR | SSTL2_I | | | | IDDR2 | | 0 / 0 |
| | | | | | | | ODDR2 | | |
| | | | | | | | TFF1 | | |
| SDLDM | IOB | OUTPUT | SSTL2_I | | | | ODDR2 | | 0 / 0 |
| SDNCLK | DIFFS | OUTPUT | DIFF_SSTL2_I | | | | | | 0 / 0 |
| SDNCLK_FB | DIFFMI | INPUT | DIFF_SSTL2_I | | | | | | 0 / 0 |
| SDRAS | IOB | OUTPUT | SSTL2_I | | | | OFF1 | | 0 / 0 |
| SDUDM | IOB | OUTPUT | SSTL2_I | | | | ODDR2 | | 0 / 0 |
| SDWE | IOB | OUTPUT | SSTL2_I | | | | OFF1 | | 0 / 0 |
| SENSPGM | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | PULLUP | 0 / 0 |
| SYS_BUSEN | IOB | OUTPUT | LVCMOS33 | | 4 | SLOW | | | 0 / 0 |
| SYS_SDCAS | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | 0 / 0 |
| SYS_SDCLK | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | 0 / 0 |
| SYS_SDCLKI | IBUF | INPUT | LVCMOS33 | | | | | | 0 / 0 |
| SYS_SDRAS | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | 0 / 0 |
| SYS_SDWE | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | 0 / 0 |
| UDQS | IOB | BIDIR | SSTL2_I | | | | IFF1 | | 0 / 0 |
| | | | | | | | ODDR2 | | |
| VACT | IBUF | INPUT | LVCMOS25 | | | | IDDR2 | | 0 / 3 |
| WE | IBUF | INPUT | LVCMOS33 | | | | IFF1 | | 0 / 0 |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Timing Report
--------------------------
This design was not run using timing mode.
Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 12 - Control Set Information
------------------------------------
No control set information for this architecture.
Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.
ISE_14_7_results/x353.ngc_xst.xrpt 0 → 100644
View file @ f5c2e000
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="lin64" product="ISE" version="14.7">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Tue Jul 28 15:28:57 2015">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="PATH"/>
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE/"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="LD_LIBRARY_PATH"/>
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Ubuntu"/>
<item stringID="User_EnvOsrelease" value="Ubuntu 14.04.1 LTS"/>
</item>
<item stringID="User_EnvHost" value="elphel-desktop"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value="Intel(R) Core(TM) i7-4771 CPU @ 3.50GHz"/>
<item stringID="speed" value="800.000 MHz"/>
</row>
</table>
</section>
<section stringID="XST_OPTION_SUMMARY">
<item DEFAULT="" label="-ifn" stringID="XST_IFN" value="x353.prj"/>
<item DEFAULT="" label="-ofn" stringID="XST_OFN" value="x353.ngc"/>
<item DEFAULT="" label="-top" stringID="XST_TOP" value="x353"/>
<item DEFAULT="" label="-p" stringID="XST_P" value="xc3s1200eft256-4"/>
<item DEFAULT="" label="-uc" stringID="XST_UC" value="x353.xcf"/>
<item DEFAULT="Speed" label="-opt_mode" stringID="XST_OPTMODE" value="speed"/>
<item DEFAULT="1" label="-opt_level" stringID="XST_OPTLEVEL" value="1"/>
<item DEFAULT="No" label="-write_timing_constraints" stringID="XST_WRITETIMINGCONSTRAINTS" value="YES"/>
</section>
<section stringID="XST_UNISIM_SUMMARY">
<item dataType="int" stringID="XST_NUM_BUF" value="1"/>
<item dataType="int" stringID="XST_NUM_BUFG" value="1"/>
<item dataType="int" stringID="XST_NUM_BUFGMUX" value="1"/>
<item dataType="int" stringID="XST_NUM_DCM" value="3"/>
<item dataType="int" stringID="XST_NUM_FD" value="5"/>
<item dataType="int" stringID="XST_NUM_FDC" value="1"/>
<item dataType="int" stringID="XST_NUM_FDCE" value="1"/>
<item dataType="int" stringID="XST_NUM_FDCPE" value="1"/>
<item dataType="int" stringID="XST_NUM_FDDRCPE" value="1"/>
<item dataType="int" stringID="XST_NUM_FDE" value="1"/>
<item dataType="int" stringID="XST_NUM_IBUF" value="26"/>
<item dataType="int" stringID="XST_NUM_IBUFDS" value="1"/>
<item dataType="int" stringID="XST_NUM_IBUFG" value="1"/>
<item dataType="int" stringID="XST_NUM_IDDR2" value="1"/>
<item dataType="int" stringID="XST_NUM_IOBUF" value="29"/>
<item dataType="int" stringID="XST_NUM_LD" value="1"/>
<item dataType="int" stringID="XST_NUM_LUT4" value="1"/>
<item dataType="int" stringID="XST_NUM_MULT18X18" value="1"/>
<item dataType="int" stringID="XST_NUM_MULT18X18SIO" value="3"/>
<item dataType="int" stringID="XST_NUM_OBUF" value="9"/>
<item dataType="int" stringID="XST_NUM_OBUFDS" value="1"/>
<item dataType="int" stringID="XST_NUM_PULLDOWN" value="1"/>
<item dataType="int" stringID="XST_NUM_PULLUP" value="1"/>
<item dataType="int" stringID="XST_NUM_RAM16X1D" value="1"/>
<item dataType="int" stringID="XST_NUM_ROM32X1" value="6"/>
<item dataType="int" stringID="XST_NUM_SRL16" value="1"/>
</section>
<section stringID="XST_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_RAMS" value="50"></item>
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="286">
<item dataType="int" stringID="XST_10BIT_ADDER" value="10"/>
<item dataType="int" stringID="XST_10BIT_SUBTRACTOR" value="3"/>
<item dataType="int" stringID="XST_11BIT_SUBTRACTOR" value="8"/>
<item dataType="int" stringID="XST_14BIT_SUBTRACTOR" value="4"/>
<item dataType="int" stringID="XST_16BIT_ADDER" value="3"/>
<item dataType="int" stringID="XST_16BIT_SUBTRACTOR" value="1"/>
<item dataType="int" stringID="XST_18BIT_SUBTRACTOR" value="6"/>
<item dataType="int" stringID="XST_2BIT_SUBTRACTOR" value="8"/>
<item dataType="int" stringID="XST_3BIT_ADDER" value="17"/>
<item dataType="int" stringID="XST_3BIT_SUBTRACTOR" value="1"/>
<item dataType="int" stringID="XST_32BIT_ADDER" value="2"/>
<item dataType="int" stringID="XST_4BIT_ADDER" value="15"/>
<item dataType="int" stringID="XST_4BIT_SUBTRACTOR" value="6"/>
<item dataType="int" stringID="XST_5BIT_SUBTRACTOR" value="9"/>
<item dataType="int" stringID="XST_6BIT_SUBTRACTOR" value="5"/>
<item dataType="int" stringID="XST_7BIT_ADDER" value="17"/>
<item dataType="int" stringID="XST_7BIT_SUBTRACTOR" value="4"/>
<item dataType="int" stringID="XST_8BIT_ADDER" value="12"/>
</item>
<item dataType="int" stringID="XST_REGISTERS" value="1778">
<item dataType="int" stringID="XST_1BIT_REGISTER" value="969"/>
<item dataType="int" stringID="XST_10BIT_REGISTER" value="42"/>
<item dataType="int" stringID="XST_11BIT_REGISTER" value="13"/>
<item dataType="int" stringID="XST_14BIT_REGISTER" value="18"/>
<item dataType="int" stringID="XST_16BIT_REGISTER" value="88"/>
<item dataType="int" stringID="XST_18BIT_REGISTER" value="36"/>
<item dataType="int" stringID="XST_19BIT_REGISTER" value="16"/>
<item dataType="int" stringID="XST_2BIT_REGISTER" value="111"/>
<item dataType="int" stringID="XST_22BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_3BIT_REGISTER" value="84"/>
<item dataType="int" stringID="XST_32BIT_REGISTER" value="22"/>
<item dataType="int" stringID="XST_4BIT_REGISTER" value="94"/>
<item dataType="int" stringID="XST_5BIT_REGISTER" value="33"/>
<item dataType="int" stringID="XST_6BIT_REGISTER" value="43"/>
<item dataType="int" stringID="XST_7BIT_REGISTER" value="17"/>
<item dataType="int" stringID="XST_8BIT_REGISTER" value="63"/>
<item dataType="int" stringID="XST_9BIT_REGISTER" value="20"/>
</item>
<item dataType="int" stringID="XST_COMPARATORS" value="67">
<item dataType="int" stringID="XST_1BIT_COMPARATOR_EQUAL" value="11"/>
<item dataType="int" stringID="XST_10BIT_COMPARATOR_EQUAL" value="5"/>
<item dataType="int" stringID="XST_2BIT_COMPARATOR_EQUAL" value="2"/>
<item dataType="int" stringID="XST_3BIT_COMPARATOR_EQUAL" value="10"/>
<item dataType="int" stringID="XST_3BIT_COMPARATOR_NOT_EQUAL" value="6"/>
<item dataType="int" stringID="XST_4BIT_COMPARATOR_EQUAL" value="3"/>
</item>
<item dataType="int" stringID="XST_MULTIPLEXERS" value="782">
<item dataType="int" stringID="XST_1BIT_2TO1_MULTIPLEXER" value="417"/>
<item dataType="int" stringID="XST_10BIT_2TO1_MULTIPLEXER" value="9"/>
<item dataType="int" stringID="XST_11BIT_2TO1_MULTIPLEXER" value="9"/>
<item dataType="int" stringID="XST_14BIT_2TO1_MULTIPLEXER" value="5"/>
<item dataType="int" stringID="XST_16BIT_2TO1_MULTIPLEXER" value="19"/>
<item dataType="int" stringID="XST_16BIT_4TO1_MULTIPLEXER" value="1"/>
<item dataType="int" stringID="XST_18BIT_2TO1_MULTIPLEXER" value="17"/>
<item dataType="int" stringID="XST_2BIT_2TO1_MULTIPLEXER" value="27"/>
<item dataType="int" stringID="XST_3BIT_2TO1_MULTIPLEXER" value="21"/>
<item dataType="int" stringID="XST_32BIT_2TO1_MULTIPLEXER" value="65"/>
<item dataType="int" stringID="XST_4BIT_2TO1_MULTIPLEXER" value="14"/>
<item dataType="int" stringID="XST_5BIT_2TO1_MULTIPLEXER" value="24"/>
<item dataType="int" stringID="XST_6BIT_2TO1_MULTIPLEXER" value="26"/>
<item dataType="int" stringID="XST_7BIT_2TO1_MULTIPLEXER" value="3"/>
<item dataType="int" stringID="XST_8BIT_2TO1_MULTIPLEXER" value="27"/>
<item dataType="int" stringID="XST_8BIT_4TO1_MULTIPLEXER" value="1"/>
</item>
<item dataType="int" stringID="XST_XORS" value="81">
<item dataType="int" stringID="XST_1BIT_XOR2" value="77"/>
</item>
</section>
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_RAMS" value="50"></item>
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="145">
<item dataType="int" stringID="XST_10BIT_ADDER" value="1"/>
<item dataType="int" stringID="XST_10BIT_SUBTRACTOR" value="3"/>
<item dataType="int" stringID="XST_11BIT_SUBTRACTOR" value="7"/>
<item dataType="int" stringID="XST_16BIT_ADDER" value="3"/>
<item dataType="int" stringID="XST_18BIT_SUBTRACTOR" value="5"/>
<item dataType="int" stringID="XST_2BIT_SUBTRACTOR" value="6"/>
<item dataType="int" stringID="XST_3BIT_ADDER" value="6"/>
<item dataType="int" stringID="XST_32BIT_ADDER" value="1"/>
<item dataType="int" stringID="XST_4BIT_ADDER" value="8"/>
<item dataType="int" stringID="XST_4BIT_SUBTRACTOR" value="4"/>
<item dataType="int" stringID="XST_5BIT_SUBTRACTOR" value="4"/>
<item dataType="int" stringID="XST_6BIT_SUBTRACTOR" value="4"/>
<item dataType="int" stringID="XST_7BIT_ADDER" value="9"/>
<item dataType="int" stringID="XST_8BIT_ADDER" value="3"/>
</item>
<item dataType="int" stringID="XST_COUNTERS" value="116">
<item dataType="int" stringID="XST_10BIT_UP_COUNTER" value="7"/>
<item dataType="int" stringID="XST_16BIT_DOWN_COUNTER" value="1"/>
<item dataType="int" stringID="XST_2BIT_DOWN_COUNTER" value="2"/>
<item dataType="int" stringID="XST_2BIT_UP_COUNTER" value="7"/>
<item dataType="int" stringID="XST_3BIT_DOWN_COUNTER" value="1"/>
<item dataType="int" stringID="XST_3BIT_UP_COUNTER" value="11"/>
<item dataType="int" stringID="XST_4BIT_DOWN_COUNTER" value="2"/>
<item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="8"/>
<item dataType="int" stringID="XST_5BIT_DOWN_COUNTER" value="5"/>
<item dataType="int" stringID="XST_9BIT_UP_COUNTER" value="3"/>
</item>
<item dataType="int" stringID="XST_ACCUMULATORS" value="23"></item>
<item dataType="int" stringID="XST_REGISTERS" value="7697">
<item dataType="int" stringID="XST_FLIPFLOPS" value="7697"/>
</item>
<item dataType="int" stringID="XST_SHIFT_REGISTERS" value="1"></item>
<item dataType="int" stringID="XST_COMPARATORS" value="67">
<item dataType="int" stringID="XST_1BIT_COMPARATOR_EQUAL" value="11"/>
<item dataType="int" stringID="XST_10BIT_COMPARATOR_EQUAL" value="5"/>
<item dataType="int" stringID="XST_2BIT_COMPARATOR_EQUAL" value="2"/>
<item dataType="int" stringID="XST_3BIT_COMPARATOR_EQUAL" value="10"/>
<item dataType="int" stringID="XST_3BIT_COMPARATOR_NOT_EQUAL" value="6"/>
<item dataType="int" stringID="XST_4BIT_COMPARATOR_EQUAL" value="3"/>
</item>
<item dataType="int" stringID="XST_MULTIPLEXERS" value="903">
<item dataType="int" stringID="XST_1BIT_2TO1_MULTIPLEXER" value="605"/>
<item dataType="int" stringID="XST_1BIT_4TO1_MULTIPLEXER" value="8"/>
<item dataType="int" stringID="XST_10BIT_2TO1_MULTIPLEXER" value="6"/>
<item dataType="int" stringID="XST_11BIT_2TO1_MULTIPLEXER" value="6"/>
<item dataType="int" stringID="XST_14BIT_2TO1_MULTIPLEXER" value="1"/>
<item dataType="int" stringID="XST_16BIT_2TO1_MULTIPLEXER" value="14"/>
<item dataType="int" stringID="XST_16BIT_4TO1_MULTIPLEXER" value="1"/>
<item dataType="int" stringID="XST_18BIT_2TO1_MULTIPLEXER" value="15"/>
<item dataType="int" stringID="XST_2BIT_2TO1_MULTIPLEXER" value="19"/>
<item dataType="int" stringID="XST_3BIT_2TO1_MULTIPLEXER" value="18"/>
<item dataType="int" stringID="XST_32BIT_2TO1_MULTIPLEXER" value="61"/>
<item dataType="int" stringID="XST_4BIT_2TO1_MULTIPLEXER" value="12"/>
<item dataType="int" stringID="XST_5BIT_2TO1_MULTIPLEXER" value="14"/>
<item dataType="int" stringID="XST_6BIT_2TO1_MULTIPLEXER" value="25"/>
<item dataType="int" stringID="XST_8BIT_2TO1_MULTIPLEXER" value="22"/>
</item>
<item dataType="int" stringID="XST_XORS" value="81">
<item dataType="int" stringID="XST_1BIT_XOR2" value="77"/>
</item>
</section>
<section stringID="XST_FINAL_REGISTER_REPORT">
<item dataType="int" stringID="XST_REGISTERS" value="7452">
<item dataType="int" stringID="XST_FLIPFLOPS" value="7452"/>
</item>
<item dataType="int" stringID="XST_SHIFT_REGISTERS" value="189">
<item dataType="int" stringID="XST_2BIT_SHIFT_REGISTER" value="134"/>
<item dataType="int" stringID="XST_3BIT_SHIFT_REGISTER" value="3"/>
</item>
</section>
<section stringID="XST_PARTITION_REPORT">
<section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
</section>
</section>
<section stringID="XST_DESIGN_SUMMARY">
<section stringID="XST_">
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="x353.ngc"/>
</section>
<section stringID="XST_PRIMITIVE_AND_BLACK_BOX_USAGE">
<item dataType="int" stringID="XST_BELS" value="13092">
<item dataType="int" stringID="XST_BUF" value="2"/>
<item dataType="int" stringID="XST_GND" value="1"/>
<item dataType="int" stringID="XST_INV" value="677"/>
<item dataType="int" stringID="XST_LUT1" value="424"/>
<item dataType="int" stringID="XST_LUT2" value="1612"/>
<item dataType="int" stringID="XST_LUT2D" value="1"/>
<item dataType="int" stringID="XST_LUT3" value="2550"/>
<item dataType="int" stringID="XST_LUT3D" value="2"/>
<item dataType="int" stringID="XST_LUT3L" value="3"/>
<item dataType="int" stringID="XST_LUT4" value="3086"/>
<item dataType="int" stringID="XST_LUT4L" value="4"/>
<item dataType="int" stringID="XST_MULTAND" value="88"/>
<item dataType="int" stringID="XST_MUXCY" value="2055"/>
<item dataType="int" stringID="XST_MUXF5" value="602"/>
<item dataType="int" stringID="XST_MUXF6" value="21"/>
<item dataType="int" stringID="XST_VCC" value="1"/>
<item dataType="int" stringID="XST_XORCY" value="1963"/>
</item>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="7750">
<item dataType="int" stringID="XST_FD" value="1684"/>
<item dataType="int" stringID="XST_FD1" value="1154"/>
<item dataType="int" stringID="XST_FDC" value="35"/>
<item dataType="int" stringID="XST_FDC1" value="16"/>
<item dataType="int" stringID="XST_FDCE" value="65"/>
<item dataType="int" stringID="XST_FDCE1" value="20"/>
<item dataType="int" stringID="XST_FDE" value="1501"/>
<item dataType="int" stringID="XST_FDE1" value="1744"/>
<item dataType="int" stringID="XST_FDPE" value="5"/>
<item dataType="int" stringID="XST_FDR" value="273"/>
<item dataType="int" stringID="XST_FDR1" value="228"/>
<item dataType="int" stringID="XST_FDRE" value="605"/>
<item dataType="int" stringID="XST_FDRS" value="32"/>
<item dataType="int" stringID="XST_FDS" value="40"/>
<item dataType="int" stringID="XST_FDSE" value="83"/>
<item dataType="int" stringID="XST_ODDR2" value="20"/>
</item>
<item dataType="int" stringID="XST_RAMS" value="373">
<item dataType="int" stringID="XST_RAM16X1D" value="338"/>
<item dataType="int" stringID="XST_RAMB16S18S18" value="6"/>
<item dataType="int" stringID="XST_RAMB16S36S36" value="1"/>
<item dataType="int" stringID="XST_RAMB16S9S9" value="6"/>
</item>
<item dataType="int" stringID="XST_SHIFT_REGISTERS" value="282">
<item dataType="int" stringID="XST_SRL16" value="185"/>
<item dataType="int" stringID="XST_SRL16E" value="2"/>
</item>
<item dataType="int" stringID="XST_CLOCK_BUFFERS" value="10">
<item dataType="int" label="-bufg" stringID="XST_BUFG" value="8"/>
<item dataType="int" stringID="XST_BUFGMUX" value="2"/>
</item>
<item dataType="int" stringID="XST_IO_BUFFERS" value="147">
<item dataType="int" stringID="XST_IBUF" value="26"/>
<item dataType="int" stringID="XST_IBUFG" value="1"/>
<item dataType="int" label="-iobuf" stringID="XST_IOBUF" value="90"/>
<item dataType="int" stringID="XST_OBUF" value="28"/>
</item>
<item dataType="int" stringID="XST_DCMS" value="4">
<item dataType="int" stringID="XST_DCMSP" value="4"/>
</item>
<item dataType="int" stringID="XST_OTHERS" value="12"></item>
</section>
</section>
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
<item stringID="XST_SELECTED_DEVICE" value="3s1200eft256-4"/>
<item AVAILABLE="8672" dataType="int" label="Number of Slices" stringID="XST_NUMBER_OF_SLICES" value="5524"/>
<item AVAILABLE="17344" dataType="int" label="Number of Slice Flip Flops" stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="7631"/>
<item AVAILABLE="17344" dataType="int" label="Number of 4 input LUTs" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="9342"/>
<item dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="8359"/>
<item dataType="int" label="Number used as Shift registers" stringID="XST_NUMBER_USED_AS_SHIFT_REGISTERS" value="282"/>
<item dataType="int" stringID="XST_NUMBER_USED_AS_RAMS" value="689"/>
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="149"/>
<item AVAILABLE="190" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="148"/>
<item AVAILABLE="28" dataType="int" stringID="XST_NUMBER_OF_BRAMS" value="22"/>
<item AVAILABLE="24" dataType="int" label="Number of GCLKs" stringID="XST_NUMBER_OF_GCLKS" value="10"/>
<item AVAILABLE="8" dataType="int" stringID="XST_NUMBER_OF_DCMS" value="4"/>
</section>
<section stringID="XST_PARTITION_RESOURCE_SUMMARY">
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
</section>
<section stringID="XST_ERRORS_STATISTICS">
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="698"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="228"/>
</section>
</application>
</document>
ISE_14_7_results/x353.pad 0 → 100644
View file @ f5c2e000
Release 14.7 - reportgen P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Tue Jul 28 15:45:48 2015
# NOTE: This file is designed to be imported into a spreadsheet program
# such as Microsoft Excel for viewing, printing and sorting. The |
# character is used as the data field separator. This file is also designed
# to support parsing.
#
INPUT FILE: x353.ncd
OUTPUT FILE: x353.pad
PART TYPE: xc3s1200e
SPEED GRADE: -4
PACKAGE: ft256
Pinout by Pin Number:
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity|
A1|||GND||||||||||||
A2|||TDI||||||||||||
A3||IBUF|IP|UNUSED||0|||||||||
A4|EXT<2>|IOB|IO_L17N_0/VREF_0|BIDIR|LVCMOS33|0|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
A5|EXT<3>|IOB|IO_L17P_0|BIDIR|LVCMOS33|0|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
A6|||VCCAUX||||||||2.5||||
A7|D<16>|IOB|IO|BIDIR|LVCMOS33|0|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
A8|CLK3|IBUF|IP_L10P_0/GCLK8|INPUT|LVCMOS33|0||||IFD||LOCATED|YES|NONE|
A9|CLK0|IBUF|IO_L09N_0/GCLK7|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
A10|CLK1|IBUF|IO_L09P_0/GCLK6|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
A11|||VCCAUX||||||||2.5||||
A12|D<15>|IOB|IO|BIDIR|LVCMOS33|0|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
A13|D<11>|IOB|IO_L03N_0/VREF_0|BIDIR|LVCMOS33|0|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
A14|DACK1|IBUF|IO_L01N_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
A15|||TCK||||||||||||
A16|||GND||||||||||||
B1|CNVSYNC|IOB|IO_L01P_3|BIDIR|LVCMOS25*|3|4|SLOW|NONE**|IFD||LOCATED|YES|NONE|
B2|CNVCLK|IOB|IO_L01N_3|BIDIR|LVCMOS25*|3|4|SLOW|NONE**|IFD||LOCATED|YES|NONE|
B3||DIFFS|IO_L19N_0/HSWAP|UNUSED||0|||||||||
B4|D<19>|IOB|IO|BIDIR|LVCMOS33|0|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
B5|||VCCO_0|||0|||||3.30||||
B6|D<23>|IOB|IO|BIDIR|LVCMOS33|0|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
B7|EXT<7>|IOB|IO_L13P_0|BIDIR|LVCMOS33|0|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
B8||DIFFSI|IP_L10N_0/GCLK9|UNUSED||0|||||||||
B9|||GND||||||||||||
B10|D<14>|IOB|IO|BIDIR|LVCMOS33|0|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
B11|D<12>|IOB|IO_L05N_0/VREF_0|BIDIR|LVCMOS33|0|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
B12|||VCCO_0|||0|||||3.30||||
B13|BROUT|IOB|IO_L03P_0|OUTPUT|LVCMOS33|0|4|SLOW|NONE**|||LOCATED|NO|NONE|
B14|DACK0|IBUF|IO_L01P_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
B15|||TMS||||||||||||
B16|BRIN|IBUF|IP|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE|
C1|ARO|IOB|IO_L02P_3|OUTPUT|LVCMOS25*|3|4|SLOW|NONE**|||LOCATED|NO|NONE|
C2||DIFFS|IO_L02N_3/VREF_3| ||3|||||1.25||||
C3|D<21>|IOB|IO_L19P_0|BIDIR|LVCMOS33|0|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
C4|EXT<0>|IOB|IO_L18N_0|BIDIR|LVCMOS33|0|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
C5|EXT<1>|IOB|IO_L18P_0|BIDIR|LVCMOS33|0|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
C6|EXT<5>|IOB|IO_L15P_0|BIDIR|LVCMOS33|0|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
C7|EXT<6>|IOB|IO_L13N_0|BIDIR|LVCMOS33|0|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
C8|D<30>|IOB|IO_L11P_0/GCLK10|BIDIR|LVCMOS33|0|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
C9||DIFFSI|IP_L07N_0|UNUSED||0|||||||||
C10||DIFFMI|IP_L07P_0|UNUSED||0|||||||||
C11|D<10>|IOB|IO_L05P_0|BIDIR|LVCMOS33|0|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
C12||DIFFSI|IP_L02N_0|UNUSED||0|||||||||
C13||IBUF|IP|UNUSED||0|||||||||
C14|||TDO||||||||||||
C15|DREQ0|IOB|IO_L19N_1/LDC2|OUTPUT|LVCMOS33|1|4|SLOW|NONE**|||LOCATED|YES|NONE|
C16|SYS_BUSEN|IOB|IO_L19P_1/LDC1|OUTPUT|LVCMOS33|1|4|SLOW|NONE**|||LOCATED|NO|NONE|
D1|SENSPGM|IOB|IO_L05P_3|BIDIR|LVCMOS25*|3|12|SLOW|PULLUP|NONE||LOCATED|NO|NONE|
D2||IBUF|IP|UNUSED||3|||||||||
D3|||PROG_B||||||||||||
D4|||VCCINT||||||||1.2||||
D5||DIFFMI|IP_L16P_0|UNUSED||0|||||||||
D6|EXT<4>|IOB|IO_L15N_0|BIDIR|LVCMOS33|0|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
D7|EXT<9>|IOB|IO_L14N_0/VREF_0|BIDIR|LVCMOS33|0|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
D8|D<31>|IOB|IO_L11N_0/GCLK11|BIDIR|LVCMOS33|0|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
D9|D<13>|IOB|IO/VREF_0|BIDIR|LVCMOS33|0|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
D10|DREQ1|IOB|IO_L06P_0|OUTPUT|LVCMOS33|0|4|SLOW|NONE**|||LOCATED|YES|NONE|
D11|BG|IOB|IO_L04P_0|TRISTATE|LVCMOS33|0|12|SLOW|NONE**|||LOCATED|NO|NONE|
D12||DIFFMI|IP_L02P_0|UNUSED||0|||||||||
D13|||VCCINT||||||||1.2||||
D14|A<0>|IBUF|IO_L18N_1/LDC0|INPUT|LVCMOS33|1||||NONE||LOCATED|YES|NONE|
D15|IRQ|IOB|IO_L18P_1/HDC|OUTPUT|LVCMOS33|1|8|SLOW|NONE**|||LOCATED|NO|NONE|
D16|CE|IBUF|IP/VREF_1|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE|
E1|ARST|IOB|IO_L05N_3|OUTPUT|LVCMOS25*|3|4|SLOW|NONE**|||LOCATED|NO|NONE|
E2|||VCCO_3|||3|||||2.50||||
E3|MRST|IOB|IO_L03P_3|BIDIR|LVCMOS25*|3|4|SLOW|PULLUP|NONE||LOCATED|NO|NONE|
E4|SDA0|IOB|IO_L03N_3|BIDIR|LVCMOS25*|3|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
E5|||VCCINT||||||||1.2||||
E6||DIFFSI|IP_L16N_0|UNUSED||0|||||||||
E7|EXT<8>|IOB|IO_L14P_0|BIDIR|LVCMOS33|0|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
E8|EXT<11>|IOB|IO_L12P_0|BIDIR|LVCMOS33|0|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
E9|D<18>|IOB|IO_L08P_0/GCLK4|BIDIR|LVCMOS33|0|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
E10|D<25>|IOB|IO_L06N_0|BIDIR|LVCMOS33|0|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
E11|A<3>|IBUF|IO_L04N_0|INPUT|LVCMOS33|0||||NONE||LOCATED|YES|NONE|
E12|||VCCINT||||||||1.2||||
E13|A<4>|IBUF|IO_L17P_1|INPUT|LVCMOS33|1||||NONE||LOCATED|YES|NONE|
E14|CE1|IBUF|IP|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE|
E15|||VCCO_1|||1|||||3.30||||
E16|A<5>|IBUF|IO_L17N_1|INPUT|LVCMOS33|1||||NONE||LOCATED|YES|NONE|
F1|||VCCAUX||||||||2.5||||
F2||IBUF|IP|UNUSED||3|||||||||
F3||DIFFM|IO_L04P_3|UNUSED||3|||||||||
F4||DIFFS|IO_L04N_3/VREF_3| ||3|||||1.25||||
F5||IBUF|IP|UNUSED||3|||||||||
F6|||GND||||||||||||
F7|||VCCO_0|||0|||||3.30||||
F8|EXT<10>|IOB|IO_L12N_0|BIDIR|LVCMOS33|0|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
F9|D<20>|IOB|IO_L08N_0/GCLK5|BIDIR|LVCMOS33|0|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
F10|||VCCO_0|||0|||||3.30||||
F11|||GND||||||||||||
F12|A<2>|IBUF|IO_L16N_1|INPUT|LVCMOS33|1||||NONE||LOCATED|YES|NONE|
F13|A<1>|IBUF|IO_L16P_1|INPUT|LVCMOS33|1||||NONE||LOCATED|YES|NONE|
F14|A<6>|IBUF|IO_L15P_1|INPUT|LVCMOS33|1||||NONE||LOCATED|YES|NONE|
F15|A<7>|IBUF|IO_L15N_1|INPUT|LVCMOS33|1||||NONE||LOCATED|YES|NONE|
F16|||VCCAUX||||||||2.5||||
G1||IBUF|IP/VREF_3| ||3|||||1.25||||
G2|SCL0|IOB|IO_L07N_3|BIDIR|LVCMOS25*|3|12|SLOW|PULLUP|NONE||LOCATED|NO|NONE|
G3|PXD<8>|IBUF|IO_L07P_3|INPUT|LVCMOS25*|3||||IFD||LOCATED|YES|NONE|
G4|PXD<7>|IBUF|IO_L06N_3|INPUT|LVCMOS25*|3||||IFD||LOCATED|YES|NONE|
G5|PXD<5>|IBUF|IO_L06P_3|INPUT|LVCMOS25*|3||||IFD||LOCATED|YES|NONE|
G6|||VCCO_3|||3|||||2.50||||
G7|||GND||||||||||||
G8|||GND||||||||||||
G9|||GND||||||||||||
G10|||GND||||||||||||
G11|||VCCO_1|||1|||||3.30||||
G12||IBUF|IP|UNUSED||1|||||||||
G13||DIFFM|IO_L14P_1|UNUSED||1|||||||||
G14||DIFFS|IO_L14N_1/A0|UNUSED||1|||||||||
G15||DIFFM|IO_L13P_1/A2|UNUSED||1|||||||||
G16||DIFFS|IO_L13N_1/A1|UNUSED||1|||||||||
H1||IBUF|IP|UNUSED||3|||||||||
H2|||GND||||||||||||
H3|PXD<9>|IBUF|IO_L09P_3/LHCLK2|INPUT|LVCMOS25*|3||||IFD||LOCATED|YES|NONE|
H4|PXD<6>|IBUF|IO_L09N_3/LHCLK3/IRDY2|INPUT|LVCMOS25*|3||||IFD||LOCATED|YES|NONE|
H5|PXD<3>|IBUF|IO_L08P_3/LHCLK0|INPUT|LVCMOS25*|3||||IFD||LOCATED|YES|NONE|
H6|PXD<1>|IBUF|IO_L08N_3/LHCLK1|INPUT|LVCMOS25*|3||||IFD||LOCATED|YES|NONE|
H7|||GND||||||||||||
H8|||GND||||||||||||
H9|||GND||||||||||||
H10|||GND||||||||||||
H11|D<22>|IOB|IO_L12N_1/A3/RHCLK7|BIDIR|LVCMOS33|1|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
H12||DIFFM|IO_L12P_1/A4/RHCLK6|UNUSED||1|||||||||
H13||IBUF|IP/VREF_1|UNUSED||1|||||||||
H14|BA<0>|IOB|IO_L11N_1/A5/RHCLK5|TRISTATE|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
H15|BA<1>|IOB|IO_L11P_1/A6/RHCLK4/IRDY1|TRISTATE|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
H16||IBUF|IP|UNUSED||1|||||||||
J1|PXD<4>|IBUF|IO_L12P_3|INPUT|LVCMOS25*|3||||IFD||LOCATED|YES|NONE|
J2|PXD<2>|IBUF|IO_L10P_3/LHCLK4/TRDY2|INPUT|LVCMOS25*|3||||IFD||LOCATED|YES|NONE|
J3|PXD<0>|IBUF|IO_L10N_3/LHCLK5|INPUT|LVCMOS25*|3||||IFD||LOCATED|YES|NONE|
J4|DUMMYVFEF|IOB|IO_L11N_3/LHCLK7|BIDIR|SSTL2_I|3|||NONE**|NONE||LOCATED|NO|NONE|
J5|HACT|IBUF|IO_L11P_3/LHCLK6|INPUT|LVCMOS25*|3||||IFD||LOCATED|YES|NONE|
J6|ALWAYS0|IBUF|IP|INPUT|LVCMOS25*|3|||PULLDOWN|NONE||LOCATED|NO|NONE|
J7|||GND||||||||||||
J8|||GND||||||||||||
J9|||GND||||||||||||
J10|||GND||||||||||||
J11||IBUF|IP|UNUSED||1|||||||||
J12|SYS_SDCLKI|IBUF|IP|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE|
J13|SYS_SDWE|IOB|IO_L10N_1/A7/RHCLK3/TRDY1|TRISTATE|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
J14|SYS_SDCLK|IOB|IO_L10P_1/A8/RHCLK2|TRISTATE|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
J15|||GND||||||||||||
J16|SYS_SDCAS|IOB|IO_L09N_1/A9/RHCLK1|TRISTATE|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
K1|VACT|IBUF|IO_L12N_3|INPUT|LVCMOS25*|3||||IFD||LOCATED|YES|NONE|
K2|SDA<3>|IOB|IO_L13P_3|OUTPUT|SSTL2_I|3|||NONE**|||LOCATED|YES|NONE|
K3|SDA<1>|IOB|IO_L13N_3|OUTPUT|SSTL2_I|3|||NONE**|||LOCATED|YES|NONE|
K4||IBUF|IP|UNUSED||3|||||||||
K5|BPF|IBUF|IO_L15P_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
K6|||VCCO_3|||3|||||2.50||||
K7|||GND||||||||||||
K8|||GND||||||||||||
K9|||GND||||||||||||
K10|||GND||||||||||||
K11|||VCCO_1|||1|||||3.30||||
K12|D<17>|IOB|IO_L07N_1/A11|BIDIR|LVCMOS33|1|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
K13|D<29>|IOB|IO_L07P_1/A12|BIDIR|LVCMOS33|1|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
K14|D<24>|IOB|IO_L08N_1/VREF_1|BIDIR|LVCMOS33|1|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
K15|D<26>|IOB|IO_L08P_1|BIDIR|LVCMOS33|1|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
K16|SYS_SDRAS|IOB|IO_L09P_1/A10/RHCLK0|TRISTATE|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
L1|||VCCAUX||||||||2.5||||
L2||DIFFS|IO_L14N_3/VREF_3| ||3|||||1.25||||
L3|DCLK|IOB|IO_L14P_3|BIDIR|LVCMOS25*|3|4|SLOW|NONE**|IFD||LOCATED|YES|NONE|
L4|SDA<14>|IOB|IO_L17N_3|OUTPUT|SSTL2_I|3|||NONE**|||LOCATED|YES|NONE|
L5||DIFFS|IO_L15N_3|UNUSED||3|||||||||
L6|||GND||||||||||||
L7|||VCCO_2|||2|||||2.50||||
L8|SDD<7>|IOB|IO_L09N_2/D6/GCLK13|BIDIR|SSTL2_I|2|||NONE**|NONE||LOCATED|YES|NONE|
L9||DIFFM|IO_L13P_2/M0|UNUSED||2|||||||||
L10|||VCCO_2|||2|||||2.50||||
L11|||GND||||||||||||
L12|D<9>|IOB|IO_L05P_1|BIDIR|LVCMOS33|1|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
L13|D<3>|IOB|IO_L05N_1|BIDIR|LVCMOS33|1|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
L14|D<27>|IOB|IO_L06P_1|BIDIR|LVCMOS33|1|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
L15|D<28>|IOB|IO_L06N_1|BIDIR|LVCMOS33|1|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
L16|||VCCAUX||||||||2.5||||
M1|SDA<2>|IOB|IO_L16P_3|OUTPUT|SSTL2_I|3|||NONE**|||LOCATED|YES|NONE|
M2|||VCCO_3|||3|||||2.50||||
M3||IBUF|IP|UNUSED||3|||||||||
M4|SDA<5>|IOB|IO_L17P_3|OUTPUT|SSTL2_I|3|||NONE**|||LOCATED|YES|NONE|
M5|||VCCINT||||||||1.2||||
M6|SDRAS|IOB|IO_L05P_2|OUTPUT|SSTL2_I|2|||NONE**|||LOCATED|YES|NONE|
M7|SDWE|IOB|IO|OUTPUT|SSTL2_I|2|||NONE**|||LOCATED|YES|NONE|
M8|SDLDM|IOB|IO_L09P_2/D7/GCLK12|OUTPUT|SSTL2_I|2|||NONE**|||LOCATED|YES|NONE|
M9|SDD<6>|IOB|IO_L13N_2/DIN/D0|BIDIR|SSTL2_I|2|||NONE**|NONE||LOCATED|YES|NONE|
M10|SDD<10>|IOB|IO_L15N_2|BIDIR|SSTL2_I|2|||NONE**|NONE||LOCATED|YES|NONE|
M11||DIFFSI|IP_L17N_2|UNUSED||2|||||||||
M12|||VCCINT||||||||1.2||||
M13|WE|IBUF|IP|INPUT|LVCMOS33|1||||NONE||LOCATED|YES|NONE|
M14|OE|IBUF|IP|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE|
M15|||VCCO_1|||1|||||3.30||||
M16|D<0>|IOB|IO_L04N_1/VREF_1|BIDIR|LVCMOS33|1|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
N1|SDA<10>|IOB|IO_L16N_3|OUTPUT|SSTL2_I|3|||NONE**|||LOCATED|YES|NONE|
N2||IBUF|IP/VREF_3| ||3|||||1.25||||
N3||IBUF|IP|UNUSED||3|||||||||
N4|||VCCINT||||||||1.2||||
N5|SDA<8>|IOB|IO_L03N_2/MOSI/CSI_B|OUTPUT|SSTL2_I|2|||NONE**|||LOCATED|YES|NONE|
N6|SDCLKE|IOB|IO_L05N_2|OUTPUT|SSTL2_I|2|||NONE**|||LOCATED|NO|NONE|
N7|SDCAS|IOB|IO_L07P_2|OUTPUT|SSTL2_I|2|||NONE**|||LOCATED|YES|NONE|
N8|LDQS|IOB|IO_L10P_2/D4/GCLK14|BIDIR|SSTL2_I|2|||NONE**|NONE||LOCATED|YES|NONE|
N9|SDD<5>|IOB|IO_L12N_2/D1/GCLK3|BIDIR|SSTL2_I|2|||NONE**|NONE||LOCATED|YES|NONE|
N10|SDD<3>|IOB|IO_L15P_2|BIDIR|SSTL2_I|2|||NONE**|NONE||LOCATED|YES|NONE|
N11||DIFFMI|IP_L17P_2|UNUSED||2|||||||||
N12|SDD<2>|IOB|IO_L18N_2/A20|BIDIR|SSTL2_I|2|||NONE**|NONE||LOCATED|YES|NONE|
N13|||VCCINT||||||||1.2||||
N14|D<5>|IOB|IO_L03P_1|BIDIR|LVCMOS33|1|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
N15|D<1>|IOB|IO_L03N_1/VREF_1|BIDIR|LVCMOS33|1|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
N16|D<2>|IOB|IO_L04P_1|BIDIR|LVCMOS33|1|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
P1|SDA<0>|IOB|IO_L18N_3|OUTPUT|SSTL2_I|3|||NONE**|||LOCATED|YES|NONE|
P2|SDA<13>|IOB|IO_L18P_3|OUTPUT|SSTL2_I|3|||NONE**|||LOCATED|YES|NONE|
P3||DIFFM|IO_L01P_2/CSO_B|UNUSED||2|||||||||
P4||DIFFS|IO_L01N_2/INIT_B|UNUSED||2|||||||||
P5|SDA<7>|IOB|IO_L03P_2/DOUT/BUSY|OUTPUT|SSTL2_I|2|||NONE**|||LOCATED|YES|NONE|
P6|SDA<11>|IOB|IO_L06N_2|OUTPUT|SSTL2_I|2|||NONE**|||LOCATED|YES|NONE|
P7|SDA<12>|IOB|IO_L07N_2|OUTPUT|SSTL2_I|2|||NONE**|||LOCATED|YES|NONE|
P8|UDQS|IOB|IO_L10N_2/D3/GCLK15|BIDIR|SSTL2_I|2|||NONE**|NONE||LOCATED|YES|NONE|
P9|SDD<8>|IOB|IO_L12P_2/D2/GCLK2|BIDIR|SSTL2_I|2|||NONE**|NONE||LOCATED|YES|NONE|
P10|SDD<9>|IOB|IO_L14P_2|BIDIR|SSTL2_I|2|||NONE**|NONE||LOCATED|YES|NONE|
P11|SDD<11>|IOB|IO_L16N_2/A22|BIDIR|SSTL2_I|2|||NONE**|NONE||LOCATED|YES|NONE|
P12|SDD<12>|IOB|IO_L18P_2/A21|BIDIR|SSTL2_I|2|||NONE**|NONE||LOCATED|YES|NONE|
P13||IOB|IO/VREF_2| ||2|||||1.25||||
P14|SDD<15>|IOB|IO_L20P_2/VS0/A17|BIDIR|SSTL2_I|2|||NONE**|NONE||LOCATED|YES|NONE|
P15|D<7>|IOB|IO_L02N_1/A13|BIDIR|LVCMOS33|1|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
P16|D<4>|IOB|IO_L02P_1/A14|BIDIR|LVCMOS33|1|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
R1|SDNCLK|DIFFS|IO_L19N_3|OUTPUT|DIFF_SSTL2_I|3|||NONE**|||LOCATED|NO|NONE|
R2|SDCLK|DIFFM|IO_L19P_3|OUTPUT|DIFF_SSTL2_I|3|||NONE**|||LOCATED|NO|NONE|
R3|SDCLK_FB|DIFFSI|IP_L02N_2|INPUT|DIFF_SSTL2_I|2||||NONE||LOCATED|NO|NONE|
R4||IOB|IO/VREF_2| ||2|||||1.25||||
R5|||VCCO_2|||2|||||2.50||||
R6|SDA<9>|IOB|IO_L06P_2|OUTPUT|SSTL2_I|2|||NONE**|||LOCATED|YES|NONE|
R7||DIFFMI|IP_L08P_2|UNUSED||2|||||||||
R8|||GND||||||||||||
R9||DIFFSI|IP_L11N_2/M2/GCLK1|UNUSED||2|||||||||
R10||DIFFS|IO_L14N_2/VREF_2| ||2|||||1.25||||
R11|SDD<4>|IOB|IO_L16P_2/A23|BIDIR|SSTL2_I|2|||NONE**|NONE||LOCATED|YES|NONE|
R12|||VCCO_2|||2|||||2.50||||
R13|SDD<13>|IOB|IO_L19N_2/VS1/A18|BIDIR|SSTL2_I|2|||NONE**|NONE||LOCATED|YES|NONE|
R14|SDD<0>|IOB|IO_L20N_2/CCLK|BIDIR|SSTL2_I|2|||NONE**|NONE||LOCATED|YES|NONE|
R15|D<8>|IOB|IO_L01N_1/A15|BIDIR|LVCMOS33|1|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
R16|D<6>|IOB|IO_L01P_1/A16|BIDIR|LVCMOS33|1|8|SLOW|NONE**|NONE||LOCATED|YES|NONE|
T1|||GND||||||||||||
T2||IBUF|IP|UNUSED||2|||||||||
T3|SDNCLK_FB|DIFFMI|IP_L02P_2|INPUT|DIFF_SSTL2_I|2||||NONE||LOCATED|NO|NONE|
T4|SDA<4>|IOB|IO_L04P_2|OUTPUT|SSTL2_I|2|||NONE**|||LOCATED|YES|NONE|
T5|SDA<6>|IOB|IO_L04N_2|OUTPUT|SSTL2_I|2|||NONE**|||LOCATED|YES|NONE|
T6|||VCCAUX||||||||2.5||||
T7||DIFFSI|IP_L08N_2/VREF_2| ||2|||||1.25||||
T8|SDUDM|IOB|IO/D5|OUTPUT|SSTL2_I|2|||NONE**|||LOCATED|YES|NONE|
T9||DIFFMI|IP_L11P_2/RDWR_B/GCLK0|UNUSED||2|||||||||
T10||IOB|IO/M1|UNUSED||2|||||||||
T11|||VCCAUX||||||||2.5||||
T12|SDD<1>|IOB|IO|BIDIR|SSTL2_I|2|||NONE**|NONE||LOCATED|YES|NONE|
T13|SDD<14>|IOB|IO_L19P_2/VS2/A19|BIDIR|SSTL2_I|2|||NONE**|NONE||LOCATED|YES|NONE|
T14||IBUF|IP|UNUSED||2|||||||||
T15|||DONE||||||||||||
T16|||GND||||||||||||
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
* Default value.
** This default Pullup/Pulldown value can be overridden in Bitgen.
****** Special VCCO requirements may apply. Please consult the device
family datasheet for specific guideline on VCCO requirements.
ISE_14_7_results/x353.par 0 → 100644
View file @ f5c2e000
Release 14.7 par P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
elphel-desktop:: Tue Jul 28 15:41:02 2015
par -w x353.ncd x353.ncd x353.pcf
Constraints file: x353.pcf.
Loading device for application Rf_Device from file '3s1200e.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
"x353" is an NCD, version 3.2, device xc3s1200e, package ft256, speed -4
Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)
Device speed data version: "PRODUCTION 1.27 2013-10-13".
Design Summary Report:
Number of External IOBs 142 out of 190 74%
Number of External Input IOBs 35
Number of External Input DIFFMIs 1
Number of LOCed External Input DIFFMIs 1 out of 1 100%
Number of External Input DIFFSIs 1
Number of LOCed External Input DIFFSIs 1 out of 1 100%
Number of External Input IBUFs 33
Number of LOCed External Input IBUFs 33 out of 33 100%
Number of External Output IOBs 37
Number of External Output DIFFMs 1
Number of LOCed External Output DIFFMs 1 out of 1 100%
Number of External Output DIFFSs 1
Number of LOCed External Output DIFFSs 1 out of 1 100%
Number of External Output IOBs 35
Number of LOCed External Output IOBs 35 out of 35 100%
Number of External Bidir IOBs 70
Number of External Bidir IOBs 70
Number of LOCed External Bidir IOBs 70 out of 70 100%
Number of BUFGMUXs 9 out of 24 37%
Number of DCMs 4 out of 8 50%
Number of MULT18X18SIOs 19 out of 28 67%
Number of RAMB16s 22 out of 28 78%
Number of Slices 6969 out of 8672 80%
Number of SLICEMs 553 out of 4336 12%
Overall effort level (-ol): Standard
Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please
consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 5 secs
Finished initial Timing Analysis. REAL time: 5 secs
Starting Placer
Total REAL time at the beginning of Placer: 5 secs
Total CPU time at the beginning of Placer: 5 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:5f7894a7) REAL time: 6 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:5f7894a7) REAL time: 6 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:5f7894a7) REAL time: 6 secs
Phase 4.2 Initial Clock and IO Placement
...................
WARNING:Place:1019 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB /
clock site pair. The clock component <i_pclk> is placed at site <BUFGMUX_X1Y11>. The IO component <BPF> is placed at
site <K5>. This will not allow the use of the fast path between the IO and the Clock buffer. This is normally an
ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <BPF.PAD> allowing your design to continue.
This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly
discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in
the design.
Phase 4.2 Initial Clock and IO Placement (Checksum:bf975b3a) REAL time: 8 secs
...........................
.....................................................................
Phase 5.30 Global Clock Region Assignment
Phase 5.30 Global Clock Region Assignment (Checksum:bf975b3a) REAL time: 37 secs
Phase 6.36 Local Placement Optimization
Phase 6.36 Local Placement Optimization (Checksum:bf975b3a) REAL time: 37 secs
Phase 7.8 Global Placement
........................
...................................................................................
......................
............................................................................................................
.....................................................................................
...............................................................................
.......
...............................................
Phase 7.8 Global Placement (Checksum:b7492e3d) REAL time: 1 mins 13 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:b7492e3d) REAL time: 1 mins 13 secs
Phase 9.18 Placement Optimization
Phase 9.18 Placement Optimization (Checksum:ebf023d6) REAL time: 1 mins 20 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:ebf023d6) REAL time: 1 mins 20 secs
Total REAL time to Placer completion: 1 mins 20 secs
Total CPU time to Placer completion: 1 mins 20 secs
Writing design to file x353.ncd
Starting Router
Phase 1 : 45535 unrouted; REAL time: 1 mins 25 secs
Phase 2 : 38069 unrouted; REAL time: 1 mins 26 secs
Phase 3 : 11748 unrouted; REAL time: 1 mins 29 secs
Phase 4 : 11903 unrouted; (Setup:16011, Hold:0, Component Switching Limit:0) REAL time: 1 mins 35 secs
Phase 5 : 0 unrouted; (Setup:29695, Hold:0, Component Switching Limit:0) REAL time: 1 mins 42 secs
Updating file: x353.ncd with current fully routed design.
Phase 6 : 0 unrouted; (Setup:29695, Hold:0, Component Switching Limit:0) REAL time: 1 mins 45 secs
Phase 7 : 0 unrouted; (Setup:7147, Hold:0, Component Switching Limit:0) REAL time: 2 mins 5 secs
Updating file: x353.ncd with current fully routed design.
Phase 8 : 0 unrouted; (Setup:5788, Hold:0, Component Switching Limit:0) REAL time: 2 mins 15 secs
Updating file: x353.ncd with current fully routed design.
Phase 9 : 0 unrouted; (Setup:5788, Hold:0, Component Switching Limit:0) REAL time: 2 mins 28 secs
Phase 10 : 0 unrouted; (Setup:5788, Hold:0, Component Switching Limit:0) REAL time: 2 mins 29 secs
Phase 11 : 0 unrouted; (Setup:5652, Hold:0, Component Switching Limit:0) REAL time: 2 mins 30 secs
WARNING:Route:455 - CLK Net:i_compressor/go_single may have excessive skew because
1 CLK pins and 30 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:pclk may have excessive skew because
0 CLK pins and 2 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:i_compressor/done_input may have excessive skew because
1 CLK pins and 4 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:i_sensorpads/fifo_clkin may have excessive skew because
1 CLK pins and 0 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:compressor_eot may have excessive skew because
1 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:i_sensortrig/done may have excessive skew because
1 CLK pins and 2 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:i_compressor/done_compress may have excessive skew because
1 CLK pins and 2 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:i_sensortrig/vacts_out may have excessive skew because
1 CLK pins and 15 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:trig_irq may have excessive skew because
1 CLK pins and 8 NON_CLK pins failed to route using a CLK template.
Total REAL time to Router completion: 2 mins 30 secs
Total CPU time to Router completion: 2 mins 29 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| xclk | BUFGMUX_X3Y4| No | 1842 | 0.207 | 0.289 |
+---------------------+--------------+------+------+------------+-------------+
| sclk0 | BUFGMUX_X2Y10| No | 2384 | 0.344 | 0.514 |
+---------------------+--------------+------+------+------------+-------------+
| pclk | BUFGMUX_X1Y11| No | 694 | 0.193 | 0.365 |
+---------------------+--------------+------+------+------------+-------------+
|i_sensorpads/i_senso | | | | | |
| r_phase/gclk_idata | BUFGMUX_X1Y0| No | 77 | 0.172 | 0.374 |
+---------------------+--------------+------+------+------------+-------------+
| pclk2x | BUFGMUX_X3Y9| No | 107 | 0.103 | 0.191 |
+---------------------+--------------+------+------+------------+-------------+
| i_sysinterface/cwr | BUFGMUX_X2Y1| No | 51 | 0.196 | 0.377 |
+---------------------+--------------+------+------+------------+-------------+
| sclk270 | BUFGMUX_X2Y11| No | 62 | 0.170 | 0.373 |
+---------------------+--------------+------+------+------------+-------------+
| i_dma_fifo1/swclk | BUFGMUX_X0Y9| No | 7 | 0.191 | 0.284 |
+---------------------+--------------+------+------+------------+-------------+
| i_dma_fifo0/swclk | BUFGMUX_X2Y0| No | 7 | 0.167 | 0.351 |
+---------------------+--------------+------+------+------------+-------------+
|i_compressor/go_sing | | | | | |
| le | Local| | 31 | 0.000 | 3.431 |
+---------------------+--------------+------+------+------------+-------------+
|i_sensortrig/vacts_o | | | | | |
| ut | Local| | 18 | 2.184 | 4.099 |
+---------------------+--------------+------+------+------------+-------------+
| i_irq_smart/irq | Local| | 1 | 0.000 | 1.950 |
+---------------------+--------------+------+------+------------+-------------+
| trig_irq | Local| | 9 | 0.000 | 2.698 |
+---------------------+--------------+------+------+------------+-------------+
|i_compressor/done_in | | | | | |
| put | Local| | 5 | 0.000 | 2.212 |
+---------------------+--------------+------+------+------------+-------------+
| i_sensortrig/done | Local| | 3 | 0.000 | 3.259 |
+---------------------+--------------+------+------+------------+-------------+
|i_sensorpads/fifo_cl | | | | | |
| kin | Local| | 4 | 0.050 | 1.954 |
+---------------------+--------------+------+------+------------+-------------+
|i_compressor/done_co | | | | | |
| mpress | Local| | 3 | 0.000 | 1.078 |
+---------------------+--------------+------+------+------------+-------------+
|i_sensortrig/xfer_ov | | | | | |
| er_irq | Local| | 1 | 0.000 | 2.040 |
+---------------------+--------------+------+------+------------+-------------+
|cb_xt_pol_virt_trig_ | | | | | |
| MUX_728_o | Local| | 1 | 0.000 | 2.442 |
+---------------------+--------------+------+------+------------+-------------+
| compressor_eot | Local| | 2 | 0.000 | 1.263 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 5652 (Setup: 5652, Hold: 0, Component Switching Limit: 0)
WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in
your design.
Review the timing report using Timing Analyzer (In ISE select "Post-Place &
Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint.
Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to
ensure the best options are set in the tools for timing closure.
Increase the PAR Effort Level setting to "high"
Use the Xilinx "SmartXplorer" script to try special combinations of
options known to produce very good results.
Visit the Xilinx technical support web at http://support.xilinx.com and go to
either "Troubleshoot->Tech Tips->Timing & Constraints" or "
TechXclusives->Timing Closure" for tips and suggestions for meeting timing
in your design.
Number of Timing Constraints that were not applied: 4
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
* TS_i_iclockios_isclk0 = PERIOD TIMEGRP "i | SETUP | -1.165ns| 8.265ns| 7| 3419
_iclockios_isclk0" TS_CLK0 HIGH 50% | HOLD | 0.676ns| | 0| 0
----------------------------------------------------------------------------------------------------------
* TS_HUFFLATCHESI = MAXDELAY FROM TIMEGRP " | SETUP | -0.225ns| 4.573ns| 2| 385
TG_HUFFFFS" TO TIMEGRP "TG_HUFFLA | | | | |
TCHES" TS_CLK0 * 0.6125 | | | | |
----------------------------------------------------------------------------------------------------------
* TS_i_sensorpads_pclk2xi = PERIOD TIMEGRP | SETUP | -0.140ns| 5.340ns| 18| 1848
"i_sensorpads_pclk2xi" TS_CLK1 / 2 | HOLD | 0.756ns| | 0| 0
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_CLK1 = PERIOD TIMEGRP "CLK1" 10.4 ns H | SETUP | 0.051ns| 10.349ns| 0| 0
IGH 50% | HOLD | 0.674ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_HUFFLATCHES = MAXDELAY FROM TIMEGRP "T | SETUP | 0.121ns| 4.316ns| 0| 0
G_HUFFLATCHES" TO TIMEGRP "TG_HUF | | | | |
FFFS" TS_CLK0 * 0.625 | | | | |
----------------------------------------------------------------------------------------------------------
TS_AXIS_READ = MAXDELAY FROM TIMEGRP "CPU | MAXDELAY | 0.123ns| 16.877ns| 0| 0
_ADDRCE" TO TIMEGRP "CPU_DATA" 17 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_i_iclockios_isclk270 = PERIOD TIMEGRP | SETUP | 0.180ns| 6.860ns| 0| 0
"i_iclockios_isclk270" TS_CLK0 PHASE | HOLD | 1.325ns| | 0| 0
5.325 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_i_sensorpads_i_sensor_phase_dcm2x180 = | SETUP | 0.186ns| 5.014ns| 0| 0
PERIOD TIMEGRP "i_sensorpads_i_s | HOLD | 1.046ns| | 0| 0
ensor_phase_dcm2x180" TS_CLK1 / 2 PHASE 2 | | | | |
.6 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_OE_TO_DATA = MAXDELAY FROM TIMEGRP "OE | MAXDELAY | 0.186ns| 11.814ns| 0| 0
" TO TIMEGRP "CPU_DATA" 12 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_HUFFRAMS = MAXDELAY FROM TIMEGRP "TG_H | SETUP | 0.241ns| 5.793ns| 0| 0
UFFRAMS" TO TIMEGRP "TG_HUFFLATCHES" | | | | |
TS_CLK0 * 0.85 | | | | |
----------------------------------------------------------------------------------------------------------
TS_DOUBLECYCS3 = MAXDELAY FROM TIMEGRP "T | SETUP | 0.321ns| 13.879ns| 0| 0
G_SLOW_SRC3" TO TIMEGRP "TG_DOUBL | | | | |
EDEST3" TS_CLK0 * 2 | | | | |
----------------------------------------------------------------------------------------------------------
TS_WE = MAXDELAY FROM TIMEGRP "WE" TO TIM | MAXDELAY | 0.519ns| 10.981ns| 0| 0
EGRP "TNM_CWR" 11.5 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_DACK0 = MAXDELAY FROM TIMEGRP "DACK" T | MAXDELAY | 0.937ns| 16.063ns| 0| 0
O TIMEGRP "ALLPADS" 17 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_HUFFRAMSA = MAXDELAY FROM TIMEGRP "TG_ | SETUP | 1.945ns| 4.178ns| 0| 0
HUFFLATCHES" TO TIMEGRP "TG_HUFFRAMS" | | | | |
TS_CLK0 * 0.8625 | | | | |
----------------------------------------------------------------------------------------------------------
TS_i_sensorpads_i_sensor_phase_dcm2x = PE | MINLOWPULSE | 2.008ns| 3.192ns| 0| 0
RIOD TIMEGRP "i_sensorpads_i_sens | | | | |
or_phase_dcm2x" TS_CLK1 / 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_CLK0 = PERIOD TIMEGRP "CLK0" 7.1 ns HI | MINLOWPULSE | 2.300ns| 4.800ns| 0| 0
GH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_HIST_DOUBLECYC2 = MAXDELAY FROM TIMEGR | SETUP | 3.411ns| 6.989ns| 0| 0
P "TG_HIST_DOUBLE2_SRC" TO TIMEGRP | | | | |
"TG_HIST_DOUBLE2_DST" TS_CLK1 | | | | |
----------------------------------------------------------------------------------------------------------
TS_DOUBLECYC_IDATA = MAXDELAY FROM TIMEGR | SETUP | 5.493ns| 4.907ns| 0| 0
P "TNM_EN_IDATA" TO TIMEGRP "TNM_ | | | | |
EN_IDATA" TS_CLK1 | | | | |
----------------------------------------------------------------------------------------------------------
TS_DOUBLECYCS2 = MAXDELAY FROM TIMEGRP "T | SETUP | 5.987ns| 8.213ns| 0| 0
G_DOUBLECYCS2" TO TIMEGRP "TG_ALL | | | | |
_SYNC" TS_CLK0 * 2 | | | | |
----------------------------------------------------------------------------------------------------------
TS_WR_DATA = MAXDELAY FROM TIMEGRP "CPU_D | SETUP | 6.460ns| 2.540ns| 0| 0
ATA" TO TIMEGRP "TG_CWRDEST" 9 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_i_sensorpads_i_sensor_phase_pre_pre_en | MINPERIOD | 8.748ns| 1.652ns| 0| 0
_idata = PERIOD TIMEGRP "i_sensor | | | | |
pads_i_sensor_phase_pre_pre_en_idata" TS_ | | | | |
CLK1 PHASE 2.6 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_i_sensorpads_i_sensor_phase_pre_pre_en | MINPERIOD | 8.748ns| 1.652ns| 0| 0
_idata90 = PERIOD TIMEGRP "i_sens | | | | |
orpads_i_sensor_phase_pre_pre_en_idata90" | | | | |
TS_CLK1 PHASE 5.2 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
PATH "TS_PCLK_PCLK2X_path" TIG | SETUP | N/A| 4.840ns| N/A| 0
----------------------------------------------------------------------------------------------------------
PATH "TS_GCLK_IDATA_PCLK_path" TIG | SETUP | N/A| 14.944ns| N/A| 0
----------------------------------------------------------------------------------------------------------
PATH "TS_PCLK_GCLK_IDATA_path" TIG | SETUP | N/A| 5.796ns| N/A| 0
----------------------------------------------------------------------------------------------------------
Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_CLK0
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_CLK0 | 7.100ns| 4.800ns| 8.265ns| 0| 9| 0| 34422|
| TS_DOUBLECYCS2 | 14.200ns| 8.213ns| N/A| 0| 0| 457| 0|
| TS_DOUBLECYCS3 | 14.200ns| 13.879ns| N/A| 0| 0| 9051| 0|
| TS_HUFFRAMS | 6.035ns| 5.793ns| N/A| 0| 0| 36| 0|
| TS_HUFFLATCHES | 4.438ns| 4.316ns| N/A| 0| 0| 109| 0|
| TS_HUFFRAMSA | 6.124ns| 4.178ns| N/A| 0| 0| 21| 0|
| TS_HUFFLATCHESI | 4.349ns| 4.573ns| N/A| 2| 0| 105| 0|
| TS_i_iclockios_isclk0 | 7.100ns| 8.265ns| N/A| 7| 0| 24555| 0|
| TS_i_iclockios_isclk270 | 7.100ns| 6.860ns| N/A| 0| 0| 88| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_CLK1
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_CLK1 | 10.400ns| 10.349ns| 10.680ns| 0| 18| 66829| 1872|
| TS_DOUBLECYC_IDATA | 10.400ns| 4.907ns| N/A| 0| 0| 242| 0|
| TS_HIST_DOUBLECYC2 | 10.400ns| 6.989ns| N/A| 0| 0| 117| 0|
| TS_i_sensorpads_pclk2xi | 5.200ns| 5.340ns| N/A| 18| 0| 1393| 0|
| TS_i_sensorpads_i_sensor_phase| 10.400ns| 1.652ns| N/A| 0| 0| 0| 0|
| _pre_pre_en_idata | | | | | | | |
| TS_i_sensorpads_i_sensor_phase| 10.400ns| 1.652ns| N/A| 0| 0| 0| 0|
| _pre_pre_en_idata90 | | | | | | | |
| TS_i_sensorpads_i_sensor_phase| 5.200ns| 3.192ns| N/A| 0| 0| 0| 0|
| _dcm2x | | | | | | | |
| TS_i_sensorpads_i_sensor_phase| 5.200ns| 5.014ns| N/A| 0| 0| 120| 0|
| _dcm2x180 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
3 constraints not met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 2 mins 31 secs
Total CPU time to PAR completion: 2 mins 31 secs
Peak Memory Usage: 786 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - 27 errors found.
Number of error messages: 0
Number of warning messages: 11
Number of info messages: 1
Writing design to file x353.ncd
PAR done!
ISE_14_7_results/x353_map.xrpt 0 → 100644
View file @ f5c2e000
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="lin64" product="ISE" version="14.7">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Map" timeStamp="Tue Jul 28 15:40:41 2015">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="PATH"/>
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE/"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="LD_LIBRARY_PATH"/>
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Ubuntu"/>
<item stringID="User_EnvOsrelease" value="Ubuntu 14.04.1 LTS"/>
</item>
<item stringID="User_EnvHost" value="elphel-desktop"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value="Intel(R) Core(TM) i7-4771 CPU @ 3.50GHz"/>
<item stringID="speed" value="800.000 MHz"/>
</row>
</table>
</section>
<section stringID="MAP_OPTION_SUMMARY">
<item DEFAULT="OFF" label="-ir" stringID="MAP_IGNORERLOCS" value="OFF"/>
<item DEFAULT="area" label="-cm" stringID="MAP_COVER_MODE" value="speed"/>
<item DEFAULT="None" label="-o" stringID="MAP_OUTFILE" value="x353.ncd"/>
<item DEFAULT="false" label="-w" stringID="MAP_OVERWRITE_OUTPUT" value="true"/>
<item DEFAULT="None" label="-p" stringID="MAP_PARTNAME" value="xc3s1200eft256-4"/>
</section>
<task stringID="MAP_PACK_REPORT">
<section stringID="MAP_DESIGN_INFORMATION">
<item stringID="MAP_PART" value="3s1200eft256-4"/>
<item stringID="MAP_DEVICE" value="xc3s1200e"/>
<item stringID="MAP_ARCHITECTURE" value="spartan3e"/>
<item stringID="MAP_PACKAGE" value="ft256"/>
<item stringID="MAP_SPEED" value="-4"/>
</section>
<section stringID="MAP_DESIGN_SUMMARY">
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
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<item stringID="MAP_TOTAL_CPU_TIME" value="9 secs "/>
</section>
<section stringID="MAP_SLICE_REPORTING">
<item AVAILABLE="17344" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="7573">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="7515"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="58"/>
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<item dataType="int" label="Number of route-thrus" stringID="MAP_NUM_LUT_RT" value="491"/>
<item dataType="int" stringID="MAP_NUM_RAM16" value="13"/>
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<item dataType="int" label="Number used as Shift registers" stringID="MAP_NUM_SHIFT" value="280"/>
</item>
<item AVAILABLE="8672" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="6969">
<item dataType="int" label="Number of Slices containing unrelated logic" stringID="MAP_NUM_SLICE_UNRELATED" value="0"/>
</item>
</section>
<section stringID="MAP_IOB_REPORTING">
<section stringID="MAP_IOB_DATA">
<item AVAILABLE="190" dataType="int" stringID="MAP_AGG_BONDED_IO" value="142"/>
<item dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="66"/>
<item dataType="int" stringID="MAP_NUM_IOB_LATCH" value="9"/>
</section>
</section>
<section stringID="MAP_HARD_IP_REPORTING">
<item AVAILABLE="28" dataType="int" stringID="MAP_NUM_RAMB16" value="22"/>
<item AVAILABLE="24" dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="9"/>
<item AVAILABLE="8" dataType="int" stringID="MAP_NUM_DCM" value="4"/>
<item AVAILABLE="28" dataType="int" stringID="MAP_NUM_MULT18X18SIO" value="19"/>
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<section stringID="MAP_MACRO_RPM_REPORTING">
<item dataType="int" stringID="MAP_HARD_MACROS" value="0"/>
<item dataType="int" stringID="MAP_RPMS" value="0"/>
</section>
<section stringID="MAP_IOB_PROPERTIES">
<table stringID="MAP_IOB_TABLE">
<column label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME"/>
<column stringID="Type"/>
<column stringID="Direction"/>
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ISE_14_7_results/x353_ngdbuild.xrpt 0 → 100644
View file @ f5c2e000
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="lin64" product="ISE" version="14.7">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Tue Jul 28 15:29:49 2015">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="PATH"/>
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games"/>
</row>
<row stringID="row" value="1">
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<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE/"/>
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</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Ubuntu"/>
<item stringID="User_EnvOsrelease" value="Ubuntu 14.04.1 LTS"/>
</item>
<item stringID="User_EnvHost" value="elphel-desktop"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value="Intel(R) Core(TM) i7-4771 CPU @ 3.50GHz"/>
<item stringID="speed" value="800.000 MHz"/>
</row>
</table>
</section>
<task stringID="NGDBUILD_OPTION_SUMMARY">
<section stringID="NGDBUILD_OPTION_SUMMARY">
<item DEFAULT="None" label="-p" stringID="NGDBUILD_partname" value="xc3s1200eft256-4"/>
</section>
</task>
<task stringID="NGDBUILD_REPORT">
<section stringID="NGDBUILD_DESIGN_SUMMARY">
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<item dataType="int" stringID="NGDBUILD_NUM_RAMB16_S18_S18" value="6"/>
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</document>
ISE_14_7_results/x353_pad.csv 0 → 100644
View file @ f5c2e000
#Release 14.7 - reportgen P.20131013 (lin64)
#Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
#Tue Jul 28 15:45:48 2015
#
## NOTE: This file is designed to be imported into a spreadsheet program
# such as Microsoft Excel for viewing, printing and sorting. The |
# character is used as the data field separator. This file is also designed
# to support parsing.
#
#INPUT FILE: x353.ncd
#OUTPUT FILE: x353_pad.csv
#PART TYPE: xc3s1200e
#SPEED GRADE: -4
#PACKAGE: ft256
#
# Pinout by Pin Number:
#
# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,IO Register,Signal Integrity,
A1,,,GND,,,,,,,,,,,,
A2,,,TDI,,,,,,,,,,,,
A3,,IBUF,IP,UNUSED,,0,,,,,,,,,
A4,EXT<2>,IOB,IO_L17N_0/VREF_0,BIDIR,LVCMOS33,0,12,SLOW,NONE**,NONE,,LOCATED,NO,NONE,
A5,EXT<3>,IOB,IO_L17P_0,BIDIR,LVCMOS33,0,12,SLOW,NONE**,NONE,,LOCATED,NO,NONE,
A6,,,VCCAUX,,,,,,,,2.5,,,,
A7,D<16>,IOB,IO,BIDIR,LVCMOS33,0,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
A8,CLK3,IBUF,IP_L10P_0/GCLK8,INPUT,LVCMOS33,0,,,,IFD,,LOCATED,YES,NONE,
A9,CLK0,IBUF,IO_L09N_0/GCLK7,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE,
A10,CLK1,IBUF,IO_L09P_0/GCLK6,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE,
A11,,,VCCAUX,,,,,,,,2.5,,,,
A12,D<15>,IOB,IO,BIDIR,LVCMOS33,0,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
A13,D<11>,IOB,IO_L03N_0/VREF_0,BIDIR,LVCMOS33,0,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
A14,DACK1,IBUF,IO_L01N_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE,
A15,,,TCK,,,,,,,,,,,,
A16,,,GND,,,,,,,,,,,,
B1,CNVSYNC,IOB,IO_L01P_3,BIDIR,LVCMOS25*,3,4,SLOW,NONE**,IFD,,LOCATED,YES,NONE,
B2,CNVCLK,IOB,IO_L01N_3,BIDIR,LVCMOS25*,3,4,SLOW,NONE**,IFD,,LOCATED,YES,NONE,
B3,,DIFFS,IO_L19N_0/HSWAP,UNUSED,,0,,,,,,,,,
B4,D<19>,IOB,IO,BIDIR,LVCMOS33,0,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
B5,,,VCCO_0,,,0,,,,,3.30,,,,
B6,D<23>,IOB,IO,BIDIR,LVCMOS33,0,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
B7,EXT<7>,IOB,IO_L13P_0,BIDIR,LVCMOS33,0,12,SLOW,NONE**,NONE,,LOCATED,NO,NONE,
B8,,DIFFSI,IP_L10N_0/GCLK9,UNUSED,,0,,,,,,,,,
B9,,,GND,,,,,,,,,,,,
B10,D<14>,IOB,IO,BIDIR,LVCMOS33,0,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
B11,D<12>,IOB,IO_L05N_0/VREF_0,BIDIR,LVCMOS33,0,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
B12,,,VCCO_0,,,0,,,,,3.30,,,,
B13,BROUT,IOB,IO_L03P_0,OUTPUT,LVCMOS33,0,4,SLOW,NONE**,,,LOCATED,NO,NONE,
B14,DACK0,IBUF,IO_L01P_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE,
B15,,,TMS,,,,,,,,,,,,
B16,BRIN,IBUF,IP,INPUT,LVCMOS33,1,,,,NONE,,LOCATED,NO,NONE,
C1,ARO,IOB,IO_L02P_3,OUTPUT,LVCMOS25*,3,4,SLOW,NONE**,,,LOCATED,NO,NONE,
C2,,DIFFS,IO_L02N_3/VREF_3, ,,3,,,,,1.25,,,,
C3,D<21>,IOB,IO_L19P_0,BIDIR,LVCMOS33,0,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
C4,EXT<0>,IOB,IO_L18N_0,BIDIR,LVCMOS33,0,12,SLOW,NONE**,NONE,,LOCATED,NO,NONE,
C5,EXT<1>,IOB,IO_L18P_0,BIDIR,LVCMOS33,0,12,SLOW,NONE**,NONE,,LOCATED,NO,NONE,
C6,EXT<5>,IOB,IO_L15P_0,BIDIR,LVCMOS33,0,12,SLOW,NONE**,NONE,,LOCATED,NO,NONE,
C7,EXT<6>,IOB,IO_L13N_0,BIDIR,LVCMOS33,0,12,SLOW,NONE**,NONE,,LOCATED,NO,NONE,
C8,D<30>,IOB,IO_L11P_0/GCLK10,BIDIR,LVCMOS33,0,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
C9,,DIFFSI,IP_L07N_0,UNUSED,,0,,,,,,,,,
C10,,DIFFMI,IP_L07P_0,UNUSED,,0,,,,,,,,,
C11,D<10>,IOB,IO_L05P_0,BIDIR,LVCMOS33,0,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
C12,,DIFFSI,IP_L02N_0,UNUSED,,0,,,,,,,,,
C13,,IBUF,IP,UNUSED,,0,,,,,,,,,
C14,,,TDO,,,,,,,,,,,,
C15,DREQ0,IOB,IO_L19N_1/LDC2,OUTPUT,LVCMOS33,1,4,SLOW,NONE**,,,LOCATED,YES,NONE,
C16,SYS_BUSEN,IOB,IO_L19P_1/LDC1,OUTPUT,LVCMOS33,1,4,SLOW,NONE**,,,LOCATED,NO,NONE,
D1,SENSPGM,IOB,IO_L05P_3,BIDIR,LVCMOS25*,3,12,SLOW,PULLUP,NONE,,LOCATED,NO,NONE,
D2,,IBUF,IP,UNUSED,,3,,,,,,,,,
D3,,,PROG_B,,,,,,,,,,,,
D4,,,VCCINT,,,,,,,,1.2,,,,
D5,,DIFFMI,IP_L16P_0,UNUSED,,0,,,,,,,,,
D6,EXT<4>,IOB,IO_L15N_0,BIDIR,LVCMOS33,0,12,SLOW,NONE**,NONE,,LOCATED,NO,NONE,
D7,EXT<9>,IOB,IO_L14N_0/VREF_0,BIDIR,LVCMOS33,0,12,SLOW,NONE**,NONE,,LOCATED,NO,NONE,
D8,D<31>,IOB,IO_L11N_0/GCLK11,BIDIR,LVCMOS33,0,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
D9,D<13>,IOB,IO/VREF_0,BIDIR,LVCMOS33,0,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
D10,DREQ1,IOB,IO_L06P_0,OUTPUT,LVCMOS33,0,4,SLOW,NONE**,,,LOCATED,YES,NONE,
D11,BG,IOB,IO_L04P_0,TRISTATE,LVCMOS33,0,12,SLOW,NONE**,,,LOCATED,NO,NONE,
D12,,DIFFMI,IP_L02P_0,UNUSED,,0,,,,,,,,,
D13,,,VCCINT,,,,,,,,1.2,,,,
D14,A<0>,IBUF,IO_L18N_1/LDC0,INPUT,LVCMOS33,1,,,,NONE,,LOCATED,YES,NONE,
D15,IRQ,IOB,IO_L18P_1/HDC,OUTPUT,LVCMOS33,1,8,SLOW,NONE**,,,LOCATED,NO,NONE,
D16,CE,IBUF,IP/VREF_1,INPUT,LVCMOS33,1,,,,NONE,,LOCATED,NO,NONE,
E1,ARST,IOB,IO_L05N_3,OUTPUT,LVCMOS25*,3,4,SLOW,NONE**,,,LOCATED,NO,NONE,
E2,,,VCCO_3,,,3,,,,,2.50,,,,
E3,MRST,IOB,IO_L03P_3,BIDIR,LVCMOS25*,3,4,SLOW,PULLUP,NONE,,LOCATED,NO,NONE,
E4,SDA0,IOB,IO_L03N_3,BIDIR,LVCMOS25*,3,12,SLOW,NONE**,NONE,,LOCATED,NO,NONE,
E5,,,VCCINT,,,,,,,,1.2,,,,
E6,,DIFFSI,IP_L16N_0,UNUSED,,0,,,,,,,,,
E7,EXT<8>,IOB,IO_L14P_0,BIDIR,LVCMOS33,0,12,SLOW,NONE**,NONE,,LOCATED,NO,NONE,
E8,EXT<11>,IOB,IO_L12P_0,BIDIR,LVCMOS33,0,12,SLOW,NONE**,NONE,,LOCATED,NO,NONE,
E9,D<18>,IOB,IO_L08P_0/GCLK4,BIDIR,LVCMOS33,0,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
E10,D<25>,IOB,IO_L06N_0,BIDIR,LVCMOS33,0,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
E11,A<3>,IBUF,IO_L04N_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,YES,NONE,
E12,,,VCCINT,,,,,,,,1.2,,,,
E13,A<4>,IBUF,IO_L17P_1,INPUT,LVCMOS33,1,,,,NONE,,LOCATED,YES,NONE,
E14,CE1,IBUF,IP,INPUT,LVCMOS33,1,,,,NONE,,LOCATED,NO,NONE,
E15,,,VCCO_1,,,1,,,,,3.30,,,,
E16,A<5>,IBUF,IO_L17N_1,INPUT,LVCMOS33,1,,,,NONE,,LOCATED,YES,NONE,
F1,,,VCCAUX,,,,,,,,2.5,,,,
F2,,IBUF,IP,UNUSED,,3,,,,,,,,,
F3,,DIFFM,IO_L04P_3,UNUSED,,3,,,,,,,,,
F4,,DIFFS,IO_L04N_3/VREF_3, ,,3,,,,,1.25,,,,
F5,,IBUF,IP,UNUSED,,3,,,,,,,,,
F6,,,GND,,,,,,,,,,,,
F7,,,VCCO_0,,,0,,,,,3.30,,,,
F8,EXT<10>,IOB,IO_L12N_0,BIDIR,LVCMOS33,0,12,SLOW,NONE**,NONE,,LOCATED,NO,NONE,
F9,D<20>,IOB,IO_L08N_0/GCLK5,BIDIR,LVCMOS33,0,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
F10,,,VCCO_0,,,0,,,,,3.30,,,,
F11,,,GND,,,,,,,,,,,,
F12,A<2>,IBUF,IO_L16N_1,INPUT,LVCMOS33,1,,,,NONE,,LOCATED,YES,NONE,
F13,A<1>,IBUF,IO_L16P_1,INPUT,LVCMOS33,1,,,,NONE,,LOCATED,YES,NONE,
F14,A<6>,IBUF,IO_L15P_1,INPUT,LVCMOS33,1,,,,NONE,,LOCATED,YES,NONE,
F15,A<7>,IBUF,IO_L15N_1,INPUT,LVCMOS33,1,,,,NONE,,LOCATED,YES,NONE,
F16,,,VCCAUX,,,,,,,,2.5,,,,
G1,,IBUF,IP/VREF_3, ,,3,,,,,1.25,,,,
G2,SCL0,IOB,IO_L07N_3,BIDIR,LVCMOS25*,3,12,SLOW,PULLUP,NONE,,LOCATED,NO,NONE,
G3,PXD<8>,IBUF,IO_L07P_3,INPUT,LVCMOS25*,3,,,,IFD,,LOCATED,YES,NONE,
G4,PXD<7>,IBUF,IO_L06N_3,INPUT,LVCMOS25*,3,,,,IFD,,LOCATED,YES,NONE,
G5,PXD<5>,IBUF,IO_L06P_3,INPUT,LVCMOS25*,3,,,,IFD,,LOCATED,YES,NONE,
G6,,,VCCO_3,,,3,,,,,2.50,,,,
G7,,,GND,,,,,,,,,,,,
G8,,,GND,,,,,,,,,,,,
G9,,,GND,,,,,,,,,,,,
G10,,,GND,,,,,,,,,,,,
G11,,,VCCO_1,,,1,,,,,3.30,,,,
G12,,IBUF,IP,UNUSED,,1,,,,,,,,,
G13,,DIFFM,IO_L14P_1,UNUSED,,1,,,,,,,,,
G14,,DIFFS,IO_L14N_1/A0,UNUSED,,1,,,,,,,,,
G15,,DIFFM,IO_L13P_1/A2,UNUSED,,1,,,,,,,,,
G16,,DIFFS,IO_L13N_1/A1,UNUSED,,1,,,,,,,,,
H1,,IBUF,IP,UNUSED,,3,,,,,,,,,
H2,,,GND,,,,,,,,,,,,
H3,PXD<9>,IBUF,IO_L09P_3/LHCLK2,INPUT,LVCMOS25*,3,,,,IFD,,LOCATED,YES,NONE,
H4,PXD<6>,IBUF,IO_L09N_3/LHCLK3/IRDY2,INPUT,LVCMOS25*,3,,,,IFD,,LOCATED,YES,NONE,
H5,PXD<3>,IBUF,IO_L08P_3/LHCLK0,INPUT,LVCMOS25*,3,,,,IFD,,LOCATED,YES,NONE,
H6,PXD<1>,IBUF,IO_L08N_3/LHCLK1,INPUT,LVCMOS25*,3,,,,IFD,,LOCATED,YES,NONE,
H7,,,GND,,,,,,,,,,,,
H8,,,GND,,,,,,,,,,,,
H9,,,GND,,,,,,,,,,,,
H10,,,GND,,,,,,,,,,,,
H11,D<22>,IOB,IO_L12N_1/A3/RHCLK7,BIDIR,LVCMOS33,1,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
H12,,DIFFM,IO_L12P_1/A4/RHCLK6,UNUSED,,1,,,,,,,,,
H13,,IBUF,IP/VREF_1,UNUSED,,1,,,,,,,,,
H14,BA<0>,IOB,IO_L11N_1/A5/RHCLK5,TRISTATE,LVCMOS33,1,12,SLOW,NONE**,,,LOCATED,NO,NONE,
H15,BA<1>,IOB,IO_L11P_1/A6/RHCLK4/IRDY1,TRISTATE,LVCMOS33,1,12,SLOW,NONE**,,,LOCATED,NO,NONE,
H16,,IBUF,IP,UNUSED,,1,,,,,,,,,
J1,PXD<4>,IBUF,IO_L12P_3,INPUT,LVCMOS25*,3,,,,IFD,,LOCATED,YES,NONE,
J2,PXD<2>,IBUF,IO_L10P_3/LHCLK4/TRDY2,INPUT,LVCMOS25*,3,,,,IFD,,LOCATED,YES,NONE,
J3,PXD<0>,IBUF,IO_L10N_3/LHCLK5,INPUT,LVCMOS25*,3,,,,IFD,,LOCATED,YES,NONE,
J4,DUMMYVFEF,IOB,IO_L11N_3/LHCLK7,BIDIR,SSTL2_I,3,,,NONE**,NONE,,LOCATED,NO,NONE,
J5,HACT,IBUF,IO_L11P_3/LHCLK6,INPUT,LVCMOS25*,3,,,,IFD,,LOCATED,YES,NONE,
J6,ALWAYS0,IBUF,IP,INPUT,LVCMOS25*,3,,,PULLDOWN,NONE,,LOCATED,NO,NONE,
J7,,,GND,,,,,,,,,,,,
J8,,,GND,,,,,,,,,,,,
J9,,,GND,,,,,,,,,,,,
J10,,,GND,,,,,,,,,,,,
J11,,IBUF,IP,UNUSED,,1,,,,,,,,,
J12,SYS_SDCLKI,IBUF,IP,INPUT,LVCMOS33,1,,,,NONE,,LOCATED,NO,NONE,
J13,SYS_SDWE,IOB,IO_L10N_1/A7/RHCLK3/TRDY1,TRISTATE,LVCMOS33,1,12,SLOW,NONE**,,,LOCATED,NO,NONE,
J14,SYS_SDCLK,IOB,IO_L10P_1/A8/RHCLK2,TRISTATE,LVCMOS33,1,12,SLOW,NONE**,,,LOCATED,NO,NONE,
J15,,,GND,,,,,,,,,,,,
J16,SYS_SDCAS,IOB,IO_L09N_1/A9/RHCLK1,TRISTATE,LVCMOS33,1,12,SLOW,NONE**,,,LOCATED,NO,NONE,
K1,VACT,IBUF,IO_L12N_3,INPUT,LVCMOS25*,3,,,,IFD,,LOCATED,YES,NONE,
K2,SDA<3>,IOB,IO_L13P_3,OUTPUT,SSTL2_I,3,,,NONE**,,,LOCATED,YES,NONE,
K3,SDA<1>,IOB,IO_L13N_3,OUTPUT,SSTL2_I,3,,,NONE**,,,LOCATED,YES,NONE,
K4,,IBUF,IP,UNUSED,,3,,,,,,,,,
K5,BPF,IBUF,IO_L15P_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
K6,,,VCCO_3,,,3,,,,,2.50,,,,
K7,,,GND,,,,,,,,,,,,
K8,,,GND,,,,,,,,,,,,
K9,,,GND,,,,,,,,,,,,
K10,,,GND,,,,,,,,,,,,
K11,,,VCCO_1,,,1,,,,,3.30,,,,
K12,D<17>,IOB,IO_L07N_1/A11,BIDIR,LVCMOS33,1,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
K13,D<29>,IOB,IO_L07P_1/A12,BIDIR,LVCMOS33,1,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
K14,D<24>,IOB,IO_L08N_1/VREF_1,BIDIR,LVCMOS33,1,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
K15,D<26>,IOB,IO_L08P_1,BIDIR,LVCMOS33,1,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
K16,SYS_SDRAS,IOB,IO_L09P_1/A10/RHCLK0,TRISTATE,LVCMOS33,1,12,SLOW,NONE**,,,LOCATED,NO,NONE,
L1,,,VCCAUX,,,,,,,,2.5,,,,
L2,,DIFFS,IO_L14N_3/VREF_3, ,,3,,,,,1.25,,,,
L3,DCLK,IOB,IO_L14P_3,BIDIR,LVCMOS25*,3,4,SLOW,NONE**,IFD,,LOCATED,YES,NONE,
L4,SDA<14>,IOB,IO_L17N_3,OUTPUT,SSTL2_I,3,,,NONE**,,,LOCATED,YES,NONE,
L5,,DIFFS,IO_L15N_3,UNUSED,,3,,,,,,,,,
L6,,,GND,,,,,,,,,,,,
L7,,,VCCO_2,,,2,,,,,2.50,,,,
L8,SDD<7>,IOB,IO_L09N_2/D6/GCLK13,BIDIR,SSTL2_I,2,,,NONE**,NONE,,LOCATED,YES,NONE,
L9,,DIFFM,IO_L13P_2/M0,UNUSED,,2,,,,,,,,,
L10,,,VCCO_2,,,2,,,,,2.50,,,,
L11,,,GND,,,,,,,,,,,,
L12,D<9>,IOB,IO_L05P_1,BIDIR,LVCMOS33,1,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
L13,D<3>,IOB,IO_L05N_1,BIDIR,LVCMOS33,1,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
L14,D<27>,IOB,IO_L06P_1,BIDIR,LVCMOS33,1,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
L15,D<28>,IOB,IO_L06N_1,BIDIR,LVCMOS33,1,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
L16,,,VCCAUX,,,,,,,,2.5,,,,
M1,SDA<2>,IOB,IO_L16P_3,OUTPUT,SSTL2_I,3,,,NONE**,,,LOCATED,YES,NONE,
M2,,,VCCO_3,,,3,,,,,2.50,,,,
M3,,IBUF,IP,UNUSED,,3,,,,,,,,,
M4,SDA<5>,IOB,IO_L17P_3,OUTPUT,SSTL2_I,3,,,NONE**,,,LOCATED,YES,NONE,
M5,,,VCCINT,,,,,,,,1.2,,,,
M6,SDRAS,IOB,IO_L05P_2,OUTPUT,SSTL2_I,2,,,NONE**,,,LOCATED,YES,NONE,
M7,SDWE,IOB,IO,OUTPUT,SSTL2_I,2,,,NONE**,,,LOCATED,YES,NONE,
M8,SDLDM,IOB,IO_L09P_2/D7/GCLK12,OUTPUT,SSTL2_I,2,,,NONE**,,,LOCATED,YES,NONE,
M9,SDD<6>,IOB,IO_L13N_2/DIN/D0,BIDIR,SSTL2_I,2,,,NONE**,NONE,,LOCATED,YES,NONE,
M10,SDD<10>,IOB,IO_L15N_2,BIDIR,SSTL2_I,2,,,NONE**,NONE,,LOCATED,YES,NONE,
M11,,DIFFSI,IP_L17N_2,UNUSED,,2,,,,,,,,,
M12,,,VCCINT,,,,,,,,1.2,,,,
M13,WE,IBUF,IP,INPUT,LVCMOS33,1,,,,NONE,,LOCATED,YES,NONE,
M14,OE,IBUF,IP,INPUT,LVCMOS33,1,,,,NONE,,LOCATED,NO,NONE,
M15,,,VCCO_1,,,1,,,,,3.30,,,,
M16,D<0>,IOB,IO_L04N_1/VREF_1,BIDIR,LVCMOS33,1,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
N1,SDA<10>,IOB,IO_L16N_3,OUTPUT,SSTL2_I,3,,,NONE**,,,LOCATED,YES,NONE,
N2,,IBUF,IP/VREF_3, ,,3,,,,,1.25,,,,
N3,,IBUF,IP,UNUSED,,3,,,,,,,,,
N4,,,VCCINT,,,,,,,,1.2,,,,
N5,SDA<8>,IOB,IO_L03N_2/MOSI/CSI_B,OUTPUT,SSTL2_I,2,,,NONE**,,,LOCATED,YES,NONE,
N6,SDCLKE,IOB,IO_L05N_2,OUTPUT,SSTL2_I,2,,,NONE**,,,LOCATED,NO,NONE,
N7,SDCAS,IOB,IO_L07P_2,OUTPUT,SSTL2_I,2,,,NONE**,,,LOCATED,YES,NONE,
N8,LDQS,IOB,IO_L10P_2/D4/GCLK14,BIDIR,SSTL2_I,2,,,NONE**,NONE,,LOCATED,YES,NONE,
N9,SDD<5>,IOB,IO_L12N_2/D1/GCLK3,BIDIR,SSTL2_I,2,,,NONE**,NONE,,LOCATED,YES,NONE,
N10,SDD<3>,IOB,IO_L15P_2,BIDIR,SSTL2_I,2,,,NONE**,NONE,,LOCATED,YES,NONE,
N11,,DIFFMI,IP_L17P_2,UNUSED,,2,,,,,,,,,
N12,SDD<2>,IOB,IO_L18N_2/A20,BIDIR,SSTL2_I,2,,,NONE**,NONE,,LOCATED,YES,NONE,
N13,,,VCCINT,,,,,,,,1.2,,,,
N14,D<5>,IOB,IO_L03P_1,BIDIR,LVCMOS33,1,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
N15,D<1>,IOB,IO_L03N_1/VREF_1,BIDIR,LVCMOS33,1,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
N16,D<2>,IOB,IO_L04P_1,BIDIR,LVCMOS33,1,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
P1,SDA<0>,IOB,IO_L18N_3,OUTPUT,SSTL2_I,3,,,NONE**,,,LOCATED,YES,NONE,
P2,SDA<13>,IOB,IO_L18P_3,OUTPUT,SSTL2_I,3,,,NONE**,,,LOCATED,YES,NONE,
P3,,DIFFM,IO_L01P_2/CSO_B,UNUSED,,2,,,,,,,,,
P4,,DIFFS,IO_L01N_2/INIT_B,UNUSED,,2,,,,,,,,,
P5,SDA<7>,IOB,IO_L03P_2/DOUT/BUSY,OUTPUT,SSTL2_I,2,,,NONE**,,,LOCATED,YES,NONE,
P6,SDA<11>,IOB,IO_L06N_2,OUTPUT,SSTL2_I,2,,,NONE**,,,LOCATED,YES,NONE,
P7,SDA<12>,IOB,IO_L07N_2,OUTPUT,SSTL2_I,2,,,NONE**,,,LOCATED,YES,NONE,
P8,UDQS,IOB,IO_L10N_2/D3/GCLK15,BIDIR,SSTL2_I,2,,,NONE**,NONE,,LOCATED,YES,NONE,
P9,SDD<8>,IOB,IO_L12P_2/D2/GCLK2,BIDIR,SSTL2_I,2,,,NONE**,NONE,,LOCATED,YES,NONE,
P10,SDD<9>,IOB,IO_L14P_2,BIDIR,SSTL2_I,2,,,NONE**,NONE,,LOCATED,YES,NONE,
P11,SDD<11>,IOB,IO_L16N_2/A22,BIDIR,SSTL2_I,2,,,NONE**,NONE,,LOCATED,YES,NONE,
P12,SDD<12>,IOB,IO_L18P_2/A21,BIDIR,SSTL2_I,2,,,NONE**,NONE,,LOCATED,YES,NONE,
P13,,IOB,IO/VREF_2, ,,2,,,,,1.25,,,,
P14,SDD<15>,IOB,IO_L20P_2/VS0/A17,BIDIR,SSTL2_I,2,,,NONE**,NONE,,LOCATED,YES,NONE,
P15,D<7>,IOB,IO_L02N_1/A13,BIDIR,LVCMOS33,1,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
P16,D<4>,IOB,IO_L02P_1/A14,BIDIR,LVCMOS33,1,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
R1,SDNCLK,DIFFS,IO_L19N_3,OUTPUT,DIFF_SSTL2_I,3,,,NONE**,,,LOCATED,NO,NONE,
R2,SDCLK,DIFFM,IO_L19P_3,OUTPUT,DIFF_SSTL2_I,3,,,NONE**,,,LOCATED,NO,NONE,
R3,SDCLK_FB,DIFFSI,IP_L02N_2,INPUT,DIFF_SSTL2_I,2,,,,NONE,,LOCATED,NO,NONE,
R4,,IOB,IO/VREF_2, ,,2,,,,,1.25,,,,
R5,,,VCCO_2,,,2,,,,,2.50,,,,
R6,SDA<9>,IOB,IO_L06P_2,OUTPUT,SSTL2_I,2,,,NONE**,,,LOCATED,YES,NONE,
R7,,DIFFMI,IP_L08P_2,UNUSED,,2,,,,,,,,,
R8,,,GND,,,,,,,,,,,,
R9,,DIFFSI,IP_L11N_2/M2/GCLK1,UNUSED,,2,,,,,,,,,
R10,,DIFFS,IO_L14N_2/VREF_2, ,,2,,,,,1.25,,,,
R11,SDD<4>,IOB,IO_L16P_2/A23,BIDIR,SSTL2_I,2,,,NONE**,NONE,,LOCATED,YES,NONE,
R12,,,VCCO_2,,,2,,,,,2.50,,,,
R13,SDD<13>,IOB,IO_L19N_2/VS1/A18,BIDIR,SSTL2_I,2,,,NONE**,NONE,,LOCATED,YES,NONE,
R14,SDD<0>,IOB,IO_L20N_2/CCLK,BIDIR,SSTL2_I,2,,,NONE**,NONE,,LOCATED,YES,NONE,
R15,D<8>,IOB,IO_L01N_1/A15,BIDIR,LVCMOS33,1,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
R16,D<6>,IOB,IO_L01P_1/A16,BIDIR,LVCMOS33,1,8,SLOW,NONE**,NONE,,LOCATED,YES,NONE,
T1,,,GND,,,,,,,,,,,,
T2,,IBUF,IP,UNUSED,,2,,,,,,,,,
T3,SDNCLK_FB,DIFFMI,IP_L02P_2,INPUT,DIFF_SSTL2_I,2,,,,NONE,,LOCATED,NO,NONE,
T4,SDA<4>,IOB,IO_L04P_2,OUTPUT,SSTL2_I,2,,,NONE**,,,LOCATED,YES,NONE,
T5,SDA<6>,IOB,IO_L04N_2,OUTPUT,SSTL2_I,2,,,NONE**,,,LOCATED,YES,NONE,
T6,,,VCCAUX,,,,,,,,2.5,,,,
T7,,DIFFSI,IP_L08N_2/VREF_2, ,,2,,,,,1.25,,,,
T8,SDUDM,IOB,IO/D5,OUTPUT,SSTL2_I,2,,,NONE**,,,LOCATED,YES,NONE,
T9,,DIFFMI,IP_L11P_2/RDWR_B/GCLK0,UNUSED,,2,,,,,,,,,
T10,,IOB,IO/M1,UNUSED,,2,,,,,,,,,
T11,,,VCCAUX,,,,,,,,2.5,,,,
T12,SDD<1>,IOB,IO,BIDIR,SSTL2_I,2,,,NONE**,NONE,,LOCATED,YES,NONE,
T13,SDD<14>,IOB,IO_L19P_2/VS2/A19,BIDIR,SSTL2_I,2,,,NONE**,NONE,,LOCATED,YES,NONE,
T14,,IBUF,IP,UNUSED,,2,,,,,,,,,
T15,,,DONE,,,,,,,,,,,,
T16,,,GND,,,,,,,,,,,,
# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
#
#* Default value.
#** This default Pullup/Pulldown value can be overridden in Bitgen.
#****** Special VCCO requirements may apply. Please consult the device
# family datasheet for specific guideline on VCCO requirements.
#
#
#
\ No newline at end of file
ISE_14_7_results/x353_pad.txt 0 → 100644
View file @ f5c2e000
Release 14.7 - reportgen P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Tue Jul 28 15:45:48 2015
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors.
2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information.
3. The <design name>.pad file designed for parsing by customers. It uses the "|" as a data field separator.
INPUT FILE: x353.ncd
OUTPUT FILE: x353_pad.txt
PART TYPE: xc3s1200e
SPEED GRADE: -4
PACKAGE: ft256
Pinout by Pin Number:
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|Pin Number|Signal Name|Pin Usage|Pin Name |Direction|IO Standard |IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|A1 | | |GND | | | | | | | | | | | |
|A2 | | |TDI | | | | | | | | | | | |
|A3 | |IBUF |IP |UNUSED | |0 | | | | | | | | |
|A4 |EXT<2> |IOB |IO_L17N_0/VREF_0 |BIDIR |LVCMOS33 |0 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE |
|A5 |EXT<3> |IOB |IO_L17P_0 |BIDIR |LVCMOS33 |0 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE |
|A6 | | |VCCAUX | | | | | | | |2.5 | | | |
|A7 |D<16> |IOB |IO |BIDIR |LVCMOS33 |0 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|A8 |CLK3 |IBUF |IP_L10P_0/GCLK8 |INPUT |LVCMOS33 |0 | | | |IFD | |LOCATED |YES |NONE |
|A9 |CLK0 |IBUF |IO_L09N_0/GCLK7 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE |
|A10 |CLK1 |IBUF |IO_L09P_0/GCLK6 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE |
|A11 | | |VCCAUX | | | | | | | |2.5 | | | |
|A12 |D<15> |IOB |IO |BIDIR |LVCMOS33 |0 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|A13 |D<11> |IOB |IO_L03N_0/VREF_0 |BIDIR |LVCMOS33 |0 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|A14 |DACK1 |IBUF |IO_L01N_0 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE |
|A15 | | |TCK | | | | | | | | | | | |
|A16 | | |GND | | | | | | | | | | | |
|B1 |CNVSYNC |IOB |IO_L01P_3 |BIDIR |LVCMOS25* |3 |4 |SLOW |NONE** |IFD | |LOCATED |YES |NONE |
|B2 |CNVCLK |IOB |IO_L01N_3 |BIDIR |LVCMOS25* |3 |4 |SLOW |NONE** |IFD | |LOCATED |YES |NONE |
|B3 | |DIFFS |IO_L19N_0/HSWAP |UNUSED | |0 | | | | | | | | |
|B4 |D<19> |IOB |IO |BIDIR |LVCMOS33 |0 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|B5 | | |VCCO_0 | | |0 | | | | |3.30 | | | |
|B6 |D<23> |IOB |IO |BIDIR |LVCMOS33 |0 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|B7 |EXT<7> |IOB |IO_L13P_0 |BIDIR |LVCMOS33 |0 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE |
|B8 | |DIFFSI |IP_L10N_0/GCLK9 |UNUSED | |0 | | | | | | | | |
|B9 | | |GND | | | | | | | | | | | |
|B10 |D<14> |IOB |IO |BIDIR |LVCMOS33 |0 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|B11 |D<12> |IOB |IO_L05N_0/VREF_0 |BIDIR |LVCMOS33 |0 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|B12 | | |VCCO_0 | | |0 | | | | |3.30 | | | |
|B13 |BROUT |IOB |IO_L03P_0 |OUTPUT |LVCMOS33 |0 |4 |SLOW |NONE** | | |LOCATED |NO |NONE |
|B14 |DACK0 |IBUF |IO_L01P_0 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE |
|B15 | | |TMS | | | | | | | | | | | |
|B16 |BRIN |IBUF |IP |INPUT |LVCMOS33 |1 | | | |NONE | |LOCATED |NO |NONE |
|C1 |ARO |IOB |IO_L02P_3 |OUTPUT |LVCMOS25* |3 |4 |SLOW |NONE** | | |LOCATED |NO |NONE |
|C2 | |DIFFS |IO_L02N_3/VREF_3 | | |3 | | | | |1.25 | | | |
|C3 |D<21> |IOB |IO_L19P_0 |BIDIR |LVCMOS33 |0 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|C4 |EXT<0> |IOB |IO_L18N_0 |BIDIR |LVCMOS33 |0 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE |
|C5 |EXT<1> |IOB |IO_L18P_0 |BIDIR |LVCMOS33 |0 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE |
|C6 |EXT<5> |IOB |IO_L15P_0 |BIDIR |LVCMOS33 |0 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE |
|C7 |EXT<6> |IOB |IO_L13N_0 |BIDIR |LVCMOS33 |0 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE |
|C8 |D<30> |IOB |IO_L11P_0/GCLK10 |BIDIR |LVCMOS33 |0 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|C9 | |DIFFSI |IP_L07N_0 |UNUSED | |0 | | | | | | | | |
|C10 | |DIFFMI |IP_L07P_0 |UNUSED | |0 | | | | | | | | |
|C11 |D<10> |IOB |IO_L05P_0 |BIDIR |LVCMOS33 |0 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|C12 | |DIFFSI |IP_L02N_0 |UNUSED | |0 | | | | | | | | |
|C13 | |IBUF |IP |UNUSED | |0 | | | | | | | | |
|C14 | | |TDO | | | | | | | | | | | |
|C15 |DREQ0 |IOB |IO_L19N_1/LDC2 |OUTPUT |LVCMOS33 |1 |4 |SLOW |NONE** | | |LOCATED |YES |NONE |
|C16 |SYS_BUSEN |IOB |IO_L19P_1/LDC1 |OUTPUT |LVCMOS33 |1 |4 |SLOW |NONE** | | |LOCATED |NO |NONE |
|D1 |SENSPGM |IOB |IO_L05P_3 |BIDIR |LVCMOS25* |3 |12 |SLOW |PULLUP |NONE | |LOCATED |NO |NONE |
|D2 | |IBUF |IP |UNUSED | |3 | | | | | | | | |
|D3 | | |PROG_B | | | | | | | | | | | |
|D4 | | |VCCINT | | | | | | | |1.2 | | | |
|D5 | |DIFFMI |IP_L16P_0 |UNUSED | |0 | | | | | | | | |
|D6 |EXT<4> |IOB |IO_L15N_0 |BIDIR |LVCMOS33 |0 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE |
|D7 |EXT<9> |IOB |IO_L14N_0/VREF_0 |BIDIR |LVCMOS33 |0 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE |
|D8 |D<31> |IOB |IO_L11N_0/GCLK11 |BIDIR |LVCMOS33 |0 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|D9 |D<13> |IOB |IO/VREF_0 |BIDIR |LVCMOS33 |0 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|D10 |DREQ1 |IOB |IO_L06P_0 |OUTPUT |LVCMOS33 |0 |4 |SLOW |NONE** | | |LOCATED |YES |NONE |
|D11 |BG |IOB |IO_L04P_0 |TRISTATE |LVCMOS33 |0 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|D12 | |DIFFMI |IP_L02P_0 |UNUSED | |0 | | | | | | | | |
|D13 | | |VCCINT | | | | | | | |1.2 | | | |
|D14 |A<0> |IBUF |IO_L18N_1/LDC0 |INPUT |LVCMOS33 |1 | | | |NONE | |LOCATED |YES |NONE |
|D15 |IRQ |IOB |IO_L18P_1/HDC |OUTPUT |LVCMOS33 |1 |8 |SLOW |NONE** | | |LOCATED |NO |NONE |
|D16 |CE |IBUF |IP/VREF_1 |INPUT |LVCMOS33 |1 | | | |NONE | |LOCATED |NO |NONE |
|E1 |ARST |IOB |IO_L05N_3 |OUTPUT |LVCMOS25* |3 |4 |SLOW |NONE** | | |LOCATED |NO |NONE |
|E2 | | |VCCO_3 | | |3 | | | | |2.50 | | | |
|E3 |MRST |IOB |IO_L03P_3 |BIDIR |LVCMOS25* |3 |4 |SLOW |PULLUP |NONE | |LOCATED |NO |NONE |
|E4 |SDA0 |IOB |IO_L03N_3 |BIDIR |LVCMOS25* |3 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE |
|E5 | | |VCCINT | | | | | | | |1.2 | | | |
|E6 | |DIFFSI |IP_L16N_0 |UNUSED | |0 | | | | | | | | |
|E7 |EXT<8> |IOB |IO_L14P_0 |BIDIR |LVCMOS33 |0 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE |
|E8 |EXT<11> |IOB |IO_L12P_0 |BIDIR |LVCMOS33 |0 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE |
|E9 |D<18> |IOB |IO_L08P_0/GCLK4 |BIDIR |LVCMOS33 |0 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|E10 |D<25> |IOB |IO_L06N_0 |BIDIR |LVCMOS33 |0 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|E11 |A<3> |IBUF |IO_L04N_0 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |YES |NONE |
|E12 | | |VCCINT | | | | | | | |1.2 | | | |
|E13 |A<4> |IBUF |IO_L17P_1 |INPUT |LVCMOS33 |1 | | | |NONE | |LOCATED |YES |NONE |
|E14 |CE1 |IBUF |IP |INPUT |LVCMOS33 |1 | | | |NONE | |LOCATED |NO |NONE |
|E15 | | |VCCO_1 | | |1 | | | | |3.30 | | | |
|E16 |A<5> |IBUF |IO_L17N_1 |INPUT |LVCMOS33 |1 | | | |NONE | |LOCATED |YES |NONE |
|F1 | | |VCCAUX | | | | | | | |2.5 | | | |
|F2 | |IBUF |IP |UNUSED | |3 | | | | | | | | |
|F3 | |DIFFM |IO_L04P_3 |UNUSED | |3 | | | | | | | | |
|F4 | |DIFFS |IO_L04N_3/VREF_3 | | |3 | | | | |1.25 | | | |
|F5 | |IBUF |IP |UNUSED | |3 | | | | | | | | |
|F6 | | |GND | | | | | | | | | | | |
|F7 | | |VCCO_0 | | |0 | | | | |3.30 | | | |
|F8 |EXT<10> |IOB |IO_L12N_0 |BIDIR |LVCMOS33 |0 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE |
|F9 |D<20> |IOB |IO_L08N_0/GCLK5 |BIDIR |LVCMOS33 |0 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|F10 | | |VCCO_0 | | |0 | | | | |3.30 | | | |
|F11 | | |GND | | | | | | | | | | | |
|F12 |A<2> |IBUF |IO_L16N_1 |INPUT |LVCMOS33 |1 | | | |NONE | |LOCATED |YES |NONE |
|F13 |A<1> |IBUF |IO_L16P_1 |INPUT |LVCMOS33 |1 | | | |NONE | |LOCATED |YES |NONE |
|F14 |A<6> |IBUF |IO_L15P_1 |INPUT |LVCMOS33 |1 | | | |NONE | |LOCATED |YES |NONE |
|F15 |A<7> |IBUF |IO_L15N_1 |INPUT |LVCMOS33 |1 | | | |NONE | |LOCATED |YES |NONE |
|F16 | | |VCCAUX | | | | | | | |2.5 | | | |
|G1 | |IBUF |IP/VREF_3 | | |3 | | | | |1.25 | | | |
|G2 |SCL0 |IOB |IO_L07N_3 |BIDIR |LVCMOS25* |3 |12 |SLOW |PULLUP |NONE | |LOCATED |NO |NONE |
|G3 |PXD<8> |IBUF |IO_L07P_3 |INPUT |LVCMOS25* |3 | | | |IFD | |LOCATED |YES |NONE |
|G4 |PXD<7> |IBUF |IO_L06N_3 |INPUT |LVCMOS25* |3 | | | |IFD | |LOCATED |YES |NONE |
|G5 |PXD<5> |IBUF |IO_L06P_3 |INPUT |LVCMOS25* |3 | | | |IFD | |LOCATED |YES |NONE |
|G6 | | |VCCO_3 | | |3 | | | | |2.50 | | | |
|G7 | | |GND | | | | | | | | | | | |
|G8 | | |GND | | | | | | | | | | | |
|G9 | | |GND | | | | | | | | | | | |
|G10 | | |GND | | | | | | | | | | | |
|G11 | | |VCCO_1 | | |1 | | | | |3.30 | | | |
|G12 | |IBUF |IP |UNUSED | |1 | | | | | | | | |
|G13 | |DIFFM |IO_L14P_1 |UNUSED | |1 | | | | | | | | |
|G14 | |DIFFS |IO_L14N_1/A0 |UNUSED | |1 | | | | | | | | |
|G15 | |DIFFM |IO_L13P_1/A2 |UNUSED | |1 | | | | | | | | |
|G16 | |DIFFS |IO_L13N_1/A1 |UNUSED | |1 | | | | | | | | |
|H1 | |IBUF |IP |UNUSED | |3 | | | | | | | | |
|H2 | | |GND | | | | | | | | | | | |
|H3 |PXD<9> |IBUF |IO_L09P_3/LHCLK2 |INPUT |LVCMOS25* |3 | | | |IFD | |LOCATED |YES |NONE |
|H4 |PXD<6> |IBUF |IO_L09N_3/LHCLK3/IRDY2 |INPUT |LVCMOS25* |3 | | | |IFD | |LOCATED |YES |NONE |
|H5 |PXD<3> |IBUF |IO_L08P_3/LHCLK0 |INPUT |LVCMOS25* |3 | | | |IFD | |LOCATED |YES |NONE |
|H6 |PXD<1> |IBUF |IO_L08N_3/LHCLK1 |INPUT |LVCMOS25* |3 | | | |IFD | |LOCATED |YES |NONE |
|H7 | | |GND | | | | | | | | | | | |
|H8 | | |GND | | | | | | | | | | | |
|H9 | | |GND | | | | | | | | | | | |
|H10 | | |GND | | | | | | | | | | | |
|H11 |D<22> |IOB |IO_L12N_1/A3/RHCLK7 |BIDIR |LVCMOS33 |1 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|H12 | |DIFFM |IO_L12P_1/A4/RHCLK6 |UNUSED | |1 | | | | | | | | |
|H13 | |IBUF |IP/VREF_1 |UNUSED | |1 | | | | | | | | |
|H14 |BA<0> |IOB |IO_L11N_1/A5/RHCLK5 |TRISTATE |LVCMOS33 |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|H15 |BA<1> |IOB |IO_L11P_1/A6/RHCLK4/IRDY1|TRISTATE |LVCMOS33 |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|H16 | |IBUF |IP |UNUSED | |1 | | | | | | | | |
|J1 |PXD<4> |IBUF |IO_L12P_3 |INPUT |LVCMOS25* |3 | | | |IFD | |LOCATED |YES |NONE |
|J2 |PXD<2> |IBUF |IO_L10P_3/LHCLK4/TRDY2 |INPUT |LVCMOS25* |3 | | | |IFD | |LOCATED |YES |NONE |
|J3 |PXD<0> |IBUF |IO_L10N_3/LHCLK5 |INPUT |LVCMOS25* |3 | | | |IFD | |LOCATED |YES |NONE |
|J4 |DUMMYVFEF |IOB |IO_L11N_3/LHCLK7 |BIDIR |SSTL2_I |3 | | |NONE** |NONE | |LOCATED |NO |NONE |
|J5 |HACT |IBUF |IO_L11P_3/LHCLK6 |INPUT |LVCMOS25* |3 | | | |IFD | |LOCATED |YES |NONE |
|J6 |ALWAYS0 |IBUF |IP |INPUT |LVCMOS25* |3 | | |PULLDOWN |NONE | |LOCATED |NO |NONE |
|J7 | | |GND | | | | | | | | | | | |
|J8 | | |GND | | | | | | | | | | | |
|J9 | | |GND | | | | | | | | | | | |
|J10 | | |GND | | | | | | | | | | | |
|J11 | |IBUF |IP |UNUSED | |1 | | | | | | | | |
|J12 |SYS_SDCLKI |IBUF |IP |INPUT |LVCMOS33 |1 | | | |NONE | |LOCATED |NO |NONE |
|J13 |SYS_SDWE |IOB |IO_L10N_1/A7/RHCLK3/TRDY1|TRISTATE |LVCMOS33 |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|J14 |SYS_SDCLK |IOB |IO_L10P_1/A8/RHCLK2 |TRISTATE |LVCMOS33 |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|J15 | | |GND | | | | | | | | | | | |
|J16 |SYS_SDCAS |IOB |IO_L09N_1/A9/RHCLK1 |TRISTATE |LVCMOS33 |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|K1 |VACT |IBUF |IO_L12N_3 |INPUT |LVCMOS25* |3 | | | |IFD | |LOCATED |YES |NONE |
|K2 |SDA<3> |IOB |IO_L13P_3 |OUTPUT |SSTL2_I |3 | | |NONE** | | |LOCATED |YES |NONE |
|K3 |SDA<1> |IOB |IO_L13N_3 |OUTPUT |SSTL2_I |3 | | |NONE** | | |LOCATED |YES |NONE |
|K4 | |IBUF |IP |UNUSED | |3 | | | | | | | | |
|K5 |BPF |IBUF |IO_L15P_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
|K6 | | |VCCO_3 | | |3 | | | | |2.50 | | | |
|K7 | | |GND | | | | | | | | | | | |
|K8 | | |GND | | | | | | | | | | | |
|K9 | | |GND | | | | | | | | | | | |
|K10 | | |GND | | | | | | | | | | | |
|K11 | | |VCCO_1 | | |1 | | | | |3.30 | | | |
|K12 |D<17> |IOB |IO_L07N_1/A11 |BIDIR |LVCMOS33 |1 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|K13 |D<29> |IOB |IO_L07P_1/A12 |BIDIR |LVCMOS33 |1 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|K14 |D<24> |IOB |IO_L08N_1/VREF_1 |BIDIR |LVCMOS33 |1 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|K15 |D<26> |IOB |IO_L08P_1 |BIDIR |LVCMOS33 |1 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|K16 |SYS_SDRAS |IOB |IO_L09P_1/A10/RHCLK0 |TRISTATE |LVCMOS33 |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|L1 | | |VCCAUX | | | | | | | |2.5 | | | |
|L2 | |DIFFS |IO_L14N_3/VREF_3 | | |3 | | | | |1.25 | | | |
|L3 |DCLK |IOB |IO_L14P_3 |BIDIR |LVCMOS25* |3 |4 |SLOW |NONE** |IFD | |LOCATED |YES |NONE |
|L4 |SDA<14> |IOB |IO_L17N_3 |OUTPUT |SSTL2_I |3 | | |NONE** | | |LOCATED |YES |NONE |
|L5 | |DIFFS |IO_L15N_3 |UNUSED | |3 | | | | | | | | |
|L6 | | |GND | | | | | | | | | | | |
|L7 | | |VCCO_2 | | |2 | | | | |2.50 | | | |
|L8 |SDD<7> |IOB |IO_L09N_2/D6/GCLK13 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|L9 | |DIFFM |IO_L13P_2/M0 |UNUSED | |2 | | | | | | | | |
|L10 | | |VCCO_2 | | |2 | | | | |2.50 | | | |
|L11 | | |GND | | | | | | | | | | | |
|L12 |D<9> |IOB |IO_L05P_1 |BIDIR |LVCMOS33 |1 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|L13 |D<3> |IOB |IO_L05N_1 |BIDIR |LVCMOS33 |1 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|L14 |D<27> |IOB |IO_L06P_1 |BIDIR |LVCMOS33 |1 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|L15 |D<28> |IOB |IO_L06N_1 |BIDIR |LVCMOS33 |1 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|L16 | | |VCCAUX | | | | | | | |2.5 | | | |
|M1 |SDA<2> |IOB |IO_L16P_3 |OUTPUT |SSTL2_I |3 | | |NONE** | | |LOCATED |YES |NONE |
|M2 | | |VCCO_3 | | |3 | | | | |2.50 | | | |
|M3 | |IBUF |IP |UNUSED | |3 | | | | | | | | |
|M4 |SDA<5> |IOB |IO_L17P_3 |OUTPUT |SSTL2_I |3 | | |NONE** | | |LOCATED |YES |NONE |
|M5 | | |VCCINT | | | | | | | |1.2 | | | |
|M6 |SDRAS |IOB |IO_L05P_2 |OUTPUT |SSTL2_I |2 | | |NONE** | | |LOCATED |YES |NONE |
|M7 |SDWE |IOB |IO |OUTPUT |SSTL2_I |2 | | |NONE** | | |LOCATED |YES |NONE |
|M8 |SDLDM |IOB |IO_L09P_2/D7/GCLK12 |OUTPUT |SSTL2_I |2 | | |NONE** | | |LOCATED |YES |NONE |
|M9 |SDD<6> |IOB |IO_L13N_2/DIN/D0 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|M10 |SDD<10> |IOB |IO_L15N_2 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|M11 | |DIFFSI |IP_L17N_2 |UNUSED | |2 | | | | | | | | |
|M12 | | |VCCINT | | | | | | | |1.2 | | | |
|M13 |WE |IBUF |IP |INPUT |LVCMOS33 |1 | | | |NONE | |LOCATED |YES |NONE |
|M14 |OE |IBUF |IP |INPUT |LVCMOS33 |1 | | | |NONE | |LOCATED |NO |NONE |
|M15 | | |VCCO_1 | | |1 | | | | |3.30 | | | |
|M16 |D<0> |IOB |IO_L04N_1/VREF_1 |BIDIR |LVCMOS33 |1 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|N1 |SDA<10> |IOB |IO_L16N_3 |OUTPUT |SSTL2_I |3 | | |NONE** | | |LOCATED |YES |NONE |
|N2 | |IBUF |IP/VREF_3 | | |3 | | | | |1.25 | | | |
|N3 | |IBUF |IP |UNUSED | |3 | | | | | | | | |
|N4 | | |VCCINT | | | | | | | |1.2 | | | |
|N5 |SDA<8> |IOB |IO_L03N_2/MOSI/CSI_B |OUTPUT |SSTL2_I |2 | | |NONE** | | |LOCATED |YES |NONE |
|N6 |SDCLKE |IOB |IO_L05N_2 |OUTPUT |SSTL2_I |2 | | |NONE** | | |LOCATED |NO |NONE |
|N7 |SDCAS |IOB |IO_L07P_2 |OUTPUT |SSTL2_I |2 | | |NONE** | | |LOCATED |YES |NONE |
|N8 |LDQS |IOB |IO_L10P_2/D4/GCLK14 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|N9 |SDD<5> |IOB |IO_L12N_2/D1/GCLK3 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|N10 |SDD<3> |IOB |IO_L15P_2 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|N11 | |DIFFMI |IP_L17P_2 |UNUSED | |2 | | | | | | | | |
|N12 |SDD<2> |IOB |IO_L18N_2/A20 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|N13 | | |VCCINT | | | | | | | |1.2 | | | |
|N14 |D<5> |IOB |IO_L03P_1 |BIDIR |LVCMOS33 |1 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|N15 |D<1> |IOB |IO_L03N_1/VREF_1 |BIDIR |LVCMOS33 |1 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|N16 |D<2> |IOB |IO_L04P_1 |BIDIR |LVCMOS33 |1 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|P1 |SDA<0> |IOB |IO_L18N_3 |OUTPUT |SSTL2_I |3 | | |NONE** | | |LOCATED |YES |NONE |
|P2 |SDA<13> |IOB |IO_L18P_3 |OUTPUT |SSTL2_I |3 | | |NONE** | | |LOCATED |YES |NONE |
|P3 | |DIFFM |IO_L01P_2/CSO_B |UNUSED | |2 | | | | | | | | |
|P4 | |DIFFS |IO_L01N_2/INIT_B |UNUSED | |2 | | | | | | | | |
|P5 |SDA<7> |IOB |IO_L03P_2/DOUT/BUSY |OUTPUT |SSTL2_I |2 | | |NONE** | | |LOCATED |YES |NONE |
|P6 |SDA<11> |IOB |IO_L06N_2 |OUTPUT |SSTL2_I |2 | | |NONE** | | |LOCATED |YES |NONE |
|P7 |SDA<12> |IOB |IO_L07N_2 |OUTPUT |SSTL2_I |2 | | |NONE** | | |LOCATED |YES |NONE |
|P8 |UDQS |IOB |IO_L10N_2/D3/GCLK15 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|P9 |SDD<8> |IOB |IO_L12P_2/D2/GCLK2 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|P10 |SDD<9> |IOB |IO_L14P_2 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|P11 |SDD<11> |IOB |IO_L16N_2/A22 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|P12 |SDD<12> |IOB |IO_L18P_2/A21 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|P13 | |IOB |IO/VREF_2 | | |2 | | | | |1.25 | | | |
|P14 |SDD<15> |IOB |IO_L20P_2/VS0/A17 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|P15 |D<7> |IOB |IO_L02N_1/A13 |BIDIR |LVCMOS33 |1 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|P16 |D<4> |IOB |IO_L02P_1/A14 |BIDIR |LVCMOS33 |1 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|R1 |SDNCLK |DIFFS |IO_L19N_3 |OUTPUT |DIFF_SSTL2_I|3 | | |NONE** | | |LOCATED |NO |NONE |
|R2 |SDCLK |DIFFM |IO_L19P_3 |OUTPUT |DIFF_SSTL2_I|3 | | |NONE** | | |LOCATED |NO |NONE |
|R3 |SDCLK_FB |DIFFSI |IP_L02N_2 |INPUT |DIFF_SSTL2_I|2 | | | |NONE | |LOCATED |NO |NONE |
|R4 | |IOB |IO/VREF_2 | | |2 | | | | |1.25 | | | |
|R5 | | |VCCO_2 | | |2 | | | | |2.50 | | | |
|R6 |SDA<9> |IOB |IO_L06P_2 |OUTPUT |SSTL2_I |2 | | |NONE** | | |LOCATED |YES |NONE |
|R7 | |DIFFMI |IP_L08P_2 |UNUSED | |2 | | | | | | | | |
|R8 | | |GND | | | | | | | | | | | |
|R9 | |DIFFSI |IP_L11N_2/M2/GCLK1 |UNUSED | |2 | | | | | | | | |
|R10 | |DIFFS |IO_L14N_2/VREF_2 | | |2 | | | | |1.25 | | | |
|R11 |SDD<4> |IOB |IO_L16P_2/A23 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|R12 | | |VCCO_2 | | |2 | | | | |2.50 | | | |
|R13 |SDD<13> |IOB |IO_L19N_2/VS1/A18 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|R14 |SDD<0> |IOB |IO_L20N_2/CCLK |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|R15 |D<8> |IOB |IO_L01N_1/A15 |BIDIR |LVCMOS33 |1 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|R16 |D<6> |IOB |IO_L01P_1/A16 |BIDIR |LVCMOS33 |1 |8 |SLOW |NONE** |NONE | |LOCATED |YES |NONE |
|T1 | | |GND | | | | | | | | | | | |
|T2 | |IBUF |IP |UNUSED | |2 | | | | | | | | |
|T3 |SDNCLK_FB |DIFFMI |IP_L02P_2 |INPUT |DIFF_SSTL2_I|2 | | | |NONE | |LOCATED |NO |NONE |
|T4 |SDA<4> |IOB |IO_L04P_2 |OUTPUT |SSTL2_I |2 | | |NONE** | | |LOCATED |YES |NONE |
|T5 |SDA<6> |IOB |IO_L04N_2 |OUTPUT |SSTL2_I |2 | | |NONE** | | |LOCATED |YES |NONE |
|T6 | | |VCCAUX | | | | | | | |2.5 | | | |
|T7 | |DIFFSI |IP_L08N_2/VREF_2 | | |2 | | | | |1.25 | | | |
|T8 |SDUDM |IOB |IO/D5 |OUTPUT |SSTL2_I |2 | | |NONE** | | |LOCATED |YES |NONE |
|T9 | |DIFFMI |IP_L11P_2/RDWR_B/GCLK0 |UNUSED | |2 | | | | | | | | |
|T10 | |IOB |IO/M1 |UNUSED | |2 | | | | | | | | |
|T11 | | |VCCAUX | | | | | | | |2.5 | | | |
|T12 |SDD<1> |IOB |IO |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|T13 |SDD<14> |IOB |IO_L19P_2/VS2/A19 |BIDIR |SSTL2_I |2 | | |NONE** |NONE | |LOCATED |YES |NONE |
|T14 | |IBUF |IP |UNUSED | |2 | | | | | | | | |
|T15 | | |DONE | | | | | | | | | | | |
|T16 | | |GND | | | | | | | | | | | |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
* Default value.
** This default Pullup/Pulldown value can be overridden in Bitgen.
****** Special VCCO requirements may apply. Please consult the device
family datasheet for specific guideline on VCCO requirements.
ISE_14_7_results/x353_par.xrpt 0 → 100644
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ISE_14_7_results/x353_reportgen.xrpt 0 → 100644
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<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="lin64" product="ISE" version="14.7">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
</document>
ISE_14_7_results/x353_summary.xml 0 → 100644
View file @ f5c2e000
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DesignSummary rev="3">
<CmdHistory>
</CmdHistory>
</DesignSummary>
ISE_14_7_results/x353_usage.xml 0 → 100644
View file @ f5c2e000
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DeviceUsageSummary rev="3">
<DesignStatistics TimeStamp="Tue Jul 28 15:44:06 2015"><group name="NetStatistics">
<item name="NumNets_Active" rev="3">
<attrib name="value" value="13897"/></item>
<item name="NumNets_Gnd" rev="3">
<attrib name="value" value="1"/></item>
<item name="NumNets_Vcc" rev="3">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_BRAMADDR" rev="3">
<attrib name="value" value="433"/></item>
<item name="NumNodesOfType_Active_BRAMDUMMY" rev="3">
<attrib name="value" value="1676"/></item>
<item name="NumNodesOfType_Active_CLKPIN" rev="3">
<attrib name="value" value="5248"/></item>
<item name="NumNodesOfType_Active_CNTRLPIN" rev="3">
<attrib name="value" value="3881"/></item>
<item name="NumNodesOfType_Active_DOUBLE" rev="3">
<attrib name="value" value="32172"/></item>
<item name="NumNodesOfType_Active_DUMMY" rev="3">
<attrib name="value" value="26799"/></item>
<item name="NumNodesOfType_Active_DUMMYBANK" rev="3">
<attrib name="value" value="507"/></item>
<item name="NumNodesOfType_Active_DUMMYESC" rev="3">
<attrib name="value" value="39"/></item>
<item name="NumNodesOfType_Active_GLOBAL" rev="3">
<attrib name="value" value="755"/></item>
<item name="NumNodesOfType_Active_HFULLHEX" rev="3">
<attrib name="value" value="590"/></item>
<item name="NumNodesOfType_Active_HLONG" rev="3">
<attrib name="value" value="271"/></item>
<item name="NumNodesOfType_Active_HUNIHEX" rev="3">
<attrib name="value" value="3734"/></item>
<item name="NumNodesOfType_Active_INPUT" rev="3">
<attrib name="value" value="34756"/></item>
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="3">
<attrib name="value" value="133"/></item>
<item name="NumNodesOfType_Active_OMUX" rev="3">
<attrib name="value" value="14432"/></item>
<item name="NumNodesOfType_Active_OUTPUT" rev="3">
<attrib name="value" value="12892"/></item>
<item name="NumNodesOfType_Active_PREBXBY" rev="3">
<attrib name="value" value="10887"/></item>
<item name="NumNodesOfType_Active_VFULLHEX" rev="3">
<attrib name="value" value="1904"/></item>
<item name="NumNodesOfType_Active_VLONG" rev="3">
<attrib name="value" value="480"/></item>
<item name="NumNodesOfType_Active_VUNIHEX" rev="3">
<attrib name="value" value="3246"/></item>
<item name="NumNodesOfType_Gnd_BRAMADDR" rev="3">
<attrib name="value" value="17"/></item>
<item name="NumNodesOfType_Gnd_BRAMDUMMY" rev="3">
<attrib name="value" value="359"/></item>
<item name="NumNodesOfType_Gnd_CLKPIN" rev="3">
<attrib name="value" value="3"/></item>
<item name="NumNodesOfType_Gnd_CNTRLPIN" rev="3">
<attrib name="value" value="40"/></item>
<item name="NumNodesOfType_Gnd_DOUBLE" rev="3">
<attrib name="value" value="236"/></item>
<item name="NumNodesOfType_Gnd_DUMMY" rev="3">
<attrib name="value" value="1298"/></item>
<item name="NumNodesOfType_Gnd_DUMMYBANK" rev="3">
<attrib name="value" value="25"/></item>
<item name="NumNodesOfType_Gnd_HFULLHEX" rev="3">
<attrib name="value" value="3"/></item>
<item name="NumNodesOfType_Gnd_HUNIHEX" rev="3">
<attrib name="value" value="4"/></item>
<item name="NumNodesOfType_Gnd_INPUT" rev="3">
<attrib name="value" value="1768"/></item>
<item name="NumNodesOfType_Gnd_OMUX" rev="3">
<attrib name="value" value="566"/></item>
<item name="NumNodesOfType_Gnd_OUTPUT" rev="3">
<attrib name="value" value="333"/></item>
<item name="NumNodesOfType_Gnd_PREBXBY" rev="3">
<attrib name="value" value="165"/></item>
<item name="NumNodesOfType_Gnd_VFULLHEX" rev="3">
<attrib name="value" value="24"/></item>
<item name="NumNodesOfType_Gnd_VLONG" rev="3">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Gnd_VUNIHEX" rev="3">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Vcc_BRAMDUMMY" rev="3">
<attrib name="value" value="64"/></item>
<item name="NumNodesOfType_Vcc_CNTRLPIN" rev="3">
<attrib name="value" value="270"/></item>
<item name="NumNodesOfType_Vcc_DUMMY" rev="3">
<attrib name="value" value="204"/></item>
<item name="NumNodesOfType_Vcc_INPUT" rev="3">
<attrib name="value" value="370"/></item>
<item name="NumNodesOfType_Vcc_PREBXBY" rev="3">
<attrib name="value" value="94"/></item>
<item name="NumNodesOfType_Vcc_VCCOUT" rev="3">
<attrib name="value" value="337"/></item>
</group>
<group name="SiteStatistics">
<item name="IBUF-DIFFM" rev="3">
<attrib name="value" value="13"/></item>
<item name="IBUF-DIFFMI" rev="3">
<attrib name="value" value="1"/></item>
<item name="IBUF-DIFFS" rev="3">
<attrib name="value" value="12"/></item>
<item name="IOB-DIFFM" rev="3">
<attrib name="value" value="49"/></item>
<item name="IOB-DIFFS" rev="3">
<attrib name="value" value="47"/></item>
<item name="SLICEL-SLICEM" rev="3">
<attrib name="value" value="2919"/></item>
</group>
<group name="MiscellaneousStatistics">
<item name="AGG_BONDED_IO" rev="2">
<attrib name="value" value="142"/></item>
<item name="AGG_IO" rev="2">
<attrib name="value" value="142"/></item>
<item name="AGG_SLICE" rev="2">
<attrib name="value" value="6969"/></item>
<item name="NUM_4_INPUT_LUT" rev="2">
<attrib name="value" value="9293"/></item>
<item name="NUM_BONDED_DIFFM" rev="2">
<attrib name="value" value="1"/></item>
<item name="NUM_BONDED_DIFFMI" rev="2">
<attrib name="value" value="1"/></item>
<item name="NUM_BONDED_DIFFS" rev="2">
<attrib name="value" value="1"/></item>
<item name="NUM_BONDED_DIFFSI" rev="2">
<attrib name="value" value="1"/></item>
<item name="NUM_BONDED_IBUF" rev="2">
<attrib name="value" value="33"/></item>
<item name="NUM_BONDED_IOB" rev="2">
<attrib name="value" value="105"/></item>
<item name="NUM_BUFGMUX" rev="2">
<attrib name="value" value="9"/></item>
<item name="NUM_CYMUX" rev="2">
<attrib name="value" value="2055"/></item>
<item name="NUM_DCM" rev="2">
<attrib name="value" value="4"/></item>
<item name="NUM_DP_RAM" rev="2">
<attrib name="value" value="676"/></item>
<item name="NUM_IDDR2_NONE" rev="2">
<attrib name="value" value="18"/></item>
<item name="NUM_IOB_FF" rev="2">
<attrib name="value" value="66"/></item>
<item name="NUM_IOB_LATCH" rev="2">
<attrib name="value" value="9"/></item>
<item name="NUM_LUT_RT" rev="2">
<attrib name="value" value="491"/></item>
<item name="NUM_MULT18X18SIO" rev="2">
<attrib name="value" value="19"/></item>
<item name="NUM_MULTAND" rev="2">
<attrib name="value" value="88"/></item>
<item name="NUM_ODDR2_NONE" rev="2">
<attrib name="value" value="20"/></item>
<item name="NUM_RAM16" rev="2">
<attrib name="value" value="13"/></item>
<item name="NUM_RAMB16" rev="2">
<attrib name="value" value="22"/></item>
<item name="NUM_SHIFT" rev="2">
<attrib name="value" value="280"/></item>
<item name="NUM_SLICEL" rev="2">
<attrib name="value" value="6416"/></item>
<item name="NUM_SLICEM" rev="2">
<attrib name="value" value="553"/></item>
<item name="NUM_SLICE_FF" rev="2">
<attrib name="value" value="7515"/></item>
<item name="NUM_SLICE_LATCH" rev="2">
<attrib name="value" value="58"/></item>
<item name="NUM_XOR" rev="2">
<attrib name="value" value="1969"/></item>
</group>
</DesignStatistics>
<DeviceUsage TimeStamp="Tue Jul 28 15:44:06 2015"><group name="SiteSummary">
<item name="BUFGMUX" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="9"/></item>
<item name="BUFGMUX_GCLKMUX" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="9"/></item>
<item name="BUFGMUX_GCLK_BUFFER" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="9"/></item>
<item name="DCM" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="4"/></item>
<item name="DCM_DCM" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="4"/></item>
<item name="DIFFM" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="DIFFMI" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="DIFFMI_INBUF" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="DIFFMI_PAD" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="DIFFM_OUTBUF" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="DIFFM_PAD" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="DIFFS" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="DIFFSI" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="DIFFSI_PAD" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="DIFFSI_PADOUT_USED" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="DIFFS_OUTBUF" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="DIFFS_PAD" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="IBUF" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="33"/></item>
<item name="IBUF_IFD_DELAY" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="13"/></item>
<item name="IBUF_IFF1" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="22"/></item>
<item name="IBUF_IFF2" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="IBUF_INBUF" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="33"/></item>
<item name="IBUF_PAD" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="33"/></item>
<item name="IOB" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="105"/></item>
<item name="IOB_IFD_DELAY" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="3"/></item>
<item name="IOB_IFF1" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="53"/></item>
<item name="IOB_IFF2" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="18"/></item>
<item name="IOB_INBUF" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="70"/></item>
<item name="IOB_OFF1" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="40"/></item>
<item name="IOB_OFF2" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="20"/></item>
<item name="IOB_OFFDDRBLACKBOX" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="20"/></item>
<item name="IOB_OUTBUF" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="105"/></item>
<item name="IOB_PAD" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="105"/></item>
<item name="IOB_TFF1" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="16"/></item>
<item name="MULT18X18SIO" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="19"/></item>
<item name="MULT18X18SIO_MULT18X18SIO" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="19"/></item>
<item name="RAMB16" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="22"/></item>
<item name="RAMB16_RAMB16" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="22"/></item>
<item name="RAMB16_RAMB16A" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="22"/></item>
<item name="RAMB16_RAMB16B" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="22"/></item>
<item name="SLICEL" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="6416"/></item>
<item name="SLICEL_C1VDD" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="181"/></item>
<item name="SLICEL_C2VDD" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="145"/></item>
<item name="SLICEL_CYMUXF" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="1073"/></item>
<item name="SLICEL_CYMUXG" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="982"/></item>
<item name="SLICEL_F" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="4108"/></item>
<item name="SLICEL_F5MUX" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="607"/></item>
<item name="SLICEL_F6MUX" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="21"/></item>
<item name="SLICEL_FAND" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="45"/></item>
<item name="SLICEL_FFX" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="3641"/></item>
<item name="SLICEL_FFY" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="3671"/></item>
<item name="SLICEL_G" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="4211"/></item>
<item name="SLICEL_GAND" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="43"/></item>
<item name="SLICEL_GNDF" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="405"/></item>
<item name="SLICEL_GNDG" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="378"/></item>
<item name="SLICEL_XORF" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="1012"/></item>
<item name="SLICEL_XORG" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="957"/></item>
<item name="SLICEM" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="553"/></item>
<item name="SLICEM_F" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="421"/></item>
<item name="SLICEM_F5MUX" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="SLICEM_FFX" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="124"/></item>
<item name="SLICEM_FFY" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="137"/></item>
<item name="SLICEM_G" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="553"/></item>
<item name="SLICEM_GMC15_BLACKBOX" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="24"/></item>
<item name="SLICEM_WSGEN" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="553"/></item>
</group>
</DeviceUsage>
<ReportConfigData TimeStamp="Tue Jul 28 15:44:06 2015"><group name="SLICEL_CYMUXF">
<item name="0" rev="3">
<attrib name="0" value="1073"/><attrib name="0_INV" value="0"/></item>
<item name="1" rev="3">
<attrib name="1_INV" value="14"/><attrib name="1" value="1059"/></item>
</group>
<group name="SLICEL_CYMUXG">
<item name="0" rev="3">
<attrib name="0" value="982"/><attrib name="0_INV" value="0"/></item>
</group>
<group name="IBUF_PAD">
<item name="IOATTRBOX" rev="3">
<attrib name="LVCMOS25" value="14"/><attrib name="LVCMOS33" value="19"/></item>
<item name="PULL" rev="3">
<attrib name="PULLDOWN" value="1"/></item>
</group>
<group name="DIFFS_OUTBUF">
<item name="IN" rev="3">
<attrib name="IN_INV" value="1"/><attrib name="IN" value="0"/></item>
</group>
<group name="IBUF_INBUF">
<item name="IBUF_DELAY_VALUE" rev="3">
<attrib name="DLY0" value="33"/></item>
<item name="IFD_DELAY_VALUE" rev="3">
<attrib name="DLY0" value="16"/><attrib name="DLY3" value="13"/></item>
</group>
<group name="SLICEM_F">
<item name="DI" rev="3">
<attrib name="DI" value="416"/><attrib name="DI_INV" value="0"/></item>
<item name="F_ATTR" rev="3">
<attrib name="DUAL_PORT" value="338"/><attrib name="SHIFT_REG" value="72"/></item>
<item name="LUT_OR_MEM" rev="3">
<attrib name="LUT" value="5"/><attrib name="RAM" value="416"/></item>
</group>
<group name="SLICEM_G">
<item name="DI" rev="3">
<attrib name="DI" value="553"/><attrib name="DI_INV" value="0"/></item>
<item name="G_ATTR" rev="3">
<attrib name="DUAL_PORT" value="338"/><attrib name="SHIFT_REG" value="208"/></item>
<item name="LUT_OR_MEM" rev="3">
<attrib name="RAM" value="553"/></item>
</group>
<group name="SLICEL">
<item name="BX" rev="3">
<attrib name="BX_INV" value="64"/><attrib name="BX" value="2231"/></item>
<item name="BY" rev="3">
<attrib name="BY" value="2003"/><attrib name="BY_INV" value="78"/></item>
<item name="CE" rev="3">
<attrib name="CE" value="2361"/><attrib name="CE_INV" value="15"/></item>
<item name="CIN" rev="3">
<attrib name="CIN_INV" value="0"/><attrib name="CIN" value="975"/></item>
<item name="CLK" rev="3">
<attrib name="CLK" value="2406"/><attrib name="CLK_INV" value="2062"/></item>
<item name="SR" rev="3">
<attrib name="SR" value="616"/><attrib name="SR_INV" value="414"/></item>
</group>
<group name="SLICEM">
<item name="BX" rev="3">
<attrib name="BX_INV" value="1"/><attrib name="BX" value="77"/></item>
<item name="BY" rev="3">
<attrib name="BY" value="553"/><attrib name="BY_INV" value="0"/></item>
<item name="CE" rev="3">
<attrib name="CE" value="41"/><attrib name="CE_INV" value="0"/></item>
<item name="CLK" rev="3">
<attrib name="CLK" value="328"/><attrib name="CLK_INV" value="225"/></item>
<item name="SR" rev="3">
<attrib name="SR" value="553"/><attrib name="SR_INV" value="0"/></item>
</group>
<group name="SLICEL_F6MUX">
<item name="S0" rev="3">
<attrib name="S0" value="21"/><attrib name="S0_INV" value="0"/></item>
</group>
<group name="RAMB16">
<item name="CLKA" rev="3">
<attrib name="CLKA_INV" value="4"/><attrib name="CLKA" value="18"/></item>
<item name="CLKB" rev="3">
<attrib name="CLKB_INV" value="14"/><attrib name="CLKB" value="8"/></item>
<item name="ENA" rev="3">
<attrib name="ENA_INV" value="0"/><attrib name="ENA" value="22"/></item>
<item name="ENB" rev="3">
<attrib name="ENB_INV" value="1"/><attrib name="ENB" value="21"/></item>
<item name="SSRA" rev="3">
<attrib name="SSRA_INV" value="0"/><attrib name="SSRA" value="22"/></item>
<item name="SSRB" rev="3">
<attrib name="SSRB_INV" value="0"/><attrib name="SSRB" value="22"/></item>
<item name="WEA" rev="3">
<attrib name="WEA" value="22"/><attrib name="WEA_INV" value="0"/></item>
<item name="WEB" rev="3">
<attrib name="WEB" value="22"/><attrib name="WEB_INV" value="0"/></item>
</group>
<group name="IOB_OFF1">
<item name="CE" rev="3">
<attrib name="CE" value="20"/><attrib name="CE_INV" value="0"/></item>
<item name="CK" rev="3">
<attrib name="CK" value="22"/><attrib name="CK_INV" value="18"/></item>
<item name="D" rev="3">
<attrib name="D" value="40"/><attrib name="D_INV" value="0"/></item>
<item name="LATCH_OR_FF" rev="3">
<attrib name="FF" value="40"/></item>
<item name="OFF1_INIT_ATTR" rev="3">
<attrib name="INIT0" value="22"/><attrib name="INIT1" value="18"/></item>
<item name="OFF1_SR_ATTR" rev="3">
<attrib name="SRLOW" value="4"/></item>
<item name="OFFATTRBOX" rev="3">
<attrib name="ASYNC" value="2"/><attrib name="SYNC" value="2"/></item>
<item name="REV" rev="3">
<attrib name="REV_INV" value="0"/><attrib name="REV" value="2"/></item>
<item name="SR" rev="3">
<attrib name="SR" value="4"/><attrib name="SR_INV" value="0"/></item>
</group>
<group name="IOB_OFF2">
<item name="CE" rev="3">
<attrib name="CE" value="20"/><attrib name="CE_INV" value="0"/></item>
<item name="CK" rev="3">
<attrib name="CK" value="0"/><attrib name="CK_INV" value="20"/></item>
<item name="D" rev="3">
<attrib name="D" value="20"/><attrib name="D_INV" value="0"/></item>
<item name="LATCH_OR_FF" rev="3">
<attrib name="FF" value="20"/></item>
<item name="OFF2_INIT_ATTR" rev="3">
<attrib name="INIT0" value="20"/></item>
<item name="OFF2_SR_ATTR" rev="3">
<attrib name="SRLOW" value="2"/></item>
<item name="OFFATTRBOX" rev="3">
<attrib name="ASYNC" value="2"/></item>
<item name="SR" rev="3">
<attrib name="SR" value="2"/><attrib name="SR_INV" value="0"/></item>
</group>
<group name="IOB_OUTBUF">
<item name="IN" rev="3">
<attrib name="IN_INV" value="1"/><attrib name="IN" value="104"/></item>
<item name="TRI" rev="3">
<attrib name="TRI_INV" value="0"/><attrib name="TRI" value="77"/></item>
</group>
<group name="DIFFM_PAD">
<item name="IOATTRBOX" rev="3">
<attrib name="DIFF_SSTL2_I" value="1"/></item>
</group>
<group name="RAMB16_RAMB16A">
<item name="CLKA" rev="3">
<attrib name="CLKA_INV" value="4"/><attrib name="CLKA" value="18"/></item>
<item name="ENA" rev="3">
<attrib name="ENA_INV" value="0"/><attrib name="ENA" value="22"/></item>
<item name="PORTA_ATTR" rev="3">
<attrib name="512X36" value="1"/><attrib name="2048X9" value="8"/><attrib name="1024X18" value="11"/><attrib name="4096X4" value="2"/></item>
<item name="SSRA" rev="3">
<attrib name="SSRA_INV" value="0"/><attrib name="SSRA" value="22"/></item>
<item name="WEA" rev="3">
<attrib name="WEA" value="22"/><attrib name="WEA_INV" value="0"/></item>
<item name="WRITEMODEA" rev="3">
<attrib name="WRITE_FIRST" value="22"/></item>
</group>
<group name="RAMB16_RAMB16B">
<item name="CLKB" rev="3">
<attrib name="CLKB_INV" value="14"/><attrib name="CLKB" value="8"/></item>
<item name="ENB" rev="3">
<attrib name="ENB_INV" value="1"/><attrib name="ENB" value="21"/></item>
<item name="PORTB_ATTR" rev="3">
<attrib name="512X36" value="7"/><attrib name="2048X9" value="6"/><attrib name="1024X18" value="9"/></item>
<item name="SSRB" rev="3">
<attrib name="SSRB_INV" value="0"/><attrib name="SSRB" value="22"/></item>
<item name="WEB" rev="3">
<attrib name="WEB" value="22"/><attrib name="WEB_INV" value="0"/></item>
<item name="WRITEMODEB" rev="3">
<attrib name="WRITE_FIRST" value="22"/></item>
</group>
<group name="IOB_IFF1">
<item name="CE" rev="3">
<attrib name="CE" value="19"/><attrib name="CE_INV" value="0"/></item>
<item name="CK" rev="3">
<attrib name="CK" value="53"/><attrib name="CK_INV" value="0"/></item>
<item name="IFF1_INIT_ATTR" rev="3">
<attrib name="INIT0" value="53"/></item>
<item name="IFF1_SR_ATTR" rev="3">
<attrib name="SRLOW" value="16"/></item>
<item name="IFFATTRBOX" rev="3">
<attrib name="SYNC" value="16"/></item>
<item name="LATCH_OR_FF" rev="3">
<attrib name="FF" value="53"/></item>
<item name="REV" rev="3">
<attrib name="REV_INV" value="0"/><attrib name="REV" value="16"/></item>
<item name="SR" rev="3">
<attrib name="SR" value="16"/><attrib name="SR_INV" value="0"/></item>
</group>
<group name="DIFFM_OUTBUF">
<item name="IN" rev="3">
<attrib name="IN_INV" value="0"/><attrib name="IN" value="1"/></item>
</group>
<group name="IOB_IFF2">
<item name="CE" rev="3">
<attrib name="CE" value="16"/><attrib name="CE_INV" value="0"/></item>
<item name="CK" rev="3">
<attrib name="CK" value="0"/><attrib name="CK_INV" value="18"/></item>
<item name="IFF2_INIT_ATTR" rev="3">
<attrib name="INIT0" value="18"/></item>
<item name="IFF2_SR_ATTR" rev="3">
<attrib name="SRLOW" value="16"/></item>
<item name="IFFATTRBOX" rev="3">
<attrib name="SYNC" value="16"/></item>
<item name="LATCH_OR_FF" rev="3">
<attrib name="FF" value="18"/></item>
<item name="REV" rev="3">
<attrib name="REV_INV" value="0"/><attrib name="REV" value="16"/></item>
<item name="SR" rev="3">
<attrib name="SR" value="16"/><attrib name="SR_INV" value="0"/></item>
</group>
<group name="IBUF">
<item name="ICE" rev="3">
<attrib name="ICE" value="12"/><attrib name="ICE_INV" value="0"/></item>
<item name="ICLK1" rev="3">
<attrib name="ICLK1_INV" value="10"/><attrib name="ICLK1" value="12"/></item>
<item name="ICLK2" rev="3">
<attrib name="ICLK2_INV" value="2"/><attrib name="ICLK2" value="0"/></item>
<item name="REV" rev="3">
<attrib name="REV_INV" value="0"/><attrib name="REV" value="2"/></item>
<item name="SR" rev="3">
<attrib name="SR" value="2"/><attrib name="SR_INV" value="0"/></item>
</group>
<group name="MULT18X18SIO">
<item name="CEA" rev="3">
<attrib name="CEA_INV" value="0"/><attrib name="CEA" value="19"/></item>
<item name="CEB" rev="3">
<attrib name="CEB_INV" value="0"/><attrib name="CEB" value="19"/></item>
<item name="CEP" rev="3">
<attrib name="CEP" value="19"/><attrib name="CEP_INV" value="0"/></item>
<item name="CLK" rev="3">
<attrib name="CLK" value="14"/><attrib name="CLK_INV" value="5"/></item>
<item name="RSTA" rev="3">
<attrib name="RSTA" value="19"/><attrib name="RSTA_INV" value="0"/></item>
<item name="RSTB" rev="3">
<attrib name="RSTB" value="19"/><attrib name="RSTB_INV" value="0"/></item>
<item name="RSTP" rev="3">
<attrib name="RSTP_INV" value="0"/><attrib name="RSTP" value="19"/></item>
</group>
<group name="IOB_TFF1">
<item name="CK" rev="3">
<attrib name="CK" value="16"/><attrib name="CK_INV" value="0"/></item>
<item name="D" rev="3">
<attrib name="D" value="16"/><attrib name="D_INV" value="0"/></item>
<item name="LATCH_OR_FF" rev="3">
<attrib name="FF" value="16"/></item>
<item name="TFF1_INIT_ATTR" rev="3">
<attrib name="INIT1" value="16"/></item>
</group>
<group name="SLICEM_F5MUX">
<item name="S0" rev="3">
<attrib name="S0" value="1"/><attrib name="S0_INV" value="0"/></item>
</group>
<group name="IOB_INBUF">
<item name="IBUF_DELAY_VALUE" rev="3">
<attrib name="DLY0" value="70"/></item>
<item name="IFD_DELAY_VALUE" rev="3">
<attrib name="DLY0" value="50"/><attrib name="DLY3" value="3"/></item>
</group>
<group name="SLICEL_FFX">
<item name="CE" rev="3">
<attrib name="CE" value="2064"/><attrib name="CE_INV" value="9"/></item>
<item name="CK" rev="3">
<attrib name="CK" value="1947"/><attrib name="CK_INV" value="1694"/></item>
<item name="D" rev="3">
<attrib name="D" value="3591"/><attrib name="D_INV" value="50"/></item>
<item name="FFX_INIT_ATTR" rev="3">
<attrib name="INIT0" value="3552"/><attrib name="INIT1" value="89"/></item>
<item name="FFX_SR_ATTR" rev="3">
<attrib name="SRLOW" value="3576"/><attrib name="SRHIGH" value="65"/></item>
<item name="LATCH_OR_FF" rev="3">
<attrib name="FF" value="3613"/><attrib name="LATCH" value="28"/></item>
<item name="REV" rev="3">
<attrib name="REV_INV" value="1"/><attrib name="REV" value="42"/></item>
<item name="SR" rev="3">
<attrib name="SR" value="433"/><attrib name="SR_INV" value="294"/></item>
<item name="SYNC_ATTR" rev="3">
<attrib name="ASYNC" value="2952"/><attrib name="SYNC" value="689"/></item>
</group>
<group name="SLICEL_XORF">
<item name="1" rev="3">
<attrib name="1_INV" value="14"/><attrib name="1" value="998"/></item>
</group>
<group name="SLICEL_FFY">
<item name="CE" rev="3">
<attrib name="CE" value="1999"/><attrib name="CE_INV" value="14"/></item>
<item name="CK" rev="3">
<attrib name="CK" value="1969"/><attrib name="CK_INV" value="1702"/></item>
<item name="D" rev="3">
<attrib name="D" value="3594"/><attrib name="D_INV" value="77"/></item>
<item name="FFY_INIT_ATTR" rev="3">
<attrib name="INIT0" value="3520"/><attrib name="INIT1" value="151"/></item>
<item name="FFY_SR_ATTR" rev="3">
<attrib name="SRLOW" value="3599"/><attrib name="SRHIGH" value="72"/></item>
<item name="LATCH_OR_FF" rev="3">
<attrib name="FF" value="3641"/><attrib name="LATCH" value="30"/></item>
<item name="REV" rev="3">
<attrib name="REV_INV" value="0"/><attrib name="REV" value="8"/></item>
<item name="SR" rev="3">
<attrib name="SR" value="491"/><attrib name="SR_INV" value="289"/></item>
<item name="SYNC_ATTR" rev="3">
<attrib name="ASYNC" value="2969"/><attrib name="SYNC" value="702"/></item>
</group>
<group name="BUFGMUX_GCLKMUX">
<item name="DISABLE_ATTR" rev="3">
<attrib name="LOW" value="9"/></item>
<item name="S" rev="3">
<attrib name="S_INV" value="7"/><attrib name="S" value="2"/></item>
</group>
<group name="SLICEL_F5MUX">
<item name="S0" rev="3">
<attrib name="S0" value="607"/><attrib name="S0_INV" value="0"/></item>
</group>
<group name="DIFFMI_INBUF">
<item name="IBUF_DELAY_VALUE" rev="3">
<attrib name="DLY0" value="1"/></item>
</group>
<group name="MULT18X18SIO_MULT18X18SIO">
<item name="AREG" rev="3">
<attrib name="0" value="3"/><attrib name="1" value="16"/></item>
<item name="BREG" rev="3">
<attrib name="0" value="3"/><attrib name="1" value="16"/></item>
<item name="B_INPUT" rev="3">
<attrib name="DIRECT" value="19"/></item>
<item name="CEA" rev="3">
<attrib name="CEA_INV" value="0"/><attrib name="CEA" value="19"/></item>
<item name="CEB" rev="3">
<attrib name="CEB_INV" value="0"/><attrib name="CEB" value="19"/></item>
<item name="CEP" rev="3">
<attrib name="CEP" value="19"/><attrib name="CEP_INV" value="0"/></item>
<item name="CLK" rev="3">
<attrib name="CLK" value="14"/><attrib name="CLK_INV" value="5"/></item>
<item name="PREG" rev="3">
<attrib name="0" value="12"/><attrib name="1" value="7"/></item>
<item name="PREG_CLKINVERSION" rev="3">
<attrib name="0" value="19"/></item>
<item name="RSTA" rev="3">
<attrib name="RSTA" value="19"/><attrib name="RSTA_INV" value="0"/></item>
<item name="RSTB" rev="3">
<attrib name="RSTB" value="19"/><attrib name="RSTB_INV" value="0"/></item>
<item name="RSTP" rev="3">
<attrib name="RSTP_INV" value="0"/><attrib name="RSTP" value="19"/></item>
</group>
<group name="IBUF_IFF1">
<item name="CE" rev="3">
<attrib name="CE" value="12"/><attrib name="CE_INV" value="0"/></item>
<item name="CK" rev="3">
<attrib name="CK" value="12"/><attrib name="CK_INV" value="10"/></item>
<item name="IFF1_INIT_ATTR" rev="3">
<attrib name="INIT0" value="22"/></item>
<item name="IFF1_SR_ATTR" rev="3">
<attrib name="SRLOW" value="2"/></item>
<item name="IFFATTRBOX" rev="3">
<attrib name="SYNC" value="2"/></item>
<item name="LATCH_OR_FF" rev="3">
<attrib name="FF" value="13"/><attrib name="LATCH" value="9"/></item>
<item name="REV" rev="3">
<attrib name="REV_INV" value="0"/><attrib name="REV" value="2"/></item>
<item name="SR" rev="3">
<attrib name="SR" value="2"/><attrib name="SR_INV" value="0"/></item>
</group>
<group name="IBUF_IFF2">
<item name="CE" rev="3">
<attrib name="CE" value="2"/><attrib name="CE_INV" value="0"/></item>
<item name="CK" rev="3">
<attrib name="CK" value="0"/><attrib name="CK_INV" value="2"/></item>
<item name="IFF2_INIT_ATTR" rev="3">
<attrib name="INIT0" value="2"/></item>
<item name="IFF2_SR_ATTR" rev="3">
<attrib name="SRLOW" value="2"/></item>
<item name="IFFATTRBOX" rev="3">
<attrib name="SYNC" value="2"/></item>
<item name="LATCH_OR_FF" rev="3">
<attrib name="FF" value="2"/></item>
<item name="REV" rev="3">
<attrib name="REV_INV" value="0"/><attrib name="REV" value="2"/></item>
<item name="SR" rev="3">
<attrib name="SR" value="2"/><attrib name="SR_INV" value="0"/></item>
</group>
<group name="DIFFS_PAD">
<item name="IOATTRBOX" rev="3">
<attrib name="DIFF_SSTL2_I" value="1"/></item>
</group>
<group name="DIFFMI_PAD">
<item name="IOATTRBOX" rev="3">
<attrib name="DIFF_SSTL2_I" value="1"/></item>
</group>
<group name="SLICEM_WSGEN">
<item name="CK" rev="3">
<attrib name="CK" value="328"/><attrib name="CK_INV" value="225"/></item>
<item name="SYNC_ATTR" rev="3">
<attrib name="ASYNC" value="188"/></item>
<item name="WE" rev="3">
<attrib name="WE_INV" value="0"/><attrib name="WE" value="553"/></item>
</group>
<group name="SLICEM_FFX">
<item name="CE" rev="3">
<attrib name="CE" value="29"/><attrib name="CE_INV" value="0"/></item>
<item name="CK" rev="3">
<attrib name="CK" value="86"/><attrib name="CK_INV" value="38"/></item>
<item name="D" rev="3">
<attrib name="D" value="123"/><attrib name="D_INV" value="1"/></item>
<item name="FFX_INIT_ATTR" rev="3">
<attrib name="INIT0" value="124"/></item>
<item name="FFX_SR_ATTR" rev="3">
<attrib name="SRLOW" value="124"/></item>
<item name="LATCH_OR_FF" rev="3">
<attrib name="FF" value="124"/></item>
<item name="SYNC_ATTR" rev="3">
<attrib name="ASYNC" value="124"/></item>
</group>
<group name="SLICEM_FFY">
<item name="CE" rev="3">
<attrib name="CE" value="18"/><attrib name="CE_INV" value="0"/></item>
<item name="CK" rev="3">
<attrib name="CK" value="94"/><attrib name="CK_INV" value="43"/></item>
<item name="D" rev="3">
<attrib name="D" value="137"/><attrib name="D_INV" value="0"/></item>
<item name="FFY_INIT_ATTR" rev="3">
<attrib name="INIT0" value="137"/></item>
<item name="FFY_SR_ATTR" rev="3">
<attrib name="SRLOW" value="137"/></item>
<item name="LATCH_OR_FF" rev="3">
<attrib name="FF" value="137"/></item>
<item name="SYNC_ATTR" rev="3">
<attrib name="ASYNC" value="137"/></item>
</group>
<group name="DIFFM">
<item name="O1" rev="3">
<attrib name="O1_INV" value="0"/><attrib name="O1" value="1"/></item>
</group>
<group name="IOB_PAD">
<item name="DRIVEATTRBOX" rev="3">
<attrib name="4" value="10"/><attrib name="8" value="33"/><attrib name="12" value="22"/></item>
<item name="IOATTRBOX" rev="3">
<attrib name="SSTL2_I" value="40"/><attrib name="LVCMOS25" value="9"/><attrib name="LVCMOS33" value="56"/></item>
<item name="PULL" rev="3">
<attrib name="PULLUP" value="3"/></item>
<item name="SLEW" rev="3">
<attrib name="SLOW" value="65"/></item>
</group>
<group name="DIFFS">
<item name="O1" rev="3">
<attrib name="O1_INV" value="1"/><attrib name="O1" value="0"/></item>
</group>
<group name="IOB">
<item name="ICE" rev="3">
<attrib name="ICE" value="19"/><attrib name="ICE_INV" value="0"/></item>
<item name="ICLK1" rev="3">
<attrib name="ICLK1_INV" value="0"/><attrib name="ICLK1" value="53"/></item>
<item name="ICLK2" rev="3">
<attrib name="ICLK2_INV" value="18"/><attrib name="ICLK2" value="0"/></item>
<item name="O1" rev="3">
<attrib name="O1_INV" value="1"/><attrib name="O1" value="104"/></item>
<item name="O2" rev="3">
<attrib name="O2" value="20"/><attrib name="O2_INV" value="0"/></item>
<item name="OCE" rev="3">
<attrib name="OCE" value="20"/><attrib name="OCE_INV" value="0"/></item>
<item name="OTCLK1" rev="3">
<attrib name="OTCLK1_INV" value="18"/><attrib name="OTCLK1" value="22"/></item>
<item name="OTCLK2" rev="3">
<attrib name="OTCLK2_INV" value="20"/><attrib name="OTCLK2" value="0"/></item>
<item name="REV" rev="3">
<attrib name="REV_INV" value="0"/><attrib name="REV" value="18"/></item>
<item name="SR" rev="3">
<attrib name="SR" value="20"/><attrib name="SR_INV" value="0"/></item>
<item name="T1" rev="3">
<attrib name="T1_INV" value="0"/><attrib name="T1" value="77"/></item>
</group>
<group name="DCM_DCM">
<item name="CLKDV_DIVIDE" rev="3">
<attrib name="2" value="4"/></item>
<item name="CLKOUT_PHASE_SHIFT" rev="3">
<attrib name="NONE" value="1"/><attrib name="FIXED" value="1"/><attrib name="VARIABLE" value="2"/></item>
<item name="CLK_FEEDBACK" rev="3">
<attrib name="1X" value="3"/><attrib name="2X" value="1"/></item>
<item name="DESKEW_ADJUST" rev="3">
<attrib name="7" value="4"/></item>
<item name="DFS_FREQUENCY_MODE" rev="3">
<attrib name="LOW" value="4"/></item>
<item name="DLL_FREQUENCY_MODE" rev="3">
<attrib name="LOW" value="4"/></item>
<item name="DUTY_CYCLE_CORRECTION" rev="3">
<attrib name="TRUE" value="4"/></item>
<item name="FACTORY_JF1" rev="3">
<attrib name="0XC0" value="4"/></item>
<item name="FACTORY_JF2" rev="3">
<attrib name="0X80" value="4"/></item>
<item name="PSCLK" rev="3">
<attrib name="PSCLK_INV" value="2"/><attrib name="PSCLK" value="2"/></item>
<item name="PSEN" rev="3">
<attrib name="PSEN_INV" value="0"/><attrib name="PSEN" value="4"/></item>
<item name="PSINCDEC" rev="3">
<attrib name="PSINCDEC" value="4"/><attrib name="PSINCDEC_INV" value="0"/></item>
<item name="RST" rev="3">
<attrib name="RST" value="4"/><attrib name="RST_INV" value="0"/></item>
</group>
<group name="DIFFSI_PAD">
<item name="IOATTRBOX" rev="3">
<attrib name="DIFF_SSTL2_I" value="1"/></item>
</group>
<group name="BUFGMUX">
<item name="S" rev="3">
<attrib name="S_INV" value="7"/><attrib name="S" value="2"/></item>
</group>
<group name="DCM">
<item name="PSCLK" rev="3">
<attrib name="PSCLK_INV" value="2"/><attrib name="PSCLK" value="2"/></item>
<item name="PSEN" rev="3">
<attrib name="PSEN_INV" value="0"/><attrib name="PSEN" value="4"/></item>
<item name="PSINCDEC" rev="3">
<attrib name="PSINCDEC" value="4"/><attrib name="PSINCDEC_INV" value="0"/></item>
<item name="RST" rev="3">
<attrib name="RST" value="4"/><attrib name="RST_INV" value="0"/></item>
</group>
</ReportConfigData>
<ReportPinData TimeStamp="Tue Jul 28 15:44:06 2015"><group name="SLICEL_CYMUXF">
<item name="0" rev="3">
<attrib name="value" value="1073"/></item>
<item name="1" rev="3">
<attrib name="value" value="1073"/></item>
<item name="OUT" rev="3">
<attrib name="value" value="1073"/></item>
<item name="S0" rev="3">
<attrib name="value" value="1073"/></item>
</group>
<group name="SLICEL_CYMUXG">
<item name="0" rev="3">
<attrib name="value" value="982"/></item>
<item name="1" rev="3">
<attrib name="value" value="982"/></item>
<item name="OUT" rev="3">
<attrib name="value" value="982"/></item>
<item name="S0" rev="3">
<attrib name="value" value="982"/></item>
</group>
<group name="IBUF_PAD">
<item name="PAD" rev="3">
<attrib name="value" value="33"/></item>
</group>
<group name="DIFFS_OUTBUF">
<item name="IN" rev="3">
<attrib name="value" value="1"/></item>
<item name="OUTP" rev="3">
<attrib name="value" value="1"/></item>
</group>
<group name="IBUF_INBUF">
<item name="IN" rev="3">
<attrib name="value" value="33"/></item>
<item name="OUT" rev="3">
<attrib name="value" value="33"/></item>
</group>
<group name="IOB_IFD_DELAY">
<item name="IN" rev="3">
<attrib name="value" value="3"/></item>
<item name="OUT" rev="3">
<attrib name="value" value="3"/></item>
</group>
<group name="SLICEM_F">
<item name="A1" rev="3">
<attrib name="value" value="421"/></item>
<item name="A2" rev="3">
<attrib name="value" value="421"/></item>
<item name="A3" rev="3">
<attrib name="value" value="418"/></item>
<item name="A4" rev="3">
<attrib name="value" value="418"/></item>
<item name="D" rev="3">
<attrib name="value" value="421"/></item>
<item name="DI" rev="3">
<attrib name="value" value="416"/></item>
<item name="WF1" rev="3">
<attrib name="value" value="344"/></item>
<item name="WF2" rev="3">
<attrib name="value" value="344"/></item>
<item name="WF3" rev="3">
<attrib name="value" value="344"/></item>
<item name="WF4" rev="3">
<attrib name="value" value="344"/></item>
<item name="WS" rev="3">
<attrib name="value" value="416"/></item>
</group>
<group name="SLICEM_G">
<item name="A1" rev="3">
<attrib name="value" value="529"/></item>
<item name="A2" rev="3">
<attrib name="value" value="529"/></item>
<item name="A3" rev="3">
<attrib name="value" value="529"/></item>
<item name="A4" rev="3">
<attrib name="value" value="529"/></item>
<item name="D" rev="3">
<attrib name="value" value="265"/></item>
<item name="DI" rev="3">
<attrib name="value" value="553"/></item>
<item name="WG1" rev="3">
<attrib name="value" value="345"/></item>
<item name="WG2" rev="3">
<attrib name="value" value="345"/></item>
<item name="WG3" rev="3">
<attrib name="value" value="345"/></item>
<item name="WG4" rev="3">
<attrib name="value" value="345"/></item>
<item name="WS" rev="3">
<attrib name="value" value="553"/></item>
</group>
<group name="BUFGMUX_GCLK_BUFFER">
<item name="IN" rev="3">
<attrib name="value" value="9"/></item>
<item name="OUT" rev="3">
<attrib name="value" value="9"/></item>
</group>
<group name="IOB_OFFDDRBLACKBOX">
<item name="OFF1" rev="3">
<attrib name="value" value="20"/></item>
<item name="OFF2" rev="3">
<attrib name="value" value="20"/></item>
<item name="OFFDDR" rev="3">
<attrib name="value" value="20"/></item>
</group>
<group name="SLICEL">
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<attrib name="value" value="2295"/></item>
<item name="BY" rev="3">
<attrib name="value" value="2081"/></item>
<item name="CE" rev="3">
<attrib name="value" value="2376"/></item>
<item name="CIN" rev="3">
<attrib name="value" value="975"/></item>
<item name="CLK" rev="3">
<attrib name="value" value="4468"/></item>
<item name="COUT" rev="3">
<attrib name="value" value="982"/></item>
<item name="F1" rev="3">
<attrib name="value" value="4060"/></item>
<item name="F2" rev="3">
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<item name="F3" rev="3">
<attrib name="value" value="2826"/></item>
<item name="F4" rev="3">
<attrib name="value" value="1688"/></item>
<item name="F5" rev="3">
<attrib name="value" value="42"/></item>
<item name="FXINA" rev="3">
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<item name="FXINB" rev="3">
<attrib name="value" value="21"/></item>
<item name="G1" rev="3">
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<item name="G2" rev="3">
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<item name="G3" rev="3">
<attrib name="value" value="2793"/></item>
<item name="G4" rev="3">
<attrib name="value" value="1565"/></item>
<item name="SR" rev="3">
<attrib name="value" value="1030"/></item>
<item name="X" rev="3">
<attrib name="value" value="1868"/></item>
<item name="XB" rev="3">
<attrib name="value" value="16"/></item>
<item name="XQ" rev="3">
<attrib name="value" value="3641"/></item>
<item name="Y" rev="3">
<attrib name="value" value="1901"/></item>
<item name="YQ" rev="3">
<attrib name="value" value="3671"/></item>
</group>
<group name="SLICEM">
<item name="BX" rev="3">
<attrib name="value" value="78"/></item>
<item name="BY" rev="3">
<attrib name="value" value="553"/></item>
<item name="CE" rev="3">
<attrib name="value" value="41"/></item>
<item name="CLK" rev="3">
<attrib name="value" value="553"/></item>
<item name="F1" rev="3">
<attrib name="value" value="421"/></item>
<item name="F2" rev="3">
<attrib name="value" value="421"/></item>
<item name="F3" rev="3">
<attrib name="value" value="418"/></item>
<item name="F4" rev="3">
<attrib name="value" value="418"/></item>
<item name="G1" rev="3">
<attrib name="value" value="529"/></item>
<item name="G2" rev="3">
<attrib name="value" value="529"/></item>
<item name="G3" rev="3">
<attrib name="value" value="529"/></item>
<item name="G4" rev="3">
<attrib name="value" value="529"/></item>
<item name="SR" rev="3">
<attrib name="value" value="553"/></item>
<item name="X" rev="3">
<attrib name="value" value="340"/></item>
<item name="XQ" rev="3">
<attrib name="value" value="124"/></item>
<item name="Y" rev="3">
<attrib name="value" value="132"/></item>
<item name="YQ" rev="3">
<attrib name="value" value="137"/></item>
</group>
<group name="SLICEL_F6MUX">
<item name="0" rev="3">
<attrib name="value" value="21"/></item>
<item name="1" rev="3">
<attrib name="value" value="21"/></item>
<item name="OUT" rev="3">
<attrib name="value" value="21"/></item>
<item name="S0" rev="3">
<attrib name="value" value="21"/></item>
</group>
<group name="RAMB16">
<item name="ADDRA10" rev="3">
<attrib name="value" value="22"/></item>
<item name="ADDRA11" rev="3">
<attrib name="value" value="22"/></item>
<item name="ADDRA12" rev="3">
<attrib name="value" value="22"/></item>
<item name="ADDRA13" rev="3">
<attrib name="value" value="22"/></item>
<item name="ADDRA2" rev="3">
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<item name="ADDRA3" rev="3">
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<item name="ADDRA4" rev="3">
<attrib name="value" value="21"/></item>
<item name="ADDRA5" rev="3">
<attrib name="value" value="22"/></item>
<item name="ADDRA6" rev="3">
<attrib name="value" value="22"/></item>
<item name="ADDRA7" rev="3">
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<item name="ADDRA8" rev="3">
<attrib name="value" value="22"/></item>
<item name="ADDRA9" rev="3">
<attrib name="value" value="22"/></item>
<item name="ADDRB10" rev="3">
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<item name="ADDRB11" rev="3">
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<item name="ADDRB12" rev="3">
<attrib name="value" value="22"/></item>
<item name="ADDRB13" rev="3">
<attrib name="value" value="22"/></item>
<item name="ADDRB3" rev="3">
<attrib name="value" value="6"/></item>
<item name="ADDRB4" rev="3">
<attrib name="value" value="15"/></item>
<item name="ADDRB5" rev="3">
<attrib name="value" value="22"/></item>
<item name="ADDRB6" rev="3">
<attrib name="value" value="22"/></item>
<item name="ADDRB7" rev="3">
<attrib name="value" value="22"/></item>
<item name="ADDRB8" rev="3">
<attrib name="value" value="22"/></item>
<item name="ADDRB9" rev="3">
<attrib name="value" value="22"/></item>
<item name="CLKA" rev="3">
<attrib name="value" value="22"/></item>
<item name="CLKB" rev="3">
<attrib name="value" value="22"/></item>
<item name="DIA0" rev="3">
<attrib name="value" value="12"/></item>
<item name="DIA1" rev="3">
<attrib name="value" value="12"/></item>
<item name="DIA10" rev="3">
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<item name="DIA11" rev="3">
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<item name="DIA12" rev="3">
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<item name="DIA13" rev="3">
<attrib name="value" value="8"/></item>
<item name="DIA14" rev="3">
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<item name="DIA15" rev="3">
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<item name="DIA16" rev="3">
<attrib name="value" value="1"/></item>
<item name="DIA17" rev="3">
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<item name="DIA18" rev="3">
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<item name="DIA19" rev="3">
<attrib name="value" value="1"/></item>
<item name="DIA2" rev="3">
<attrib name="value" value="12"/></item>
<item name="DIA20" rev="3">
<attrib name="value" value="1"/></item>
<item name="DIA21" rev="3">
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<item name="DIA22" rev="3">
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<item name="DIA23" rev="3">
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<item name="DIA24" rev="3">
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<item name="DIA25" rev="3">
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<item name="DIA26" rev="3">
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<item name="DIA27" rev="3">
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<item name="DIA28" rev="3">
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<item name="DIA29" rev="3">
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<item name="DIA3" rev="3">
<attrib name="value" value="12"/></item>
<item name="DIA30" rev="3">
<attrib name="value" value="1"/></item>
<item name="DIA31" rev="3">
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<item name="DIA4" rev="3">
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<item name="DIA5" rev="3">
<attrib name="value" value="12"/></item>
<item name="DIA6" rev="3">
<attrib name="value" value="12"/></item>
<item name="DIA7" rev="3">
<attrib name="value" value="12"/></item>
<item name="DIA8" rev="3">
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<item name="DIA9" rev="3">
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<item name="DIB0" rev="3">
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<item name="DIB1" rev="3">
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<item name="DIB10" rev="3">
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<item name="DIB11" rev="3">
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<item name="DIB12" rev="3">
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<item name="DIB13" rev="3">
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<item name="DIB14" rev="3">
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<item name="DIB15" rev="3">
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<group name="SLICEM_GMC15_BLACKBOX">
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<attrib name="value" value="24"/></item>
<item name="WS2" rev="3">
<attrib name="value" value="24"/></item>
</group>
<group name="DIFFMI_PAD">
<item name="PAD" rev="3">
<attrib name="value" value="1"/></item>
</group>
<group name="SLICEM_WSGEN">
<item name="CK" rev="3">
<attrib name="value" value="553"/></item>
<item name="WE" rev="3">
<attrib name="value" value="553"/></item>
<item name="WSF" rev="3">
<attrib name="value" value="416"/></item>
<item name="WSG" rev="3">
<attrib name="value" value="553"/></item>
</group>
<group name="SLICEM_FFX">
<item name="CE" rev="3">
<attrib name="value" value="29"/></item>
<item name="CK" rev="3">
<attrib name="value" value="124"/></item>
<item name="D" rev="3">
<attrib name="value" value="124"/></item>
<item name="Q" rev="3">
<attrib name="value" value="124"/></item>
</group>
<group name="SLICEM_FFY">
<item name="CE" rev="3">
<attrib name="value" value="18"/></item>
<item name="CK" rev="3">
<attrib name="value" value="137"/></item>
<item name="D" rev="3">
<attrib name="value" value="137"/></item>
<item name="Q" rev="3">
<attrib name="value" value="137"/></item>
</group>
<group name="DIFFM">
<item name="O1" rev="3">
<attrib name="value" value="1"/></item>
<item name="PAD" rev="3">
<attrib name="value" value="1"/></item>
</group>
<group name="IOB_PAD">
<item name="PAD" rev="3">
<attrib name="value" value="105"/></item>
</group>
<group name="DIFFS">
<item name="O1" rev="3">
<attrib name="value" value="1"/></item>
<item name="PAD" rev="3">
<attrib name="value" value="1"/></item>
</group>
<group name="DIFFSI_PADOUT_USED">
<item name="0" rev="3">
<attrib name="value" value="1"/></item>
<item name="OUT" rev="3">
<attrib name="value" value="1"/></item>
</group>
<group name="SLICEL_C1VDD">
<item name="1" rev="3">
<attrib name="value" value="181"/></item>
</group>
<group name="IOB">
<item name="I" rev="3">
<attrib name="value" value="18"/></item>
<item name="ICE" rev="3">
<attrib name="value" value="19"/></item>
<item name="ICLK1" rev="3">
<attrib name="value" value="53"/></item>
<item name="ICLK2" rev="3">
<attrib name="value" value="18"/></item>
<item name="IQ1" rev="3">
<attrib name="value" value="53"/></item>
<item name="IQ2" rev="3">
<attrib name="value" value="18"/></item>
<item name="O1" rev="3">
<attrib name="value" value="105"/></item>
<item name="O2" rev="3">
<attrib name="value" value="20"/></item>
<item name="OCE" rev="3">
<attrib name="value" value="20"/></item>
<item name="OTCLK1" rev="3">
<attrib name="value" value="40"/></item>
<item name="OTCLK2" rev="3">
<attrib name="value" value="20"/></item>
<item name="PAD" rev="3">
<attrib name="value" value="105"/></item>
<item name="REV" rev="3">
<attrib name="value" value="18"/></item>
<item name="SR" rev="3">
<attrib name="value" value="20"/></item>
<item name="T1" rev="3">
<attrib name="value" value="77"/></item>
</group>
<group name="DCM_DCM">
<item name="CLK0" rev="3">
<attrib name="value" value="3"/></item>
<item name="CLK180" rev="3">
<attrib name="value" value="2"/></item>
<item name="CLK270" rev="3">
<attrib name="value" value="2"/></item>
<item name="CLK2X" rev="3">
<attrib name="value" value="2"/></item>
<item name="CLK2X180" rev="3">
<attrib name="value" value="1"/></item>
<item name="CLK90" rev="3">
<attrib name="value" value="2"/></item>
<item name="CLKFB" rev="3">
<attrib name="value" value="4"/></item>
<item name="CLKIN" rev="3">
<attrib name="value" value="4"/></item>
<item name="LOCKED" rev="3">
<attrib name="value" value="3"/></item>
<item name="PSCLK" rev="3">
<attrib name="value" value="4"/></item>
<item name="PSDONE" rev="3">
<attrib name="value" value="2"/></item>
<item name="PSEN" rev="3">
<attrib name="value" value="4"/></item>
<item name="PSINCDEC" rev="3">
<attrib name="value" value="4"/></item>
<item name="RST" rev="3">
<attrib name="value" value="4"/></item>
<item name="STATUS0" rev="3">
<attrib name="value" value="3"/></item>
<item name="STATUS1" rev="3">
<attrib name="value" value="1"/></item>
</group>
<group name="DIFFSI_PAD">
<item name="PAD" rev="3">
<attrib name="value" value="1"/></item>
</group>
<group name="BUFGMUX">
<item name="I0" rev="3">
<attrib name="value" value="9"/></item>
<item name="I1" rev="3">
<attrib name="value" value="2"/></item>
<item name="O" rev="3">
<attrib name="value" value="9"/></item>
<item name="S" rev="3">
<attrib name="value" value="9"/></item>
</group>
<group name="SLICEL_FAND">
<item name="0" rev="3">
<attrib name="value" value="45"/></item>
<item name="1" rev="3">
<attrib name="value" value="45"/></item>
<item name="O" rev="3">
<attrib name="value" value="45"/></item>
</group>
<group name="DCM">
<item name="CLK0" rev="3">
<attrib name="value" value="3"/></item>
<item name="CLK180" rev="3">
<attrib name="value" value="2"/></item>
<item name="CLK270" rev="3">
<attrib name="value" value="2"/></item>
<item name="CLK2X" rev="3">
<attrib name="value" value="2"/></item>
<item name="CLK2X180" rev="3">
<attrib name="value" value="1"/></item>
<item name="CLK90" rev="3">
<attrib name="value" value="2"/></item>
<item name="CLKFB" rev="3">
<attrib name="value" value="4"/></item>
<item name="CLKIN" rev="3">
<attrib name="value" value="4"/></item>
<item name="LOCKED" rev="3">
<attrib name="value" value="3"/></item>
<item name="PSCLK" rev="3">
<attrib name="value" value="4"/></item>
<item name="PSDONE" rev="3">
<attrib name="value" value="2"/></item>
<item name="PSEN" rev="3">
<attrib name="value" value="4"/></item>
<item name="PSINCDEC" rev="3">
<attrib name="value" value="4"/></item>
<item name="RST" rev="3">
<attrib name="value" value="4"/></item>
<item name="STATUS0" rev="3">
<attrib name="value" value="3"/></item>
<item name="STATUS1" rev="3">
<attrib name="value" value="1"/></item>
</group>
<group name="SLICEL_F">
<item name="A1" rev="3">
<attrib name="value" value="3986"/></item>
<item name="A2" rev="3">
<attrib name="value" value="3577"/></item>
<item name="A3" rev="3">
<attrib name="value" value="2826"/></item>
<item name="A4" rev="3">
<attrib name="value" value="1688"/></item>
<item name="D" rev="3">
<attrib name="value" value="4108"/></item>
</group>
<group name="SLICEL_G">
<item name="A1" rev="3">
<attrib name="value" value="4082"/></item>
<item name="A2" rev="3">
<attrib name="value" value="3682"/></item>
<item name="A3" rev="3">
<attrib name="value" value="2793"/></item>
<item name="A4" rev="3">
<attrib name="value" value="1565"/></item>
<item name="D" rev="3">
<attrib name="value" value="4211"/></item>
</group>
<group name="IBUF_IFD_DELAY">
<item name="IN" rev="3">
<attrib name="value" value="13"/></item>
<item name="OUT" rev="3">
<attrib name="value" value="13"/></item>
</group>
<group name="RAMB16_RAMB16">
<item name="ADDRA" rev="3">
<attrib name="value" value="22"/></item>
<item name="ADDRB" rev="3">
<attrib name="value" value="22"/></item>
<item name="DIA" rev="3">
<attrib name="value" value="22"/></item>
<item name="DIB" rev="3">
<attrib name="value" value="22"/></item>
<item name="DOA" rev="3">
<attrib name="value" value="22"/></item>
<item name="DOB" rev="3">
<attrib name="value" value="22"/></item>
</group>
<group name="SLICEL_GNDF">
<item name="0" rev="3">
<attrib name="value" value="405"/></item>
</group>
<group name="SLICEL_GNDG">
<item name="0" rev="3">
<attrib name="value" value="378"/></item>
</group>
</ReportPinData>
<CmdHistory>
</CmdHistory>
</DeviceUsageSummary>
control/dma_fifo353.v
View file @ f5c2e000
......@@ -84,6 +84,10 @@ module dma_fifo_sync ( clk, // system clock, 120MHz? (currentle negedge used)
reg firstclk; // generated 1-clk_long pulse as a source for swclk
reg written_burst; // 16 of 16-bit words are just written to FIFO
wire mem_re; // memory RE signal (alo increments counters)
//AF2015: Could not find any iob=true for this register, but it is still duplicated
// OK, it has only sync inputs, so no risk to have different values here and in the IOB
//FlipFlop i_dma_fifo0/dreq has been replicated 1 time(s) to handle iob=true attribute.
//FlipFlop i_dma_fifo1/dreq has been replicated 1 time(s) to handle iob=true attribute.
reg dreq;
reg [1:0] burst_start_sync; // 1 clk long pulse (clk-sync) after start of the DMA burst
reg [1:0] dack_r; // synchronize to clk, dual to prevent metastability
......
sensor/sensor_phase353.v
View file @ f5c2e000
......@@ -293,6 +293,10 @@ BUFGMUX i_pclk (.O(gclk_idata), .I0(dcm2x), .I1(dcm2x180), .S(inv_gclk_idata))
.IBUF_DELAY_VALUE (IBUF_DELAY_SENSOR_VHACT),
.IFD_DELAY_VALUE (IFD_DELAY_SENSOR_VHACT)
) i_vact (.I(VACT), .O(ivact));
// synthesis attribute IOB of i_hact is "TRUE"
// synthesis attribute IOB of i_vact is "TRUE"
always @ (posedge gclk_idata) begin
hact_q1 <= ihact00;
vact_q1 <= ivact00;
......@@ -333,6 +337,20 @@ BUFGMUX i_pclk (.O(gclk_idata), .I0(dcm2x), .I1(dcm2x180), .S(inv_gclk_idata))
FDCE i_idi_9 (.Q(idi[ 9]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[ 9]));
FDCE i_idi_10 (.Q(idi[10]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[10]));
FDCE i_idi_11 (.Q(idi[11]), .C(gclk_idata),.CE(en_idata),.CLR(1'b0),.D(DI[11]));
// are they still needed - seems yes
// synthesis attribute IOB of i_sync_alt_d0 is "TRUE"
// synthesis attribute IOB of i_idi_0 is "TRUE"
// synthesis attribute IOB of i_idi_1 is "TRUE"
// synthesis attribute IOB of i_idi_2 is "TRUE"
// synthesis attribute IOB of i_idi_3 is "TRUE"
// synthesis attribute IOB of i_idi_4 is "TRUE"
// synthesis attribute IOB of i_idi_5 is "TRUE"
// synthesis attribute IOB of i_idi_6 is "TRUE"
// synthesis attribute IOB of i_idi_7 is "TRUE"
// synthesis attribute IOB of i_idi_8 is "TRUE"
// synthesis attribute IOB of i_idi_9 is "TRUE"
// synthesis attribute IOB of i_idi_10 is "TRUE"
// synthesis attribute IOB of i_idi_11 is "TRUE"
reg [1:0] shact_zero; // shact was zero (inactive), sync to gclk_data
always @ (posedge gclk_idata) if (en_idata) begin
......
x353.v
View file @ f5c2e000
......@@ -71,8 +71,8 @@ module x353 #(
parameter SLEW_SENSOR_CLK = "SLOW",
parameter DRIVE_SENSOR_CLK = 4,
parameter IFD_DELAY_SENSOR_PXD = "0",
parameter IFD_DELAY_SENSOR_VHACT ="0",
parameter IFD_DELAY_SENSOR_PXD = "AUTO",
parameter IFD_DELAY_SENSOR_VHACT ="AUTO",
parameter IBUF_DELAY_SENSOR_PXD = "0",
parameter IBUF_DELAY_SENSOR_VHACT ="0",
......@@ -143,7 +143,8 @@ module x353 #(
output BG,
input BRIN,
output BROUT);
parameter MODELREV=32'h0353402b; // adding more bits to motors positions
parameter MODELREV=32'h03535000; // Trying ISE 14.7
// parameter MODELREV=32'h0353402b; // adding more bits to motors positions
// parameter MODELREV=32'h0353402a; // IMU restart after ready (DIO2)
// parameter MODELREV=32'h03534029; // working on IMU
// parameter MODELREV=32'h03534028; // DMA for logging, changing DMA control (neds drivers update)
......
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