making changes to match 393 simulation

.project

@@ -52,7 +52,7 @@
 		<link>
 			<name>ise_logs/ISExst.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x353/ise_logs/ISExst-20150728152838290.log</location>
+			<location>/home/andrey/git/x353/ise_logs/ISExst-20150729134023977.log</location>
 		</link>
 		<link>
 			<name>ise_state/x353-map.tgz</name>
@@ -72,7 +72,7 @@
 		<link>
 			<name>ise_state/x353-synth.tgz</name>
 			<type>1</type>
-			<location>/home/andrey/git/x353/ise_state/x353-synth-20150728152838290.tgz</location>
+			<location>/home/andrey/git/x353/ise_state/x353-synth-20150729134023977.tgz</location>
 		</link>
 	</linkedResources>
 </projectDescription>

.settings/com.elphel.vdt.iverilog.prefs

-com.elphel.store.context.iverilog=iverilog_100_TopModulesOther<-@\#\#@->iverilog_102_ExtraFiles<-@\#\#@->iverilog_103_IncludeDir<-@\#\#@->iverilog_117_GTKWaveSavFile<-@\#\#@->iverilog_96_Param_Exe<-@\#\#@->iverilog_97_VVP_Exe<-@\#\#@->iverilog_98_GtkWave_Exe<-@\#\#@->iverilog_108_ShowNoProblem<-@\#\#@->iverilog_111_SaveLogsPreprocessor<-@\#\#@->iverilog_112_SaveLogsSimulator<-@\#\#@->
+com.elphel.store.context.iverilog=iverilog_100_TopModulesOther<-@\#\#@->iverilog_102_ExtraFiles<-@\#\#@->iverilog_103_IncludeDir<-@\#\#@->iverilog_117_GTKWaveSavFile<-@\#\#@->iverilog_96_Param_Exe<-@\#\#@->iverilog_97_VVP_Exe<-@\#\#@->iverilog_98_GtkWave_Exe<-@\#\#@->iverilog_108_ShowNoProblem<-@\#\#@->iverilog_111_SaveLogsPreprocessor<-@\#\#@->iverilog_112_SaveLogsSimulator<-@\#\#@->iverilog_109_ShowNoProblem<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->
 eclipse.preferences.version=1
 iverilog_100_TopModulesOther=glbl<-@\#\#@->
+iverilog_101_TopModulesOther=glbl<-@\#\#@->
 iverilog_102_ExtraFiles=glbl.v<-@\#\#@->
+iverilog_103_ExtraFiles=glbl.v<-@\#\#@->
 iverilog_103_IncludeDir=${verilog_project_loc}/ddr<-@\#\#@->
+iverilog_104_IncludeDir=${verilog_project_loc}/ddr<-@\#\#@->
 iverilog_108_ShowNoProblem=true
+iverilog_109_ShowNoProblem=true
 iverilog_111_SaveLogsPreprocessor=true
 iverilog_112_SaveLogsSimulator=true
 iverilog_117_GTKWaveSavFile=${verilog_project_loc}/x353_1.sav

sensor/sensorpix353.v

@@ -419,13 +419,25 @@ module sensorpix(  pclk,                  // clock (==pclk)
       .SSRB(1'b0),                              // Port B Synchronous Set/Reset Input
       .WEB(1'b1)                                // Port B Write Enable Input
    );
+   
+   /// AF2015 *************** Fixing old bug - moved outside ******************
+/*   
+   reg [1:0] newline_d;
+   reg [1:0] linerun_d;
+   always @ (posedge pclk) begin
+       newline_d <= {newline_d[0],hact & ~hact_d[0]};
+       linerun_d <= {linerun_d[0],hact_d[1]};
+   end
+*/   
 lens_flat i_lens_flat(.sclk(sclk),                   /// system clock @negedge
                       .wen(we_lensff),               /// write LSW from di
                       .di(wd[15:0]),                 /// [15:0] data in
                       .pclk(pclk),                   /// pixel clock (@pclk)
                       .fstart(en && !en_d),          /// frame start - single clock (will have frame latency as coefficients are written after the fstart)
                       .newline(hact & ~hact_d[0]),    /// start of scan line  - ahead of linerun
+//                      .newline(newline_d[1]),    /// start of scan line  - ahead of linerun
                       .linerun(hact_d[1]),           /// active pixel output - latency will be = 3 clocks
+//                      .linerun(linerun_d[1]),           /// active pixel output - latency will be = 3 clocks
                       .bayer(bayer[1:0]),
                       .pixdi(pd_lenscorr_in[15:0]),  /// pixel data in,16 bit (normal data is positive, 15 bits)
                       .pixdo(pd_lenscorr_out[15:0])  /// pixel data out, same format as input

x353.v

@@ -976,8 +976,14 @@ rtc353 i_rtc353            (.mclk(sclk0),           // system clock (negedge)
                             .psec(psec[31:0]),      // [31:0] seconds counter output
                             .usec(running_usec[19:0]), // [19:0] running usec output
                             .sec(running_sec[31:0]));  //[31:0] running seconds counter output
+// AF2015 - delaying to match
+reg ihact_d;
+reg ihact_ts_d;
 
-
+always @ (posedge pclk) begin
+    ihact_d <=    ihact;
+    ihact_ts_d <= ihact_ts;
+end
 timestamp353 i_timestamp353(.mclk(sclk0),    // system clock (negedge)
                             .pre_we(da_timestamp),  // 1 cycle ahead of writing data
                             .wd(idi[1:0]),      // [31:0] data to write, valid 1 cycle after pre_we, wa
@@ -985,7 +991,8 @@ timestamp353 i_timestamp353(.mclk(sclk0),    // system clock (negedge)
                             .pxdi(ipxd[15:0]),  // [9:0] pixel data from sensor
                             .pxdo(ipxd_ts[15:0]),  // [9:0] data to replace pxdi (next cycle)
                             .vacts(vacts_every), // vertical sync (actual sensor)
-                            .hacti(ihact), // hact input
+//                            .hacti(ihact), // hact input
+                            .hacti(ihact_d), // hact input
                             .hacto(ihact_ts), // hact output (next cycle)
                             .sec(ts_sync_sec[31:0]),    // [31:0] number of seconds
                             .usec(ts_sync_usec[19:0]),    // [19:0] number of microseconds
@@ -1305,7 +1312,9 @@ sensorpix   i_sensorpix(
                    .hact_out(line_run),
 
 // sensor interface
-                   .hact(ihact_ts),       // line active
+//AF2015                   .hact(ihact_ts),       // line active
+                   .hact(ihact_ts_d),       // line active
+                   
                    .pxd(ipxd_ts[15:0]),      // [9:0] - 10 bit pixel data
 // channel 0 (data->SDRAM) interface
                    .dwe(sens_we),         // WE to SDRAM buffer

x353_1.tf

@@ -48,7 +48,7 @@ module testbench353();
     `include "IVERILOG_INCLUDE.v"
 `else
     initial $display("IVERILOG is not defined");
-    parameter lxtname = "x353_1.lxt";
+    parameter fstname = "x353_1.fst";
 `endif
 
 `ifdef SYNC_COMPRESS
@@ -513,8 +513,8 @@ defparam i_sensor12bits.trigdly = TRIG_LINES;   // delay between trigger input a
 
 
         initial begin
-//    $dumpfile("x353.lxt");
-    $dumpfile(lxtname);
+//    $dumpfile("x353.fst");
+    $dumpfile(fstname);
     $dumpvars(0,testbench353); //testbench353 cannot be resolved to a signal or parameter //SuppressThisWarning Veditor
             TTRIG = 1;
             CLK3 = 0;
@@ -964,7 +964,11 @@ end
 
 
 
-   cpu_wr('h4c,'h1);   // time stamp mode 1 (
+//AF2015   cpu_wr('h4c,'h1);   // time stamp mode 1 (
+   cpu_wr('h4c,'h0);   // time stamp mode off (not supported in 393!) (
+
+
+
 // +++++++++++ photofinish mode ++++++++++
 //   init_chan (0,0,1,1,'h200000,'h07,'h1f);  // 
 //   cpu_wr('h48,'h2);   //  time stamp mode 2
@@ -1136,7 +1140,7 @@ $display ("saturation=2");
 */
 
 
-
+// Lens flat field correction
    cpu_wr('h62,'h31000000); // [AX] => 0x0
    cpu_wr('h62,'h31080000); // [AY] => 0
    cpu_wr('h62,'h31108000); // [C] => 0x8000