debugging simulation

general/macros353.v

@@ -82,7 +82,7 @@ parameter DATA_2DEPTH=(1<<DATA_DEPTH)-1;
     assign	QR= ram[AR];
 endmodule
 
-// Fixing Xilinx SLR16_x
+// Modifying Xilinx SLR16_x to better simulate real hardware
 module SRL16_MOD #(
     parameter INIT = 16'h0000,
     parameter INVERT = 0 // *_1 - invert
@@ -100,9 +100,10 @@ module SRL16_MOD #(
     wire        clk_;
     wire  [3:0] a = {A3, A2, A1, A0};
 
+    assign Q = (|data) ? ((&data) ? 1'b1 : data[a]) :  1'b0 ;
 
-    assign Q = (data == 16'h0) ? 1'b0 :
-               ((data == 16'hffff) ? 1'b1 : data[a]);
+//    assign Q = (data == 16'h0) ? 1'b0 :
+//               ((data == 16'hffff) ? 1'b1 : data[a]);
     assign clk_ = INVERT? (~CLK) : CLK;
 
     initial

memctrl353/sdseq353.v

@@ -186,7 +186,6 @@ module sdseq (clk0,	// global clock 75-100MHz (hope to get to 120MHz with Sparta
      next <= prenext_refr || prenext_wr || (!drun_wr && pre_next_old); // add m0 and refr here too
      decLeft <= (prenext_m1s || prenext_m1d || prenext_m0); // add m0 and refr here too
      if (first) left[4:0] <= (mode)? 5'h14:((param[4:0]==5'b0)?5'h1f:param[4:0]);
-///AF2015 - revert:    	 if (first || rst) left[4:0] <= (mode)? 5'h14:((param[4:0]==5'b0)?5'h1f:param[4:0]);
      else if (decLeft)   left[4:0] <= left[4:0] -1;
    end