Commit 1bf7e77f authored by Andrey Filippov's avatar Andrey Filippov

starting compressor co-simulation with 393

parent 49896216
......@@ -65,8 +65,8 @@ module histogram (pclk, // pixel clock (posedge, only some input si
input di_vld_a;
input [ 1:0] bayer_phase;
parameter correct_bayer=2'b11; //AF2015: Correct Bayer to have histogram [2'b00] matcsh even row, even column data
parameter correct_bayer=2'b10; // 11; //AF2015: Correct Bayer to have histogram [2'b00] match even row, even column data
// for bayer_phase=0 correct_bayer=2'b10
wire [17:0] hist_do0;
// extra layer of registers
......
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......@@ -1124,7 +1124,7 @@ $display ("saturation=2");
cpu_wr('h62,'h0c000006); // mode - single
cpu_wr('h62, 'h4e000000 | 'h4 );// bayer=0
//AF2015 cpu_wr('h64, 'h4e000000 | 'h5 );// bayer=1
cpu_wr('h65, 'h4e000000 | 'h5 );// bayer=1 AF2015 - make it later to compare with 393
cpu_wr('h66, 'h4e000000 | 'h5 );// bayer=1 AF2015 - make it later to compare with 393
/*
AX(0x000000): writing 0x000000 to 0x31
......
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