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Commit d0d3b282 authored by Andrey Filippov's avatar Andrey Filippov
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added define of TRACE macro

parent c143e134
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tools/Verilog/IVerilog.xml
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...@@ -369,6 +369,7 @@ ...@@ -369,6 +369,7 @@
"%OutFileFull" "%OutFileFull"
</if-not> </if-not>
" -DIVERILOG" " -DIVERILOG"
" -DTRACE"
"%IVerilogOther" "%IVerilogOther"
"%Param_TopModule" "%Param_TopModule"
"%TopModulesOther" "%TopModulesOther"
......
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