fixed template

templates/verilog.xml

@@ -148,7 +148,7 @@ endmodule
     enabled="true"
     id="com.elphel.vdt.veditor.templates.verilog.newFile.GPL"
     name="Verilog GPL File"
->/!
+>/*!
  * <b>Module:</b> ${modulename}
  * @file ${modulename}.v
  * @date ${year}-${month}-${day}