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Elphel
vdt-plugin
Commits
a1fdf168
Commit
a1fdf168
authored
Feb 03, 2014
by
Andrey Filippov
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removed unisim_retarget_comp.v from copying, fixed spelling
parent
2a759855
Changes
4
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4 changed files
with
6 additions
and
6 deletions
+6
-6
DesignMenu.xml
tools/DesignMenu.xml
+1
-1
FPGA_project.xml
tools/FPGA_project.xml
+1
-1
vivado_synthesis.xml
tools/Xilinx/vivado_synthesis.xml
+2
-2
vivado_unisims.xml
tools/Xilinx/vivado_unisims.xml
+2
-2
No files found.
tools/DesignMenu.xml
View file @
a1fdf168
...
@@ -49,7 +49,7 @@
...
@@ -49,7 +49,7 @@
icon=
"my_tool.gif"
icon=
"my_tool.gif"
call=
"VivadoTest"
/>
call=
"VivadoTest"
/>
<menuitem
name=
"VivadoSynthesis"
<menuitem
name=
"VivadoSynthesis"
label=
"Synthesi
s
e design"
label=
"Synthesi
z
e design"
icon=
"xilinx.png"
icon=
"xilinx.png"
call=
"VivadoSynthesis"
/>
call=
"VivadoSynthesis"
/>
<menuitem
name=
"VivadoOptPlace"
<menuitem
name=
"VivadoOptPlace"
...
...
tools/FPGA_project.xml
View file @
a1fdf168
...
@@ -97,7 +97,7 @@
...
@@ -97,7 +97,7 @@
readonly=
"false"
/>
readonly=
"false"
/>
<parameter
id=
"SimulationTopModule"
label=
"Simulation top module"
tooltip=
"Project top simulation module"
<parameter
id=
"SimulationTopModule"
label=
"Simulation top module"
tooltip=
"Project top simulation module"
type=
"String"
default=
""
format=
"CopyValue"
readonly=
"false"
/>
type=
"String"
default=
""
format=
"CopyValue"
readonly=
"false"
/>
<parameter
id=
"ImplementationTopFile"
label=
"Implementation top
modu
le"
tooltip=
"Project file with top implementation module"
<parameter
id=
"ImplementationTopFile"
label=
"Implementation top
fi
le"
tooltip=
"Project file with top implementation module"
type=
"Filename"
default=
""
format=
"CopyValue"
readonly=
"false"
/>
type=
"Filename"
default=
""
format=
"CopyValue"
readonly=
"false"
/>
<parameter
id=
"SimulDir"
label=
"Simulation directory"
tooltip=
"Project simulation directory"
<parameter
id=
"SimulDir"
label=
"Simulation directory"
tooltip=
"Project simulation directory"
type=
"Pathname"
default=
"simulation"
format=
"CopyValue"
readonly=
"false"
/>
type=
"Pathname"
default=
"simulation"
format=
"CopyValue"
readonly=
"false"
/>
...
...
tools/Xilinx/vivado_synthesis.xml
View file @
a1fdf168
...
@@ -49,7 +49,7 @@
...
@@ -49,7 +49,7 @@
</typedef>
</typedef>
</interface>
</interface>
<tool
name=
"VivadoSynthesis"
label=
"Load Source files to Vivado and Synthesi
s
e"
<tool
name=
"VivadoSynthesis"
label=
"Load Source files to Vivado and Synthesi
z
e"
project=
"FPGA_project"
project=
"FPGA_project"
interface=
"VivadoSynthesisInterface"
interface=
"VivadoSynthesisInterface"
package=
"FPGA_package"
package=
"FPGA_package"
...
@@ -62,7 +62,7 @@
...
@@ -62,7 +62,7 @@
</extensions-list>
</extensions-list>
<action-menu>
<action-menu>
<action
label=
"Synthesi
s
e with Vivado:"
resource=
"%ImplementationTopFile"
<action
label=
"Synthesi
z
e with Vivado:"
resource=
"%ImplementationTopFile"
check-extension=
"false"
check-existence=
"true"
icon=
"xilinx.png"
/>
check-extension=
"false"
check-existence=
"true"
icon=
"xilinx.png"
/>
<action
label=
"Check by Vivado Synthesis:"
resource=
"%%SelectedFile"
<action
label=
"Check by Vivado Synthesis:"
resource=
"%%SelectedFile"
check-extension=
"true"
check-existence=
"true"
icon=
"sample.gif"
/>
check-extension=
"true"
check-existence=
"true"
icon=
"sample.gif"
/>
...
...
tools/Xilinx/vivado_unisims.xml
View file @
a1fdf168
...
@@ -22,9 +22,9 @@
...
@@ -22,9 +22,9 @@
"rsync -avr -e ssh"
"rsync -avr -e ssh"
"%RemoteUser@%RemoteHost:%VivadoUnisimsAbsolutePath/unisims"
"%RemoteUser@%RemoteHost:%VivadoUnisimsAbsolutePath/unisims"
"./;"
"./;"
"rsync -avr -e ssh"
<!--
"rsync -avr -e ssh"
"%RemoteUser@%RemoteHost:%VivadoUnisimsAbsolutePath/unisim_retarget_comp.v"
"%RemoteUser@%RemoteHost:%VivadoUnisimsAbsolutePath/unisim_retarget_comp.v"
"unisims ;"
"unisims ;"
-->
</line>
</line>
</output>
</output>
</tool>
</tool>
...
...
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