Commit 72dd6bd8 authored by Oleg Dzhimiev's avatar Oleg Dzhimiev

bitstream linking

parent 72dc2a87
...@@ -16,8 +16,10 @@ ifconfig eth0 192.168.0.9 ...@@ -16,8 +16,10 @@ ifconfig eth0 192.168.0.9
cd /usr/local/verilog/ cd /usr/local/verilog/
if [ $SENSOR_TYPE -eq 5 ]; then if [ $SENSOR_TYPE -eq 5 ]; then
/usr/local/bin/test_mcntrl.py @startup5 >> /dev/null 2>&1 & /usr/local/bin/test_mcntrl.py @startup5 >> /dev/null 2>&1 &
ln -sf /usr/local/verilog/x393_parallel.bit /usr/local/verilog/x393.bit
else else
/usr/local/bin/test_mcntrl.py @startup14 >> /dev/null 2>&1 & /usr/local/bin/test_mcntrl.py @startup14 >> /dev/null 2>&1 &
ln -sf /usr/local/verilog/x393_hispi.bit /usr/local/verilog/x393.bit
fi fi
sleep 10 sleep 10
......
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