Commit 72dd6bd8 authored by Oleg Dzhimiev's avatar Oleg Dzhimiev

bitstream linking

parent 72dc2a87
......@@ -16,8 +16,10 @@ ifconfig eth0 192.168.0.9
cd /usr/local/verilog/
if [ $SENSOR_TYPE -eq 5 ]; then
/usr/local/bin/test_mcntrl.py @startup5 >> /dev/null 2>&1 &
ln -sf /usr/local/verilog/x393_parallel.bit /usr/local/verilog/x393.bit
else
/usr/local/bin/test_mcntrl.py @startup14 >> /dev/null 2>&1 &
ln -sf /usr/local/verilog/x393_hispi.bit /usr/local/verilog/x393.bit
fi
sleep 10
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment