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Elphel
linux-elphel
Commits
592cdda2
Commit
592cdda2
authored
Apr 06, 2018
by
Oleg Dzhimiev
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changes for triggered mode. part 1
parent
5dd588f5
Changes
2
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with
7 additions
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1 deletion
+7
-1
mt9f002.c
src/drivers/elphel/mt9f002.c
+5
-0
mt9f002.h
src/drivers/elphel/mt9f002.h
+2
-1
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src/drivers/elphel/mt9f002.c
View file @
592cdda2
...
@@ -337,6 +337,11 @@ int mt9f002_pgm_detectsensor (int sensor_port, ///< sensor port
...
@@ -337,6 +337,11 @@ int mt9f002_pgm_detectsensor (int sensor_port, ///< sensor port
sensio_ctl
.
d32
=
0
;
sensio_ctl
.
d32
=
0
;
sensio_ctl
.
aro
=
1
;
sensio_ctl
.
aro
=
1
;
sensio_ctl
.
aro_set
=
1
;
sensio_ctl
.
aro_set
=
1
;
// trigger bits
sensio_ctl
.
gp0_set
=
1
;
sensio_ctl
.
gp0
=
0x3
;
// normal iaro - 'active low'
sensio_ctl
.
gp1_set
=
1
;
sensio_ctl
.
gp1
=
0x3
;
// inverted iaro - 'active high'
x393_sensio_ctrl
(
sensio_ctl
,
sensor_port
);
x393_sensio_ctrl
(
sensio_ctl
,
sensor_port
);
return
sensor
->
sensorType
;
return
sensor
->
sensorType
;
...
...
src/drivers/elphel/mt9f002.h
View file @
592cdda2
...
@@ -22,7 +22,8 @@
...
@@ -22,7 +22,8 @@
// bit 9 should have set masking for broken frames
// bit 9 should have set masking for broken frames
// cleared bit 3 allows writing to some RO registers
// cleared bit 3 allows writing to some RO registers
#define MT9F002_RESET_REGISTER_VALUE 0x001c
//#define MT9F002_RESET_REGISTER_VALUE 0x001c
#define MT9F002_RESET_REGISTER_VALUE 0x0011c
//#define MT9F002_RESET_REGISTER_VALUE 0x0014
//#define MT9F002_RESET_REGISTER_VALUE 0x0014
// number of lines to sacrifice before generating Frame Valid
// number of lines to sacrifice before generating Frame Valid
#define MT9F002_VACT_DELAY 2
#define MT9F002_VACT_DELAY 2
...
...
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