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Elphel
kicad-source-mirror
Commits
eaa147c1
Commit
eaa147c1
authored
Jan 26, 2008
by
dickelbeck
Browse files
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Plain Diff
spelling errors, specctra work
parent
501fb2c2
Changes
13
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13 changed files
with
612 additions
and
386 deletions
+612
-386
change_log.txt
change_log.txt
+19
-18
pcbstruct.h
include/pcbstruct.h
+13
-13
classpcb.cpp
pcbnew/classpcb.cpp
+5
-4
dialog_track_options.cpp
pcbnew/dialog_track_options.cpp
+355
-212
edit.cpp
pcbnew/edit.cpp
+2
-2
initpcb.cpp
pcbnew/initpcb.cpp
+3
-3
ioascii.cpp
pcbnew/ioascii.cpp
+4
-4
onrightclick.cpp
pcbnew/onrightclick.cpp
+5
-5
pcbcfg.cpp
pcbnew/pcbcfg.cpp
+3
-3
pcbframe.cpp
pcbnew/pcbframe.cpp
+5
-5
specctra.h
pcbnew/specctra.h
+1
-3
specctra_export.cpp
pcbnew/specctra_export.cpp
+191
-114
todo.txt
todo.txt
+6
-0
No files found.
change_log.txt
View file @
eaa147c1
...
@@ -8,28 +8,29 @@ email address.
...
@@ -8,28 +8,29 @@ email address.
2008-Jan-25 UPDATE Dick Hollenbeck <dick@softplc.com>
2008-Jan-25 UPDATE Dick Hollenbeck <dick@softplc.com>
================================================================================
================================================================================
+pcbnew:
+pcbnew:
SPECCTRA export does padstacks ok, except that oval
arcs need to be split
* SPECCTRA export does padstacks ok, except that oval pad's
arcs need to be split
into quarter circle arcs, and no consideration is given to "layer types"
into quarter circle arcs, and no consideration is given to "layer types"
.
See page bottom of page 74 of the SECCTRA Design Language Reference, May 2000.
See page bottom of page 74 of the SECCTRA Design Language Reference, May 2000.
Still working today...
* HISTORY_NUMBER was spelt with a zero.
* Width was spelt as Widht
2008-Jan-25 UPDATE Jean-Pierre Charras <jean-pierre.charras@inpg.fr>
2008-Jan-25 UPDATE Jean-Pierre Charras <jean-pierre.charras@inpg.fr>
================================================================================
================================================================================
+pcbnew:
+pcbnew:
- void Change_Side_Module( MODULE* Module, wxDC* DC ) is now member of class BOARD.
- void Change_Side_Module( MODULE* Module, wxDC* DC ) is now member of class BOARD.
- Better support for micro vias and buried vias (drill files now are useable for board manufacturers)
- Better support for micro vias and buried vias (drill files now are useable for board manufacturers)
But not yet tested by a board manufacturer. Be carefull.
But not yet tested by a board manufacturer. Be carefull.
Todo: tools to conversion between via through and buried via and buried viad optimisation.
Todo: tools to conversion between via through and buried via and buried viad optimisation.
But must works for micro vias (needed for my next board)
But must works for micro vias (needed for my next board)
(in pcbnew micro vias are blind vias between 2 adjacent layers: micro vias must be enabled
(in pcbnew micro vias are blind vias between 2 adjacent layers: micro vias must be enabled
in Dimensions/track and via menu, and placed by ctrl v.
in Dimensions/track and via menu, and placed by ctrl v.
They are intended to connect small pitch BGA pins to the inner layer, and can be drilled by laser
They are intended to connect small pitch BGA pins to the inner layer, and can be drilled by laser
if the hole diameter is small < 0.2mm. A laser can only drill a hole between 2 adjacent layers ).
if the hole diameter is small < 0.2mm. A laser can only drill a hole between 2 adjacent layers ).
** Currently use buried via for tests only, not for production **.
** Currently use buried via for tests only, not for production **.
2008-Jan-24 UPDATE Dick Hollenbeck <dick@softplc.com>
2008-Jan-24 UPDATE Dick Hollenbeck <dick@softplc.com>
================================================================================
================================================================================
...
@@ -45,8 +46,8 @@ email address.
...
@@ -45,8 +46,8 @@ email address.
2008-Jan-24 UPDATE Jean-Pierre Charras <jean-pierre.charras@inpg.fr>
2008-Jan-24 UPDATE Jean-Pierre Charras <jean-pierre.charras@inpg.fr>
================================================================================
================================================================================
+pcbnew:
+pcbnew:
Bugs about fill zones removed (not all, of course).
Bugs about fill zones removed (not all, of course).
Fixed an old bug in block delete (could crashes pcbnew after deleting footprints).
Fixed an old bug in block delete (could crashes pcbnew after deleting footprints).
2008-Jan-23 UPDATE Dick Hollenbeck <dick@softplc.com>
2008-Jan-23 UPDATE Dick Hollenbeck <dick@softplc.com>
================================================================================
================================================================================
...
...
include/pcbstruct.h
View file @
eaa147c1
/**************************************************************/
/**************************************************************/
/*
pcbstruct.h : definition des structures de donnees type PCB */
/*
pcbstruct.h : definition des structures de donnees type PCB */
/**************************************************************/
/**************************************************************/
#ifndef PCBSTRUCT_H
#ifndef PCBSTRUCT_H
...
@@ -144,7 +144,7 @@ struct CHEVELU;
...
@@ -144,7 +144,7 @@ struct CHEVELU;
#include "class_board.h"
#include "class_board.h"
// Class for handle current printed board design settings
// Class for handle current printed board design settings
#define HIST
0
RY_NUMBER 8
#define HIST
O
RY_NUMBER 8
class
EDA_BoardDesignSettings
class
EDA_BoardDesignSettings
{
{
public
:
public
:
...
@@ -153,11 +153,11 @@ public:
...
@@ -153,11 +153,11 @@ public:
int
m_MicroViaDrill
;
// micro via drill (for the entire board)
int
m_MicroViaDrill
;
// micro via drill (for the entire board)
int
m_CurrentViaSize
;
// Current via size
int
m_CurrentViaSize
;
// Current via size
int
m_CurrentMicroViaSize
;
// Current micro via size
int
m_CurrentMicroViaSize
;
// Current micro via size
bool
m_MicroViasAllowed
;
// true to allow micro vias
bool
m_MicroViasAllowed
;
// true to allow micro vias
int
m_ViaSizeHistory
[
HIST
0RY_NUMBER
];
// Last HIST0
RY_NUMBER used via sizes
int
m_ViaSizeHistory
[
HIST
ORY_NUMBER
];
// Last HISTO
RY_NUMBER used via sizes
int
m_CurrentViaType
;
// via type (BLIND, TROUGHT ...), bits 1 and 2 (not 0 and 1)
int
m_CurrentViaType
;
// via type (BLIND, TROUGHT ...), bits 1 and 2 (not 0 and 1)
int
m_CurrentTrackWidth
;
// current track width
int
m_CurrentTrackWidth
;
// current track width
int
m_TrackWid
htHistory
[
HIST0RY_NUMBER
];
// Last HIST0
RY_NUMBER used track widths
int
m_TrackWid
thHistory
[
HISTORY_NUMBER
];
// Last HISTO
RY_NUMBER used track widths
int
m_DrawSegmentWidth
;
// current graphic line width (not EDGE layer)
int
m_DrawSegmentWidth
;
// current graphic line width (not EDGE layer)
int
m_EdgeSegmentWidth
;
// current graphic line width (EDGE layer only)
int
m_EdgeSegmentWidth
;
// current graphic line width (EDGE layer only)
int
m_PcbTextWidth
;
// current Pcb (not module) Text width
int
m_PcbTextWidth
;
// current Pcb (not module) Text width
...
@@ -226,13 +226,13 @@ public:
...
@@ -226,13 +226,13 @@ public:
*/
*/
BOARD_ITEM
*
GetCurItem
()
const
{
return
(
BOARD_ITEM
*
)
BASE_SCREEN
::
GetCurItem
();
}
BOARD_ITEM
*
GetCurItem
()
const
{
return
(
BOARD_ITEM
*
)
BASE_SCREEN
::
GetCurItem
();
}
/* Return true if a microvia can be put on board
/* Return true if a microvia can be put on board
* A microvia ia a small via restricted to 2 near neighbour layers
* A microvia ia a small via restricted to 2 near neighbour layers
* because its is hole is made by laser which can penetrate only one layer
* because its is hole is made by laser which can penetrate only one layer
* It is mainly used to connect BGA to the first inner layer
* It is mainly used to connect BGA to the first inner layer
* And it is allowed from an external layer to the first inner layer
* And it is allowed from an external layer to the first inner layer
*/
*/
bool
IsMicroViaAcceptable
(
void
);
bool
IsMicroViaAcceptable
(
void
);
};
};
/**********************************/
/**********************************/
...
@@ -240,9 +240,9 @@ public:
...
@@ -240,9 +240,9 @@ public:
/**********************************/
/**********************************/
#include "class_pad.h" // class for pads
#include "class_pad.h" // class for pads
#include "class_edge_mod.h"
// Class for footprint graphic elements
#include "class_edge_mod.h"
// Class for footprint graphic elements
#include "class_text_mod.h"
// Class for footprint fields
#include "class_text_mod.h"
// Class for footprint fields
#include "class_module.h"
// Class for the footprint
#include "class_module.h"
// Class for the footprint
#include "class_equipot.h"
#include "class_equipot.h"
...
...
pcbnew/classpcb.cpp
View file @
eaa147c1
...
@@ -127,7 +127,8 @@ EDA_BoardDesignSettings::EDA_BoardDesignSettings()
...
@@ -127,7 +127,8 @@ EDA_BoardDesignSettings::EDA_BoardDesignSettings()
// Default values for designing boards
// Default values for designing boards
{
{
int
ii
;
int
ii
;
int
default_layer_color
[
32
]
=
{
static
const
int
default_layer_color
[
32
]
=
{
GREEN
,
LIGHTGRAY
,
LIGHTGRAY
,
LIGHTGRAY
,
GREEN
,
LIGHTGRAY
,
LIGHTGRAY
,
LIGHTGRAY
,
LIGHTGRAY
,
LIGHTGRAY
,
LIGHTGRAY
,
LIGHTGRAY
,
LIGHTGRAY
,
LIGHTGRAY
,
LIGHTGRAY
,
LIGHTGRAY
,
LIGHTGRAY
,
LIGHTGRAY
,
LIGHTGRAY
,
LIGHTGRAY
,
LIGHTGRAY
,
LIGHTGRAY
,
LIGHTGRAY
,
LIGHTGRAY
,
...
@@ -150,10 +151,10 @@ EDA_BoardDesignSettings::EDA_BoardDesignSettings()
...
@@ -150,10 +151,10 @@ EDA_BoardDesignSettings::EDA_BoardDesignSettings()
m_CurrentViaSize
=
450
;
// Current via size
m_CurrentViaSize
=
450
;
// Current via size
m_CurrentViaType
=
VIA_THROUGH
;
/* via type (BLIND, TROUGHT ...), bits 1 and 2 (not 0 and 1)*/
m_CurrentViaType
=
VIA_THROUGH
;
/* via type (BLIND, TROUGHT ...), bits 1 and 2 (not 0 and 1)*/
m_CurrentTrackWidth
=
170
;
// current track width
m_CurrentTrackWidth
=
170
;
// current track width
for
(
ii
=
0
;
ii
<
HIST
0
RY_NUMBER
;
ii
++
)
for
(
ii
=
0
;
ii
<
HIST
O
RY_NUMBER
;
ii
++
)
{
{
m_TrackWid
htHistory
[
ii
]
=
0
;
// Last HIST0
RY_NUMBER used track widths
m_TrackWid
thHistory
[
ii
]
=
0
;
// Last HISTO
RY_NUMBER used track widths
m_ViaSizeHistory
[
ii
]
=
0
;
// Last HIST
0
RY_NUMBER used via sizes
m_ViaSizeHistory
[
ii
]
=
0
;
// Last HIST
O
RY_NUMBER used via sizes
}
}
m_DrawSegmentWidth
=
100
;
// current graphic line width (not EDGE layer)
m_DrawSegmentWidth
=
100
;
// current graphic line width (not EDGE layer)
...
...
pcbnew/dialog_track_options.cpp
View file @
eaa147c1
This diff is collapsed.
Click to expand it.
pcbnew/edit.cpp
View file @
eaa147c1
...
@@ -829,7 +829,7 @@ void WinEDA_PcbFrame::Process_Special_Functions( wxCommandEvent& event )
...
@@ -829,7 +829,7 @@ void WinEDA_PcbFrame::Process_Special_Functions( wxCommandEvent& event )
case
ID_AUX_TOOLBAR_PCB_TRACK_WIDTH
:
case
ID_AUX_TOOLBAR_PCB_TRACK_WIDTH
:
{
{
int
ii
=
m_SelTrackWidthBox
->
GetChoice
();
int
ii
=
m_SelTrackWidthBox
->
GetChoice
();
g_DesignSettings
.
m_CurrentTrackWidth
=
g_DesignSettings
.
m_TrackWid
ht
History
[
ii
];
g_DesignSettings
.
m_CurrentTrackWidth
=
g_DesignSettings
.
m_TrackWid
th
History
[
ii
];
DisplayTrackSettings
();
DisplayTrackSettings
();
m_SelTrackWidthBox_Changed
=
FALSE
;
m_SelTrackWidthBox_Changed
=
FALSE
;
m_SelViaSizeBox_Changed
=
FALSE
;
m_SelViaSizeBox_Changed
=
FALSE
;
...
@@ -847,7 +847,7 @@ void WinEDA_PcbFrame::Process_Special_Functions( wxCommandEvent& event )
...
@@ -847,7 +847,7 @@ void WinEDA_PcbFrame::Process_Special_Functions( wxCommandEvent& event )
DrawPanel
->
MouseToCursorSchema
();
DrawPanel
->
MouseToCursorSchema
();
{
{
int
ii
=
id
-
ID_POPUP_PCB_SELECT_WIDTH1
;
int
ii
=
id
-
ID_POPUP_PCB_SELECT_WIDTH1
;
g_DesignSettings
.
m_CurrentTrackWidth
=
g_DesignSettings
.
m_TrackWid
ht
History
[
ii
];
g_DesignSettings
.
m_CurrentTrackWidth
=
g_DesignSettings
.
m_TrackWid
th
History
[
ii
];
DisplayTrackSettings
();
DisplayTrackSettings
();
}
}
break
;
break
;
...
...
pcbnew/initpcb.cpp
View file @
eaa147c1
...
@@ -192,13 +192,13 @@ bool WinEDA_BasePcbFrame::Clear_Pcb( bool query )
...
@@ -192,13 +192,13 @@ bool WinEDA_BasePcbFrame::Clear_Pcb( bool query )
g_HightLigt_Status
=
0
;
g_HightLigt_Status
=
0
;
for
(
int
ii
=
1
;
ii
<
HIST
0
RY_NUMBER
;
ii
++
)
for
(
int
ii
=
1
;
ii
<
HIST
O
RY_NUMBER
;
ii
++
)
{
{
g_DesignSettings
.
m_ViaSizeHistory
[
ii
]
=
g_DesignSettings
.
m_ViaSizeHistory
[
ii
]
=
g_DesignSettings
.
m_TrackWid
ht
History
[
ii
]
=
0
;
g_DesignSettings
.
m_TrackWid
th
History
[
ii
]
=
0
;
}
}
g_DesignSettings
.
m_TrackWid
ht
History
[
0
]
=
g_DesignSettings
.
m_CurrentTrackWidth
;
g_DesignSettings
.
m_TrackWid
th
History
[
0
]
=
g_DesignSettings
.
m_CurrentTrackWidth
;
g_DesignSettings
.
m_ViaSizeHistory
[
0
]
=
g_DesignSettings
.
m_CurrentViaSize
;
g_DesignSettings
.
m_ViaSizeHistory
[
0
]
=
g_DesignSettings
.
m_CurrentViaSize
;
Zoom_Automatique
(
TRUE
);
Zoom_Automatique
(
TRUE
);
...
...
pcbnew/ioascii.cpp
View file @
eaa147c1
...
@@ -519,12 +519,12 @@ static int WriteSetup( FILE* File, WinEDA_BasePcbFrame* frame )
...
@@ -519,12 +519,12 @@ static int WriteSetup( FILE* File, WinEDA_BasePcbFrame* frame )
fprintf
(
File
,
"Layers %d
\n
"
,
g_DesignSettings
.
m_CopperLayerCount
);
fprintf
(
File
,
"Layers %d
\n
"
,
g_DesignSettings
.
m_CopperLayerCount
);
fprintf
(
File
,
"TrackWidth %d
\n
"
,
g_DesignSettings
.
m_CurrentTrackWidth
);
fprintf
(
File
,
"TrackWidth %d
\n
"
,
g_DesignSettings
.
m_CurrentTrackWidth
);
for
(
ii
=
0
;
ii
<
HIST
0
RY_NUMBER
;
ii
++
)
for
(
ii
=
0
;
ii
<
HIST
O
RY_NUMBER
;
ii
++
)
{
{
if
(
g_DesignSettings
.
m_TrackWid
ht
History
[
ii
]
==
0
)
if
(
g_DesignSettings
.
m_TrackWid
th
History
[
ii
]
==
0
)
break
;
break
;
fprintf
(
File
,
"TrackWidthHistory %d
\n
"
,
fprintf
(
File
,
"TrackWidthHistory %d
\n
"
,
g_DesignSettings
.
m_TrackWid
ht
History
[
ii
]
);
g_DesignSettings
.
m_TrackWid
th
History
[
ii
]
);
}
}
fprintf
(
File
,
"TrackClearence %d
\n
"
,
g_DesignSettings
.
m_TrackClearence
);
fprintf
(
File
,
"TrackClearence %d
\n
"
,
g_DesignSettings
.
m_TrackClearence
);
...
@@ -534,7 +534,7 @@ static int WriteSetup( FILE* File, WinEDA_BasePcbFrame* frame )
...
@@ -534,7 +534,7 @@ static int WriteSetup( FILE* File, WinEDA_BasePcbFrame* frame )
fprintf
(
File
,
"EdgeSegmWidth %d
\n
"
,
g_DesignSettings
.
m_EdgeSegmentWidth
);
fprintf
(
File
,
"EdgeSegmWidth %d
\n
"
,
g_DesignSettings
.
m_EdgeSegmentWidth
);
fprintf
(
File
,
"ViaSize %d
\n
"
,
g_DesignSettings
.
m_CurrentViaSize
);
fprintf
(
File
,
"ViaSize %d
\n
"
,
g_DesignSettings
.
m_CurrentViaSize
);
fprintf
(
File
,
"ViaDrill %d
\n
"
,
g_DesignSettings
.
m_ViaDrill
);
fprintf
(
File
,
"ViaDrill %d
\n
"
,
g_DesignSettings
.
m_ViaDrill
);
for
(
ii
=
0
;
ii
<
HIST
0
RY_NUMBER
;
ii
++
)
for
(
ii
=
0
;
ii
<
HIST
O
RY_NUMBER
;
ii
++
)
{
{
if
(
g_DesignSettings
.
m_ViaSizeHistory
[
ii
]
==
0
)
if
(
g_DesignSettings
.
m_ViaSizeHistory
[
ii
]
==
0
)
break
;
break
;
...
...
pcbnew/onrightclick.cpp
View file @
eaa147c1
...
@@ -71,12 +71,12 @@ static wxMenu* Append_Track_Width_List()
...
@@ -71,12 +71,12 @@ static wxMenu* Append_Track_Width_List()
double
value
;
double
value
;
trackwidth_menu
=
new
wxMenu
;
trackwidth_menu
=
new
wxMenu
;
for
(
ii
=
0
;
(
ii
<
HIST
0
RY_NUMBER
)
&&
(
ii
<
TRACK_HISTORY_NUMBER_MAX
);
ii
++
)
for
(
ii
=
0
;
(
ii
<
HIST
O
RY_NUMBER
)
&&
(
ii
<
TRACK_HISTORY_NUMBER_MAX
);
ii
++
)
{
{
if
(
g_DesignSettings
.
m_TrackWid
ht
History
[
ii
]
==
0
)
if
(
g_DesignSettings
.
m_TrackWid
th
History
[
ii
]
==
0
)
break
;
break
;
value
=
To_User_Unit
(
g_UnitMetric
,
value
=
To_User_Unit
(
g_UnitMetric
,
g_DesignSettings
.
m_TrackWid
ht
History
[
ii
],
g_DesignSettings
.
m_TrackWid
th
History
[
ii
],
PCB_INTERNAL_UNIT
);
PCB_INTERNAL_UNIT
);
if
(
g_UnitMetric
==
INCHES
)
// Affichage en mils
if
(
g_UnitMetric
==
INCHES
)
// Affichage en mils
msg
.
Printf
(
_
(
"Track %.1f"
),
value
*
1000
);
msg
.
Printf
(
_
(
"Track %.1f"
),
value
*
1000
);
...
@@ -84,12 +84,12 @@ static wxMenu* Append_Track_Width_List()
...
@@ -84,12 +84,12 @@ static wxMenu* Append_Track_Width_List()
msg
.
Printf
(
_
(
"Track %.3f"
),
value
);
msg
.
Printf
(
_
(
"Track %.3f"
),
value
);
trackwidth_menu
->
Append
(
ID_POPUP_PCB_SELECT_WIDTH1
+
ii
,
msg
,
wxEmptyString
,
TRUE
);
trackwidth_menu
->
Append
(
ID_POPUP_PCB_SELECT_WIDTH1
+
ii
,
msg
,
wxEmptyString
,
TRUE
);
if
(
g_DesignSettings
.
m_TrackWid
ht
History
[
ii
]
==
g_DesignSettings
.
m_CurrentTrackWidth
)
if
(
g_DesignSettings
.
m_TrackWid
th
History
[
ii
]
==
g_DesignSettings
.
m_CurrentTrackWidth
)
trackwidth_menu
->
Check
(
ID_POPUP_PCB_SELECT_WIDTH1
+
ii
,
TRUE
);
trackwidth_menu
->
Check
(
ID_POPUP_PCB_SELECT_WIDTH1
+
ii
,
TRUE
);
}
}
trackwidth_menu
->
AppendSeparator
();
trackwidth_menu
->
AppendSeparator
();
for
(
ii
=
0
;
(
ii
<
HIST
0
RY_NUMBER
)
&&
(
ii
<
VIA_HISTORY_NUMBER_MAX
);
ii
++
)
for
(
ii
=
0
;
(
ii
<
HIST
O
RY_NUMBER
)
&&
(
ii
<
VIA_HISTORY_NUMBER_MAX
);
ii
++
)
{
{
if
(
g_DesignSettings
.
m_ViaSizeHistory
[
ii
]
==
0
)
if
(
g_DesignSettings
.
m_ViaSizeHistory
[
ii
]
==
0
)
break
;
break
;
...
...
pcbnew/pcbcfg.cpp
View file @
eaa147c1
...
@@ -170,11 +170,11 @@ int ii;
...
@@ -170,11 +170,11 @@ int ii;
ScreenPcb
->
m_UserGridUnit
=
g_UserGrid_Unit
;
ScreenPcb
->
m_UserGridUnit
=
g_UserGrid_Unit
;
}
}
g_DesignSettings
.
m_TrackWid
ht
History
[
0
]
=
g_DesignSettings
.
m_CurrentTrackWidth
;
g_DesignSettings
.
m_TrackWid
th
History
[
0
]
=
g_DesignSettings
.
m_CurrentTrackWidth
;
g_DesignSettings
.
m_ViaSizeHistory
[
0
]
=
g_DesignSettings
.
m_CurrentViaSize
;
g_DesignSettings
.
m_ViaSizeHistory
[
0
]
=
g_DesignSettings
.
m_CurrentViaSize
;
for
(
ii
=
1
;
ii
<
HIST
0
RY_NUMBER
;
ii
++
)
for
(
ii
=
1
;
ii
<
HIST
O
RY_NUMBER
;
ii
++
)
{
{
g_DesignSettings
.
m_TrackWid
ht
History
[
ii
]
=
0
;
g_DesignSettings
.
m_TrackWid
th
History
[
ii
]
=
0
;
g_DesignSettings
.
m_ViaSizeHistory
[
ii
]
=
0
;
g_DesignSettings
.
m_ViaSizeHistory
[
ii
]
=
0
;
}
}
...
...
pcbnew/pcbframe.cpp
View file @
eaa147c1
...
@@ -452,12 +452,12 @@ void WinEDA_PcbFrame::SetToolbars()
...
@@ -452,12 +452,12 @@ void WinEDA_PcbFrame::SetToolbars()
else
else
format
+=
wxT
(
" %.3f"
);
format
+=
wxT
(
" %.3f"
);
for
(
ii
=
0
;
ii
<
HIST
0
RY_NUMBER
;
ii
++
)
for
(
ii
=
0
;
ii
<
HIST
O
RY_NUMBER
;
ii
++
)
{
{
if
(
g_DesignSettings
.
m_TrackWid
ht
History
[
ii
]
==
0
)
if
(
g_DesignSettings
.
m_TrackWid
th
History
[
ii
]
==
0
)
break
;
// Fin de liste
break
;
// Fin de liste
double
value
=
To_User_Unit
(
g_UnitMetric
,
double
value
=
To_User_Unit
(
g_UnitMetric
,
g_DesignSettings
.
m_TrackWid
ht
History
[
ii
],
g_DesignSettings
.
m_TrackWid
th
History
[
ii
],
PCB_INTERNAL_UNIT
);
PCB_INTERNAL_UNIT
);
if
(
g_UnitMetric
==
INCHES
)
if
(
g_UnitMetric
==
INCHES
)
...
@@ -467,7 +467,7 @@ void WinEDA_PcbFrame::SetToolbars()
...
@@ -467,7 +467,7 @@ void WinEDA_PcbFrame::SetToolbars()
m_SelTrackWidthBox
->
Append
(
msg
);
m_SelTrackWidthBox
->
Append
(
msg
);
if
(
g_DesignSettings
.
m_TrackWid
ht
History
[
ii
]
==
if
(
g_DesignSettings
.
m_TrackWid
th
History
[
ii
]
==
g_DesignSettings
.
m_CurrentTrackWidth
)
g_DesignSettings
.
m_CurrentTrackWidth
)
m_SelTrackWidthBox
->
SetSelection
(
ii
);
m_SelTrackWidthBox
->
SetSelection
(
ii
);
}
}
...
@@ -484,7 +484,7 @@ void WinEDA_PcbFrame::SetToolbars()
...
@@ -484,7 +484,7 @@ void WinEDA_PcbFrame::SetToolbars()
else
else
format
+=
wxT
(
" %.3f"
);
format
+=
wxT
(
" %.3f"
);
for
(
ii
=
0
;
ii
<
HIST
0
RY_NUMBER
;
ii
++
)
for
(
ii
=
0
;
ii
<
HIST
O
RY_NUMBER
;
ii
++
)
{
{
if
(
g_DesignSettings
.
m_ViaSizeHistory
[
ii
]
==
0
)
if
(
g_DesignSettings
.
m_ViaSizeHistory
[
ii
]
==
0
)
break
;
// Fin de liste
break
;
// Fin de liste
...
...
pcbnew/specctra.h
View file @
eaa147c1
...
@@ -1706,7 +1706,7 @@ public:
...
@@ -1706,7 +1706,7 @@ public:
/**
/**
* Class SHAPE
* Class SHAPE
* corresponds to the "(shape ..)" element in the specctra dsn spec.
* corresponds to the "(shape ..)" element in the specctra dsn spec.
* It is not a <shape_descriptor> which is one of things that this
* It is not a <shape_descriptor>
,
which is one of things that this
* elements contains, i.e. in its "shape" field. This class also implements
* elements contains, i.e. in its "shape" field. This class also implements
* the "(outline ...)" element as a dual personality.
* the "(outline ...)" element as a dual personality.
*/
*/
...
@@ -1739,11 +1739,9 @@ public:
...
@@ -1739,11 +1739,9 @@ public:
delete
shape
;
delete
shape
;
}
}
void
SetShape
(
ELEM
*
aShape
)
void
SetShape
(
ELEM
*
aShape
)
{
{
delete
shape
;
delete
shape
;
shape
=
aShape
;
shape
=
aShape
;
if
(
aShape
)
if
(
aShape
)
...
...
pcbnew/specctra_export.cpp
View file @
eaa147c1
This diff is collapsed.
Click to expand it.
todo.txt
View file @
eaa147c1
...
@@ -71,3 +71,9 @@ asked by: jp Charras
...
@@ -71,3 +71,9 @@ asked by: jp Charras
Use the collector classes in eeschema.
Use the collector classes in eeschema.
2008-Jan-25 Assigned To: any one who wants to
asked by: dick
================================================================================
Split the QARCs being created as 1/2 circles into quarter arcs. Problem
is in 4 places in specctra_export.cpp
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