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Commit eaa147c1 authored by dickelbeck's avatar dickelbeck
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spelling errors, specctra work

parent 501fb2c2
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change_log.txt
View file @ eaa147c1
......@@ -8,28 +8,29 @@ email address.
2008-Jan-25 UPDATE Dick Hollenbeck <dick@softplc.com>
================================================================================
+pcbnew:
SPECCTRA export does padstacks ok, except that oval arcs need to be split
into quarter circle arcs, and no consideration is given to "layer types"
* SPECCTRA export does padstacks ok, except that oval pad's arcs need to be split
into quarter circle arcs, and no consideration is given to "layer types".
See page bottom of page 74 of the SECCTRA Design Language Reference, May 2000.
Still working today...
* HISTORY_NUMBER was spelt with a zero.
* Width was spelt as Widht
2008-Jan-25 UPDATE Jean-Pierre Charras <jean-pierre.charras@inpg.fr>
================================================================================
+pcbnew:
- void Change_Side_Module( MODULE* Module, wxDC* DC ) is now member of class BOARD.
- Better support for micro vias and buried vias (drill files now are useable for board manufacturers)
But not yet tested by a board manufacturer. Be carefull.
Todo: tools to conversion between via through and buried via and buried viad optimisation.
But must works for micro vias (needed for my next board)
(in pcbnew micro vias are blind vias between 2 adjacent layers: micro vias must be enabled
in Dimensions/track and via menu, and placed by ctrl v.
They are intended to connect small pitch BGA pins to the inner layer, and can be drilled by laser
if the hole diameter is small < 0.2mm. A laser can only drill a hole between 2 adjacent layers ).
** Currently use buried via for tests only, not for production **.
- void Change_Side_Module( MODULE* Module, wxDC* DC ) is now member of class BOARD.
- Better support for micro vias and buried vias (drill files now are useable for board manufacturers)
But not yet tested by a board manufacturer. Be carefull.
Todo: tools to conversion between via through and buried via and buried viad optimisation.
But must works for micro vias (needed for my next board)
(in pcbnew micro vias are blind vias between 2 adjacent layers: micro vias must be enabled
in Dimensions/track and via menu, and placed by ctrl v.
They are intended to connect small pitch BGA pins to the inner layer, and can be drilled by laser
if the hole diameter is small < 0.2mm. A laser can only drill a hole between 2 adjacent layers ).
** Currently use buried via for tests only, not for production **.
2008-Jan-24 UPDATE Dick Hollenbeck <dick@softplc.com>
================================================================================
......@@ -45,8 +46,8 @@ email address.
2008-Jan-24 UPDATE Jean-Pierre Charras <jean-pierre.charras@inpg.fr>
================================================================================
+pcbnew:
Bugs about fill zones removed (not all, of course).
Fixed an old bug in block delete (could crashes pcbnew after deleting footprints).
Bugs about fill zones removed (not all, of course).
Fixed an old bug in block delete (could crashes pcbnew after deleting footprints).
2008-Jan-23 UPDATE Dick Hollenbeck <dick@softplc.com>
================================================================================
......
include/pcbstruct.h
View file @ eaa147c1
/**************************************************************/
/* pcbstruct.h : definition des structures de donnees type PCB */
/* pcbstruct.h : definition des structures de donnees type PCB */
/**************************************************************/
#ifndef PCBSTRUCT_H
......@@ -144,7 +144,7 @@ struct CHEVELU;
#include "class_board.h"
// Class for handle current printed board design settings
#define HIST0RY_NUMBER 8
#define HISTORY_NUMBER 8
class EDA_BoardDesignSettings
{
public:
......@@ -153,11 +153,11 @@ public:
int m_MicroViaDrill; // micro via drill (for the entire board)
int m_CurrentViaSize; // Current via size
int m_CurrentMicroViaSize; // Current micro via size
bool m_MicroViasAllowed; // true to allow micro vias
int m_ViaSizeHistory[HIST0RY_NUMBER]; // Last HIST0RY_NUMBER used via sizes
bool m_MicroViasAllowed; // true to allow micro vias
int m_ViaSizeHistory[HISTORY_NUMBER]; // Last HISTORY_NUMBER used via sizes
int m_CurrentViaType; // via type (BLIND, TROUGHT ...), bits 1 and 2 (not 0 and 1)
int m_CurrentTrackWidth; // current track width
int m_TrackWidhtHistory[HIST0RY_NUMBER]; // Last HIST0RY_NUMBER used track widths
int m_TrackWidthHistory[HISTORY_NUMBER]; // Last HISTORY_NUMBER used track widths
int m_DrawSegmentWidth; // current graphic line width (not EDGE layer)
int m_EdgeSegmentWidth; // current graphic line width (EDGE layer only)
int m_PcbTextWidth; // current Pcb (not module) Text width
......@@ -226,13 +226,13 @@ public:
*/
BOARD_ITEM* GetCurItem() const { return (BOARD_ITEM*) BASE_SCREEN::GetCurItem(); }
/* Return true if a microvia can be put on board
* A microvia ia a small via restricted to 2 near neighbour layers
/* Return true if a microvia can be put on board
* A microvia ia a small via restricted to 2 near neighbour layers
* because its is hole is made by laser which can penetrate only one layer
* It is mainly used to connect BGA to the first inner layer
* And it is allowed from an external layer to the first inner layer
* It is mainly used to connect BGA to the first inner layer
* And it is allowed from an external layer to the first inner layer
*/
bool IsMicroViaAcceptable(void);
bool IsMicroViaAcceptable(void);
};
/**********************************/
......@@ -240,9 +240,9 @@ public:
/**********************************/
#include "class_pad.h" // class for pads
#include "class_edge_mod.h" // Class for footprint graphic elements
#include "class_text_mod.h" // Class for footprint fields
#include "class_module.h" // Class for the footprint
#include "class_edge_mod.h" // Class for footprint graphic elements
#include "class_text_mod.h" // Class for footprint fields
#include "class_module.h" // Class for the footprint
#include "class_equipot.h"
......
pcbnew/classpcb.cpp
View file @ eaa147c1
......@@ -127,7 +127,8 @@ EDA_BoardDesignSettings::EDA_BoardDesignSettings()
// Default values for designing boards
{
int ii;
int default_layer_color[32] = {
static const int default_layer_color[32] = {
GREEN, LIGHTGRAY, LIGHTGRAY, LIGHTGRAY,
LIGHTGRAY, LIGHTGRAY, LIGHTGRAY, LIGHTGRAY,
LIGHTGRAY, LIGHTGRAY, LIGHTGRAY, LIGHTGRAY,
......@@ -150,10 +151,10 @@ EDA_BoardDesignSettings::EDA_BoardDesignSettings()
m_CurrentViaSize = 450; // Current via size
m_CurrentViaType = VIA_THROUGH; /* via type (BLIND, TROUGHT ...), bits 1 and 2 (not 0 and 1)*/
m_CurrentTrackWidth = 170; // current track width
for( ii = 0; ii < HIST0RY_NUMBER; ii++ )
for( ii = 0; ii < HISTORY_NUMBER; ii++ )
{
m_TrackWidhtHistory[ii] = 0; // Last HIST0RY_NUMBER used track widths
m_ViaSizeHistory[ii] = 0; // Last HIST0RY_NUMBER used via sizes
m_TrackWidthHistory[ii] = 0; // Last HISTORY_NUMBER used track widths
m_ViaSizeHistory[ii] = 0; // Last HISTORY_NUMBER used via sizes
}
m_DrawSegmentWidth = 100; // current graphic line width (not EDGE layer)
......
pcbnew/dialog_track_options.cpp
View file @ eaa147c1
This diff is collapsed.
pcbnew/edit.cpp
View file @ eaa147c1
......@@ -829,7 +829,7 @@ void WinEDA_PcbFrame::Process_Special_Functions( wxCommandEvent& event )
case ID_AUX_TOOLBAR_PCB_TRACK_WIDTH:
{
int ii = m_SelTrackWidthBox->GetChoice();
g_DesignSettings.m_CurrentTrackWidth = g_DesignSettings.m_TrackWidhtHistory[ii];
g_DesignSettings.m_CurrentTrackWidth = g_DesignSettings.m_TrackWidthHistory[ii];
DisplayTrackSettings();
m_SelTrackWidthBox_Changed = FALSE;
m_SelViaSizeBox_Changed = FALSE;
......@@ -847,7 +847,7 @@ void WinEDA_PcbFrame::Process_Special_Functions( wxCommandEvent& event )
DrawPanel->MouseToCursorSchema();
{
int ii = id - ID_POPUP_PCB_SELECT_WIDTH1;
g_DesignSettings.m_CurrentTrackWidth = g_DesignSettings.m_TrackWidhtHistory[ii];
g_DesignSettings.m_CurrentTrackWidth = g_DesignSettings.m_TrackWidthHistory[ii];
DisplayTrackSettings();
}
break;
......
pcbnew/initpcb.cpp
View file @ eaa147c1
......@@ -192,13 +192,13 @@ bool WinEDA_BasePcbFrame::Clear_Pcb( bool query )
g_HightLigt_Status = 0;
for( int ii = 1; ii < HIST0RY_NUMBER; ii++ )
for( int ii = 1; ii < HISTORY_NUMBER; ii++ )
{
g_DesignSettings.m_ViaSizeHistory[ii] =
g_DesignSettings.m_TrackWidhtHistory[ii] = 0;
g_DesignSettings.m_TrackWidthHistory[ii] = 0;
}
g_DesignSettings.m_TrackWidhtHistory[0] = g_DesignSettings.m_CurrentTrackWidth;
g_DesignSettings.m_TrackWidthHistory[0] = g_DesignSettings.m_CurrentTrackWidth;
g_DesignSettings.m_ViaSizeHistory[0] = g_DesignSettings.m_CurrentViaSize;
Zoom_Automatique( TRUE );
......
pcbnew/ioascii.cpp
View file @ eaa147c1
......@@ -519,12 +519,12 @@ static int WriteSetup( FILE* File, WinEDA_BasePcbFrame* frame )
fprintf( File, "Layers %d\n", g_DesignSettings.m_CopperLayerCount );
fprintf( File, "TrackWidth %d\n", g_DesignSettings.m_CurrentTrackWidth );
for( ii = 0; ii < HIST0RY_NUMBER; ii++ )
for( ii = 0; ii < HISTORY_NUMBER; ii++ )
{
if( g_DesignSettings.m_TrackWidhtHistory[ii] == 0 )
if( g_DesignSettings.m_TrackWidthHistory[ii] == 0 )
break;
fprintf( File, "TrackWidthHistory %d\n",
g_DesignSettings.m_TrackWidhtHistory[ii] );
g_DesignSettings.m_TrackWidthHistory[ii] );
}
fprintf( File, "TrackClearence %d\n", g_DesignSettings.m_TrackClearence );
......@@ -534,7 +534,7 @@ static int WriteSetup( FILE* File, WinEDA_BasePcbFrame* frame )
fprintf( File, "EdgeSegmWidth %d\n", g_DesignSettings.m_EdgeSegmentWidth );
fprintf( File, "ViaSize %d\n", g_DesignSettings.m_CurrentViaSize );
fprintf( File, "ViaDrill %d\n", g_DesignSettings.m_ViaDrill );
for( ii = 0; ii < HIST0RY_NUMBER; ii++ )
for( ii = 0; ii < HISTORY_NUMBER; ii++ )
{
if( g_DesignSettings.m_ViaSizeHistory[ii] == 0 )
break;
......
pcbnew/onrightclick.cpp
View file @ eaa147c1
......@@ -71,12 +71,12 @@ static wxMenu* Append_Track_Width_List()
double value;
trackwidth_menu = new wxMenu;
for( ii = 0; (ii < HIST0RY_NUMBER) && (ii < TRACK_HISTORY_NUMBER_MAX); ii++ )
for( ii = 0; (ii < HISTORY_NUMBER) && (ii < TRACK_HISTORY_NUMBER_MAX); ii++ )
{
if( g_DesignSettings.m_TrackWidhtHistory[ii] == 0 )
if( g_DesignSettings.m_TrackWidthHistory[ii] == 0 )
break;
value = To_User_Unit( g_UnitMetric,
g_DesignSettings.m_TrackWidhtHistory[ii],
g_DesignSettings.m_TrackWidthHistory[ii],
PCB_INTERNAL_UNIT );
if( g_UnitMetric == INCHES ) // Affichage en mils
msg.Printf( _( "Track %.1f" ), value * 1000 );
......@@ -84,12 +84,12 @@ static wxMenu* Append_Track_Width_List()
msg.Printf( _( "Track %.3f" ), value );
trackwidth_menu->Append( ID_POPUP_PCB_SELECT_WIDTH1 + ii, msg, wxEmptyString, TRUE );
if( g_DesignSettings.m_TrackWidhtHistory[ii] == g_DesignSettings.m_CurrentTrackWidth )
if( g_DesignSettings.m_TrackWidthHistory[ii] == g_DesignSettings.m_CurrentTrackWidth )
trackwidth_menu->Check( ID_POPUP_PCB_SELECT_WIDTH1 + ii, TRUE );
}
trackwidth_menu->AppendSeparator();
for( ii = 0; (ii < HIST0RY_NUMBER) && (ii < VIA_HISTORY_NUMBER_MAX); ii++ )
for( ii = 0; (ii < HISTORY_NUMBER) && (ii < VIA_HISTORY_NUMBER_MAX); ii++ )
{
if( g_DesignSettings.m_ViaSizeHistory[ii] == 0 )
break;
......
pcbnew/pcbcfg.cpp
View file @ eaa147c1
......@@ -170,11 +170,11 @@ int ii;
ScreenPcb->m_UserGridUnit = g_UserGrid_Unit;
}
g_DesignSettings.m_TrackWidhtHistory[0] = g_DesignSettings.m_CurrentTrackWidth;
g_DesignSettings.m_TrackWidthHistory[0] = g_DesignSettings.m_CurrentTrackWidth;
g_DesignSettings.m_ViaSizeHistory[0] = g_DesignSettings.m_CurrentViaSize;
for ( ii = 1; ii < HIST0RY_NUMBER; ii++)
for ( ii = 1; ii < HISTORY_NUMBER; ii++)
{
g_DesignSettings.m_TrackWidhtHistory[ii] = 0;
g_DesignSettings.m_TrackWidthHistory[ii] = 0;
g_DesignSettings.m_ViaSizeHistory[ii] = 0;
}
......
pcbnew/pcbframe.cpp
View file @ eaa147c1
......@@ -452,12 +452,12 @@ void WinEDA_PcbFrame::SetToolbars()
else
format += wxT( " %.3f" );
for( ii = 0; ii < HIST0RY_NUMBER; ii++ )
for( ii = 0; ii < HISTORY_NUMBER; ii++ )
{
if( g_DesignSettings.m_TrackWidhtHistory[ii] == 0 )
if( g_DesignSettings.m_TrackWidthHistory[ii] == 0 )
break; // Fin de liste
double value = To_User_Unit( g_UnitMetric,
g_DesignSettings.m_TrackWidhtHistory[ii],
g_DesignSettings.m_TrackWidthHistory[ii],
PCB_INTERNAL_UNIT );
if( g_UnitMetric == INCHES )
......@@ -467,7 +467,7 @@ void WinEDA_PcbFrame::SetToolbars()
m_SelTrackWidthBox->Append( msg );
if( g_DesignSettings.m_TrackWidhtHistory[ii] ==
if( g_DesignSettings.m_TrackWidthHistory[ii] ==
g_DesignSettings.m_CurrentTrackWidth )
m_SelTrackWidthBox->SetSelection( ii );
}
......@@ -484,7 +484,7 @@ void WinEDA_PcbFrame::SetToolbars()
else
format += wxT( " %.3f" );
for( ii = 0; ii < HIST0RY_NUMBER; ii++ )
for( ii = 0; ii < HISTORY_NUMBER; ii++ )
{
if( g_DesignSettings.m_ViaSizeHistory[ii] == 0 )
break; // Fin de liste
......
pcbnew/specctra.h
View file @ eaa147c1
......@@ -1706,7 +1706,7 @@ public:
/**
* Class SHAPE
* corresponds to the "(shape ..)" element in the specctra dsn spec.
* It is not a &lt;shape_descriptor&gt; which is one of things that this
* It is not a &lt;shape_descriptor&gt;, which is one of things that this
* elements contains, i.e. in its "shape" field. This class also implements
* the "(outline ...)" element as a dual personality.
*/
......@@ -1739,11 +1739,9 @@ public:
delete shape;
}
void SetShape( ELEM* aShape )
{
delete shape;
shape = aShape;
if( aShape )
......
pcbnew/specctra_export.cpp
View file @ eaa147c1
This diff is collapsed.
todo.txt
View file @ eaa147c1
......@@ -71,3 +71,9 @@ asked by: jp Charras
Use the collector classes in eeschema.
2008-Jan-25 Assigned To: any one who wants to
asked by: dick
================================================================================
Split the QARCs being created as 1/2 circles into quarter arcs. Problem
is in 4 places in specctra_export.cpp
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