Commit 032ef3a7 authored by Maciej Suminski's avatar Maciej Suminski

Showing net names on tracks.

parent 5a0869f2
...@@ -214,6 +214,7 @@ enum PCB_VISIBLE ...@@ -214,6 +214,7 @@ enum PCB_VISIBLE
MOD_REFERENCES_VISIBLE, ///< show modules references (when texts are visibles) MOD_REFERENCES_VISIBLE, ///< show modules references (when texts are visibles)
TRACKS_VISIBLE, TRACKS_VISIBLE,
TRACKS_NETNAMES_VISIBLE,
PADS_VISIBLE, PADS_VISIBLE,
VIA_HOLES_VISIBLE, VIA_HOLES_VISIBLE,
PAD_HOLES_VISIBLE, PAD_HOLES_VISIBLE,
......
...@@ -97,9 +97,10 @@ const int m_galLayerOrder[] = ...@@ -97,9 +97,10 @@ const int m_galLayerOrder[] =
ITEM_GAL_LAYER( VIA_HOLES_VISIBLE ), ITEM_GAL_LAYER( PAD_HOLES_VISIBLE ), ITEM_GAL_LAYER( VIA_HOLES_VISIBLE ), ITEM_GAL_LAYER( PAD_HOLES_VISIBLE ),
ITEM_GAL_LAYER( VIAS_VISIBLE ), ITEM_GAL_LAYER( PADS_VISIBLE ), ITEM_GAL_LAYER( VIAS_VISIBLE ), ITEM_GAL_LAYER( PADS_VISIBLE ),
ITEM_GAL_LAYER( PAD_FR_VISIBLE ), LAYER_N_FRONT, LAYER_N_15, LAYER_N_14, LAYER_N_13, ITEM_GAL_LAYER( TRACKS_NETNAMES_VISIBLE ), ITEM_GAL_LAYER( PAD_FR_VISIBLE ),
LAYER_N_FRONT, LAYER_N_15, LAYER_N_14, LAYER_N_13,
LAYER_N_12, LAYER_N_11, LAYER_N_10, LAYER_N_9, LAYER_N_8, LAYER_N_7, LAYER_N_6, LAYER_N_12, LAYER_N_11, LAYER_N_10, LAYER_N_9, LAYER_N_8, LAYER_N_7, LAYER_N_6,
LAYER_N_5, LAYER_N_4, LAYER_N_3, LAYER_N_2, ITEM_GAL_LAYER( PAD_BK_VISIBLE ), LAYER_N_BACK, LAYER_N_5, LAYER_N_4, LAYER_N_3, LAYER_N_2, LAYER_N_BACK, ITEM_GAL_LAYER( PAD_BK_VISIBLE ),
SOLDERMASK_N_BACK, ADHESIVE_N_BACK, SOLDERPASTE_N_BACK, SILKSCREEN_N_BACK, SOLDERMASK_N_BACK, ADHESIVE_N_BACK, SOLDERPASTE_N_BACK, SILKSCREEN_N_BACK,
ITEM_GAL_LAYER( MOD_TEXT_BK_VISIBLE ) ITEM_GAL_LAYER( MOD_TEXT_BK_VISIBLE )
...@@ -223,6 +224,10 @@ void PCB_BASE_FRAME::SetBoard( BOARD* aBoard ) ...@@ -223,6 +224,10 @@ void PCB_BASE_FRAME::SetBoard( BOARD* aBoard )
view->SetLayerOrder( m_galLayerOrder[i], i ); view->SetLayerOrder( m_galLayerOrder[i], i );
} }
// Netnames are drawn only when scale is sufficient (level of details)
// so there is no point in caching them
view->SetLayerCached( ITEM_GAL_LAYER( TRACKS_NETNAMES_VISIBLE ), false );
// Load layer & elements visibility settings // Load layer & elements visibility settings
for( unsigned int i = 0; i < NB_LAYERS; ++i ) for( unsigned int i = 0; i < NB_LAYERS; ++i )
{ {
......
...@@ -749,6 +749,36 @@ void TRACK::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode, ...@@ -749,6 +749,36 @@ void TRACK::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode,
} }
void TRACK::ViewGetLayers( int aLayers[], int& aCount ) const
{
// Show the track and its netname on different layers
aLayers[0] = GetLayer();
aLayers[1] = ITEM_GAL_LAYER( TRACKS_NETNAMES_VISIBLE );
aCount = 2;
}
void TRACK::ViewGetRequiredLayers( int aLayers[], int& aCount ) const
{
// The only required layer is the track layer itself
aLayers[0] = GetLayer();
aCount = 1;
}
unsigned int TRACK::ViewGetLOD( int aLayer ) const
{
// Netnames will be shown only if zoom is appropriate
if( aLayer == ITEM_GAL_LAYER( TRACKS_NETNAMES_VISIBLE ) )
{
return ( 20000000 / m_Width );
}
// Other layers are shown without any conditions
return 0;
}
void SEGVIA::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode, void SEGVIA::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode,
const wxPoint& aOffset ) const wxPoint& aOffset )
{ {
...@@ -964,16 +994,6 @@ void SEGVIA::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode, ...@@ -964,16 +994,6 @@ void SEGVIA::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode,
void SEGVIA::ViewGetLayers( int aLayers[], int& aCount ) const void SEGVIA::ViewGetLayers( int aLayers[], int& aCount ) const
{ {
/*int top_layer, bottom_layer;
ReturnLayerPair( &top_layer, &bottom_layer );
// We can add vias to all layers they belong, but then they are drawn this many times
aCount = 0;
for( int i = bottom_layer; i <= top_layer; ++i )
{
aLayers[aCount++] = i;
}*/
// Just show it on common via & via holes layers // Just show it on common via & via holes layers
aLayers[0] = ITEM_GAL_LAYER( VIAS_VISIBLE ); aLayers[0] = ITEM_GAL_LAYER( VIAS_VISIBLE );
aLayers[1] = ITEM_GAL_LAYER( VIA_HOLES_VISIBLE ); aLayers[1] = ITEM_GAL_LAYER( VIA_HOLES_VISIBLE );
......
...@@ -328,6 +328,15 @@ public: ...@@ -328,6 +328,15 @@ public:
virtual EDA_ITEM* Clone() const; virtual EDA_ITEM* Clone() const;
/// @copydoc VIEW_ITEM::ViewGetLayers()
virtual void ViewGetLayers( int aLayers[], int& aCount ) const;
/// @copydoc VIEW_ITEM::ViewGetRequiredLayers()
virtual void ViewGetRequiredLayers( int aLayers[], int& aCount ) const;
/// @copydoc VIEW_ITEM::ViewGetLOD()
virtual unsigned int ViewGetLOD( int aLayer ) const;
#if defined (DEBUG) #if defined (DEBUG)
virtual void Show( int nestLevel, std::ostream& os ) const { ShowDummy( os ); } // override virtual void Show( int nestLevel, std::ostream& os ) const { ShowDummy( os ); } // override
......
...@@ -23,6 +23,7 @@ ...@@ -23,6 +23,7 @@
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*/ */
#include <class_board.h>
#include <class_track.h> #include <class_track.h>
#include <class_module.h> #include <class_module.h>
#include <class_pad.h> #include <class_pad.h>
...@@ -33,6 +34,7 @@ ...@@ -33,6 +34,7 @@
#include <class_marker_pcb.h> #include <class_marker_pcb.h>
#include <class_dimension.h> #include <class_dimension.h>
#include <class_mire.h> #include <class_mire.h>
#include <class_netinfo.h>
#include <pcbstruct.h> #include <pcbstruct.h>
#include <view/view.h> #include <view/view.h>
...@@ -65,10 +67,12 @@ void PCB_RENDER_SETTINGS::ImportLegacyColors( COLORS_DESIGN_SETTINGS* aSettings ...@@ -65,10 +67,12 @@ void PCB_RENDER_SETTINGS::ImportLegacyColors( COLORS_DESIGN_SETTINGS* aSettings
m_itemColors[i] = m_legacyColorMap[aSettings->GetItemColor( i )]; m_itemColors[i] = m_legacyColorMap[aSettings->GetItemColor( i )];
} }
m_itemColors[VIA_HOLES_VISIBLE] = COLOR4D( 0.5, 0.4, 0.0, 1.0 ); // Default colors for specific layers
m_itemColors[PAD_HOLES_VISIBLE] = COLOR4D( 0.0, 0.5, 0.5, 1.0 ); m_itemColors[VIA_HOLES_VISIBLE] = COLOR4D( 0.5, 0.4, 0.0, 1.0 );
m_itemColors[VIAS_VISIBLE] = COLOR4D( 0.7, 0.7, 0.7, 1.0 ); m_itemColors[PAD_HOLES_VISIBLE] = COLOR4D( 0.0, 0.5, 0.5, 1.0 );
m_itemColors[PADS_VISIBLE] = COLOR4D( 0.7, 0.7, 0.7, 1.0 ); m_itemColors[VIAS_VISIBLE] = COLOR4D( 0.7, 0.7, 0.7, 1.0 );
m_itemColors[PADS_VISIBLE] = COLOR4D( 0.7, 0.7, 0.7, 1.0 );
m_itemColors[TRACKS_NETNAMES_VISIBLE] = COLOR4D( 0.9, 0.9, 0.9, 1.0 );
Update(); Update();
} }
...@@ -200,7 +204,7 @@ bool PCB_PAINTER::Draw( const VIEW_ITEM* aItem, int aLayer ) ...@@ -200,7 +204,7 @@ bool PCB_PAINTER::Draw( const VIEW_ITEM* aItem, int aLayer )
{ {
case PCB_ZONE_T: case PCB_ZONE_T:
case PCB_TRACE_T: case PCB_TRACE_T:
draw( (TRACK*) aItem ); draw( (TRACK*) aItem, aLayer );
break; break;
case PCB_VIA_T: case PCB_VIA_T:
...@@ -246,30 +250,63 @@ bool PCB_PAINTER::Draw( const VIEW_ITEM* aItem, int aLayer ) ...@@ -246,30 +250,63 @@ bool PCB_PAINTER::Draw( const VIEW_ITEM* aItem, int aLayer )
} }
void PCB_PAINTER::draw( const TRACK* aTrack ) void PCB_PAINTER::draw( const TRACK* aTrack, int aLayer )
{ {
VECTOR2D start( aTrack->GetStart() ); VECTOR2D start( aTrack->GetStart() );
VECTOR2D end( aTrack->GetEnd() ); VECTOR2D end( aTrack->GetEnd() );
int width = aTrack->GetWidth(); int width = aTrack->GetWidth();
COLOR4D color = getLayerColor( aTrack->GetLayer(), aTrack->GetNet() ); int netNumber = aTrack->GetNet();
COLOR4D color = getLayerColor( aLayer, netNumber );
m_gal->SetStrokeColor( color ); m_gal->SetStrokeColor( color );
m_gal->SetIsStroke( true );
if( m_pcbSettings->m_sketchModeSelect[TRACKS_VISIBLE] ) if( aLayer == ITEM_GAL_LAYER( TRACKS_NETNAMES_VISIBLE) )
{ {
// Outline mode // If there is a net name - display it on the track
m_gal->SetLineWidth( m_pcbSettings->m_outlineWidth ); if( netNumber != 0 )
m_gal->SetIsFill( false ); {
VECTOR2D line = ( end - start );
double length = line.EuclideanNorm();
// Check if the track is long enough to have a netname displayed
if( length < 10 * width )
return;
NETINFO_ITEM* net = ( (BOARD*) aTrack->GetParent() )->FindNet( netNumber );
std::string netName = std::string( net->GetShortNetname().mb_str() );
VECTOR2D textPosition = start + line / 2.0; // center of the track
double textOrientation = -atan( line.y / line.x );
double textSize = std::min( static_cast<double>( width ), length / netName.length() );
m_gal->SetLineWidth( width / 10.0 );
m_gal->SetBold( false );
m_gal->SetItalic( false );
m_gal->SetMirrored( false );
m_gal->SetGlyphSize( VECTOR2D( textSize * 0.7, textSize * 0.7 ) );
m_gal->SetHorizontalJustify( GR_TEXT_HJUSTIFY_CENTER );
m_gal->SetVerticalJustify( GR_TEXT_VJUSTIFY_CENTER );
m_gal->StrokeText( netName, textPosition, textOrientation );
}
} }
else else
{ {
// Filled mode // Draw a regular track
m_gal->SetFillColor( color ); m_gal->SetIsStroke( true );
m_gal->SetIsFill( true );
}
m_gal->DrawSegment( start, end, width ); if( m_pcbSettings->m_sketchModeSelect[TRACKS_VISIBLE] )
{
// Outline mode
m_gal->SetLineWidth( m_pcbSettings->m_outlineWidth );
m_gal->SetIsFill( false );
}
else
{
// Filled mode
m_gal->SetFillColor( color );
m_gal->SetIsFill( true );
}
m_gal->DrawSegment( start, end, width );
}
} }
......
...@@ -149,7 +149,7 @@ protected: ...@@ -149,7 +149,7 @@ protected:
const COLOR4D& getItemColor( int aItemType, int aNetCode ) const; const COLOR4D& getItemColor( int aItemType, int aNetCode ) const;
// Drawing functions for various types of PCB-specific items // Drawing functions for various types of PCB-specific items
void draw( const TRACK* ); void draw( const TRACK*, int );
void draw( const SEGVIA*, int ); void draw( const SEGVIA*, int );
void draw( const D_PAD*, int ); void draw( const D_PAD*, int );
void draw( const DRAWSEGMENT* ); void draw( const DRAWSEGMENT* );
......
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