Design 3-A4i rung C1 (native tile_processor_gpu 7db7cf6):
- IntersceneLma: PoseLmaPrepareProvider + residentPrepare() (mirrors the
  getFxDerivs head: ERS pokes + setupERS + camera/centers capture; per-cycle
  H2D = camera state + pose vector + centers + 6 policy floats). Production
  lean prepare skips setSamplesWeights / both fx passes / WJtJ+reg+normalize /
  y-build entirely; weights/y stay GPU-resident; initial RMS seeds from the
  first resident step's packed[19,20] (kills the runLma first-step
  re-linearization = C0's 'LMA CPU remainder'). Invalid/unavailable falls
  back loudly to the legacy Java prepare.
- One-shot oracle (pose_lma_debug>=1, first prepare): the capture cycle runs
  FULLY legacy, then the resident prepare captures its buffers and the new
  IntersceneLmaFloat.prepareResidentOracle (serial float clone) must match
  BIT-EXACTLY ('resident CUDA vs Java-float PREPARE: ... mismatches=0').
- lmaStep: prepared-resident steps pass NULL weights/y/eigen (no per-step
  H2D); first-block linearization skipped when prepared.
- CuasPoseRT: provider wiring (slot 0xff + CORR_NTILE_SHIFT = host policy),
  new marker 'resident CUDA prepareLMA active'; cycle_rms_meas moved after
  runLma reading getInitialRms() (same value on both paths).
- Stage0 kernel count 33 -> 36 (3 new prepare kernels).
Gates: mvn package + test PASS; Stage0 36/36; full native suite in
tile_processor_gpu 7db7cf6 (direct prepare BIT-EXACT, sanitizer 0 errors).
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>