Overlap-ring design ratified 07/17 (handoffs/2026-07-17_pose_d5_overlap_ring_design.md):
- TpJna/GpuQuadJna/GpuQuad: bindings for the D5a image-set ring
  (selectImageSet/execConditioningAsync/imageSetReadyRecord) and the D5b
  launch/collect split (execPoseSceneDpLaunch/Collect); base/JCuda =
  unsupported (serial order + blocking entry retained).
- CuasConditioning.conditionPreloadedSceneToGpuOverlap: same staged upload +
  same conditioning kernel into ring slot img_set on the copy stream (bytes
  identical by construction - the D5a slot-equivalence case); restores the
  previous set on any failure.
- CuasPoseRT: dpSceneEntry takes an overlap Runnable - launch -> condition
  the NEXT scene -> collect (the ~5.6 ms/scene conditioning+H2D stage hides
  under the ~12.5 ms chain); the D4 oracle replay stays blocking; the loop
  builds the runnable (preloaded harness only, next non-null scene), skips
  the serial conditioning for a pre-conditioned scene, and disables the
  overlap for the rest of the run on any failure (fail-safe; the previous
  set is restored, records unaffected).
- CuasRtParameters: saved checkbox pose_h2d_overlap (default ON, under
  pose_scene_dp) = the A/B knob.
Gates: mvn clean package + mvn test PASS; Stage0 40/40 (no new kernels);
native run_cases.sh ALL PASS (img_ring + scene_dp_split + all existing).
REAL-SCENE GATE PENDING: routine saves-OFF run, 497 Done lines byte-identical
to the 07/16 22:52 record, expect whole ~20.9 -> ~15.5 ms/scene, ~63-65
scenes/s (60 FPS PASS on the mean).
Co-authored-by: Claude Opus 4.8 <claude-opus-4-8@anthropic.com>
Co-authored-by: Claude Fable 5 <claude-fable-5@anthropic.com>