CLAUDE: M1 - Stage0 kernel count 40->41 (erase_clt_task_tiles)

Co-authored-by: Claude Opus 4.8 <claude-opus-4-8@anthropic.com>
Co-authored-by: Claude Fable 5 <claude-fable-5@anthropic.com>

src/main/java/com/elphel/imagej/gpu/jna/Stage0.java

@@ -10,7 +10,7 @@ import com.sun.jna.Pointer;
  *        com.elphel.imagej.gpu.jna.Stage0 [kernel_src_dir] [libcudadevrt.a]
  */
 public class Stage0 {
-	private static final int EXPECTED_KERNELS = 40; // 36 (through rung C1) + 2 DP-cycles (D1: pose_lma_dp_cycles/commit) + measure-chain DP (D2: pose_measure_dp + launch helpers) + scene DP parent family (D3: pose_scene_dp lma/step/commit) - the native D1-D3 sessions could not touch this Java constant, synced at D4 // By Claude on 07/17/2026
+	private static final int EXPECTED_KERNELS = 41; // 40 (through rung D4) + erase_clt_task_tiles (margin rung M1: erase-by-task-list in the pose chain) // By Claude on 07/17/2026
     public static void main(String[] args) {
         String srcdir = (args.length > 0) ? args[0] : "/home/elphel/git/tile_processor_gpu/src";
         String devrt  = (args.length > 1) ? args[1] : "/usr/local/cuda/targets/x86_64-linux/lib/libcudadevrt.a";