Design 3-A4i rung C2 (native tile_processor_gpu HEAD):
- IntersceneLma: per-SEQUENCE cache (reference Camera + flattened centers,
  keyed on the reference ErsCorrection; the virtual center is static by
  construction - zero pose, zero rates) with an explicit
  resetPoseSequenceCache() re-armed at sequence start; per-SCENE cache
  (scene Camera in the per-scene instance: ERS rates never change across
  cycles - setupERS depends only on rates/line_time, verified, and the 3
  adjusted angles travel in pose_vectors). setupERS + Camera.capture now run
  once per level instead of 4x/scene; the provider gets null for resident
  groups. Provider/GpuQuad/GpuQuadJna signatures gain explicit numTiles.
- Dead work deleted: the threaded setEigenTransform build at the prepareLMA
  head runs only on the legacy/capture/MB fall-through (the GPU assemble
  builds the transform from resident peaks on the production path).
- CuasPoseRT: resetPoseSequenceCache() at testPoseSequence start.
Expected: prep setup 5.7 -> ~1.5 ms cycle-1 / ~0.3-0.7 cycles 2-4, prepare
~22.9 -> ~3-5 ms/scene; per-cycle PCIe ~120KB -> ~60B + result.
Gates: mvn package+test PASS; Stage0 36/36; full native suite PASS.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>