Commits · 1d4e9a4c5d7b5e7ca24689393b9dc4c03682afa8 · Elphel / ezynq

09 Sep, 2013 1 commit
- Entering register definitions for SLCR clocks and resets · 1d4e9a4c
  Andrey Filippov authored Sep 09, 2013
  
  1d4e9a4c
08 Sep, 2013 2 commits
- Re-organized DDR-related parameters to separate device datasheet ones · 60c8fcd2
  Andrey Filippov authored Sep 08, 2013
  
  60c8fcd2
- Mor DDR registers · 4e40c7aa
  Andrey Filippov authored Sep 08, 2013
  
  4e40c7aa
07 Sep, 2013 1 commit
- More registers/parameters defined · e3be621b
  Andrey Filippov authored Sep 07, 2013
  
  e3be621b
06 Sep, 2013 1 commit
- Added DDR Mode Registers configuration, address mapping calculation · fcf56187
  Andrey Filippov authored Sep 06, 2013
  
  fcf56187
05 Sep, 2013 4 commits
- Add *.pyc to .gitignore · 4c09d564
  Paulo Henrique Silva authored Sep 05, 2013
  
  4c09d564
- Continuing with the DDR configuration · 92a49327
  Andrey Filippov authored Sep 05, 2013
  
  92a49327
- was renamed · d385610f
  Eyesisbox Elphel authored Sep 05, 2013
  
  d385610f
- continue on DDR initialization · a3f7f58e
  Eyesisbox Elphel authored Sep 05, 2013
  
  a3f7f58e
02 Sep, 2013 1 commit
- Working on DDR configuration · 496a0d6f
  Eyesisbox Elphel authored Sep 02, 2013
  
  496a0d6f
30 Aug, 2013 1 commit
- Initial release of the files · 5b2e54e8
  Eyesisbox Elphel authored Aug 30, 2013
  
  5b2e54e8