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ezynq
Commit 2d6c690c authored by Andrey Filippov's avatar Andrey Filippov
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Generating lowlevel.c for u-boot

parent a7aad2bb
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Showing with 219 additions and 86 deletions
ezynq_clk.py
View file @ 2d6c690c
...@@ -340,7 +340,8 @@ class EzynqClk: ...@@ -340,7 +340,8 @@ class EzynqClk:
clk=self.iface_divs[name] clk=self.iface_divs[name]
if (not 'PLL' in clk ) and (not 'FREQ' in clk): if (not 'PLL' in clk ) and (not 'FREQ' in clk):
self.iface_divs[name]['FREQ']=self.iface_divs[self.iface_divs[name]['SOURCE']]['FREQ'] # same frequency - possible to use 'VALUE' as scale self.iface_divs[name]['FREQ']=self.iface_divs[self.iface_divs[name]['SOURCE']]['FREQ'] # same frequency - possible to use 'VALUE' as scale
def get_plls_used (self):
return set([pll for pll in self.pll_fdivs])
def html_list_clocks(self,html_file): def html_list_clocks(self,html_file):
def list_with_children(name): def list_with_children(name):
...@@ -411,23 +412,26 @@ class EzynqClk: ...@@ -411,23 +412,26 @@ class EzynqClk:
def get_new_register_sets(self): def get_new_register_sets(self):
return self.clk_register_set.get_register_sets(True,True) return self.clk_register_set.get_register_sets(True,True)
def clocks_rbl_setup(self,current_reg_sets,force=False,warn=False): def clocks_regs_setup(self,current_reg_sets,unlock_needed=True,force=False,warn=False):
clk_register_set=self.clk_register_set clk_register_set=self.clk_register_set
clk_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state clk_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state
if unlock_needed:
self.slcr_unlock()
_ = clk_register_set.get_register_sets(True,True) # close previous register settings
# Bypass used PLL-s - stage 1 of PLL setup # Bypass used PLL-s - stage 1 of PLL setup
self.clocks_rbl_pll_bypass(force=False,warn=False) self.clocks_pll_bypass(force=False,warn=False)
_ = clk_register_set.get_register_sets(True,True) # close previous register settings _ = clk_register_set.get_register_sets(True,True) # close previous register settings
# Turn on PLL reset and program feedback - stage 2 of PLL setup # Turn on PLL reset and program feedback - stage 2 of PLL setup
self.clocks_rbl_pll_reset_and_fdiv(force=False,warn=False) self.clocks_pll_reset_and_fdiv(force=False,warn=False)
_ = clk_register_set.get_register_sets(True,True) # close previous register settings _ = clk_register_set.get_register_sets(True,True) # close previous register settings
# Configure PLL parameters - stage 3 of PLL setup # Configure PLL parameters - stage 3 of PLL setup
self.clocks_rbl_pll_conf(force=False,warn=False) self.clocks_pll_conf(force=False,warn=False)
_ = clk_register_set.get_register_sets(True,True) # close previous register settings _ = clk_register_set.get_register_sets(True,True) # close previous register settings
# Release reset of the PLLs (let them start) - stage 4 of PLL setup # Release reset of the PLLs (let them start) - stage 4 of PLL setup
self.clocks_rbl_pll_start(force=False,warn=False) self.clocks_pll_start(force=False,warn=False)
_ = clk_register_set.get_register_sets(True,True) # close previous register settings _ = clk_register_set.get_register_sets(True,True) # close previous register settings
# Do after PLL bypass and Reset - stage 5 of clocks setup # stage 5 of clocks setup
self.clocks_rbl_program(force=False,warn=False) self.clocks_program(force=False,warn=False)
# #Trying toggle feature (but actually for now it can be left in reset state - is this on/off/on needed? # #Trying toggle feature (but actually for now it can be left in reset state - is this on/off/on needed?
# _ = ddriob_register_set.get_register_sets(True,True) # close previous register settings # _ = ddriob_register_set.get_register_sets(True,True) # close previous register settings
...@@ -444,9 +448,16 @@ class EzynqClk: ...@@ -444,9 +448,16 @@ class EzynqClk:
# ('update_control',0)),force,warn) # ('update_control',0)),force,warn)
#Unlock SLCR (if the code is running after RBL) - stage 0 of PLL setup
def slcr_unlock(self):
clk_register_set=self.clk_register_set
if self.verbosity>0 :
print 'Unlocking SLCR'
clk_register_set.set_word('slcr_unlock',0xdf0d)
#Bypass used PLL-s - stage 1 of PLL setup #Bypass used PLL-s - stage 1 of PLL setup
def clocks_rbl_pll_bypass(self,force=False,warn=False): def clocks_pll_bypass(self,force=False,warn=False):
clk_register_set=self.clk_register_set clk_register_set=self.clk_register_set
if self.verbosity>0 : if self.verbosity>0 :
print 'pll_fdivs=', self.pll_fdivs print 'pll_fdivs=', self.pll_fdivs
...@@ -464,7 +475,7 @@ class EzynqClk: ...@@ -464,7 +475,7 @@ class EzynqClk:
('pll_bypass_force', 1)),force,warn) ('pll_bypass_force', 1)),force,warn)
# Turn on PLL reset and program feedback - stage 2 of PLL setup # Turn on PLL reset and program feedback - stage 2 of PLL setup
def clocks_rbl_pll_reset_and_fdiv(self,force=False,warn=False): def clocks_pll_reset_and_fdiv(self,force=False,warn=False):
clk_register_set=self.clk_register_set clk_register_set=self.clk_register_set
if 'DDR' in self.pll_fdivs: if 'DDR' in self.pll_fdivs:
clk_register_set.set_bitfields('ddr_pll_ctrl',( # clk_register_set.set_bitfields('ddr_pll_ctrl',( #
...@@ -480,7 +491,7 @@ class EzynqClk: ...@@ -480,7 +491,7 @@ class EzynqClk:
('pll_reset', 1)),force,warn) ('pll_reset', 1)),force,warn)
# Configure PLL parameters - stage 3 of PLL setup # Configure PLL parameters - stage 3 of PLL setup
def clocks_rbl_pll_conf(self,force=False,warn=False): def clocks_pll_conf(self,force=False,warn=False):
clk_register_set=self.clk_register_set clk_register_set=self.clk_register_set
if 'DDR' in self.pll_fdivs: if 'DDR' in self.pll_fdivs:
ddr_fdiv=self.pll_fdivs['DDR'] ddr_fdiv=self.pll_fdivs['DDR']
...@@ -504,7 +515,7 @@ class EzynqClk: ...@@ -504,7 +515,7 @@ class EzynqClk:
('pll_res', self.pll_pars[arm_fdiv]['PLL_RES']), # PLL loop filter resistor control ('pll_res', self.pll_pars[arm_fdiv]['PLL_RES']), # PLL loop filter resistor control
),force,warn) ),force,warn)
# Release reset of the PLLs (let them start) - stage 4 of PLL setup # Release reset of the PLLs (let them start) - stage 4 of PLL setup
def clocks_rbl_pll_start(self,force=False,warn=False): def clocks_pll_start(self,force=False,warn=False):
clk_register_set=self.clk_register_set clk_register_set=self.clk_register_set
if 'DDR' in self.pll_fdivs: if 'DDR' in self.pll_fdivs:
clk_register_set.set_bitfields('ddr_pll_ctrl',(('pll_reset', 0)),force,warn) clk_register_set.set_bitfields('ddr_pll_ctrl',(('pll_reset', 0)),force,warn)
...@@ -513,9 +524,23 @@ class EzynqClk: ...@@ -513,9 +524,23 @@ class EzynqClk:
if 'ARM' in self.pll_fdivs: if 'ARM' in self.pll_fdivs:
clk_register_set.set_bitfields('arm_pll_ctrl',(('pll_reset', 0)),force,warn) clk_register_set.set_bitfields('arm_pll_ctrl',(('pll_reset', 0)),force,warn)
# Release bypass the PLLs (PLLs should be locked already!)
def clocks_pll_bypass_off(self,current_reg_sets,force=False,warn=False):
clk_register_set=self.clk_register_set
clk_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state
if 'DDR' in self.pll_fdivs:
clk_register_set.set_bitfields('ddr_pll_ctrl',(('pll_bypass_force', 0),
('pll_bypass_qual', 0)),force,warn)
if 'IO' in self.pll_fdivs:
clk_register_set.set_bitfields('io_pll_ctrl', (('pll_bypass_force', 0),
('pll_bypass_qual', 0)),force,warn)
if 'ARM' in self.pll_fdivs:
clk_register_set.set_bitfields('arm_pll_ctrl',(('pll_bypass_force', 0),
('pll_bypass_qual', 0)),force,warn)
# Do after PLL bypass and Reset - stage 5 of clocks setup #clocks setup
def clocks_rbl_program(self,force=False,warn=False): def clocks_program(self,force=False,warn=False):
clk_register_set=self.clk_register_set clk_register_set=self.clk_register_set
# PLLs are now bypassed and reset, now program # PLLs are now bypassed and reset, now program
# reg arm_clk_ctrl, offs=0x120 dflt:0x1f000400 actual: 0x1f000200 # reg arm_clk_ctrl, offs=0x120 dflt:0x1f000400 actual: 0x1f000200
......
ezynq_ddr.py
View file @ 2d6c690c
...@@ -243,21 +243,24 @@ class EzynqDDR: ...@@ -243,21 +243,24 @@ class EzynqDDR:
return (address_mapping,page_mask) return (address_mapping,page_mask)
def get_new_register_sets(self): def get_new_register_sets(self):
# return self.ddrc_register_sets['MAIN'].get_register_sets(True,True)
return self.ddrc_register_set.get_register_sets(True,True) return self.ddrc_register_set.get_register_sets(True,True)
def get_ddr_type(self): def get_ddr_type(self):
return self.features.get_par_value('MEMORY_TYPE') return self.features.get_par_value('MEMORY_TYPE')
# Start DDR initialization procedure (unlock DDRC)
def ddr_start(self,current_reg_sets,force=False,warn=False):
ddrc_register_set=self.ddrc_register_set
ddrc_register_set.set_initial_state(current_reg_sets, True)
ddrc_register_set.set_bitfields('ddrc_ctrl',(('reg_ddrc_soft_rstb', 0x1)),force,warn)
return ddrc_register_set.get_register_sets(True,True)
def ddr_init_memory(self,current_reg_sets,force=False,warn=False): def ddr_init_memory(self,current_reg_sets,force=False,warn=False):
# print 'ddr_init_memory, len(current_reg_sets)=',len(current_reg_sets),'\n' # print 'ddr_init_memory, len(current_reg_sets)=',len(current_reg_sets),'\n'
if not self.features.get_par_value('ENABLE'): if not self.features.get_par_value('ENABLE'):
print 'DDR configuration is disabled' print 'DDR configuration is disabled'
# do some stuff (write regs, output) # do some stuff (write regs, output)
return return
# ddriob_register_set=self.ddriob_register_sets['MAIN']
# ddrc_register_set= self.ddrc_register_sets['MAIN']
ddriob_register_set=self.ddriob_register_set ddriob_register_set=self.ddriob_register_set
ddrc_register_set= self.ddrc_register_set ddrc_register_set= self.ddrc_register_set
ddriob_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state ddriob_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state
...@@ -268,8 +271,7 @@ class EzynqDDR: ...@@ -268,8 +271,7 @@ class EzynqDDR:
self.ddr_init_ddrc(force,warn) self.ddr_init_ddrc(force,warn)
return ddrc_register_set.get_register_sets(True,True) return ddrc_register_set.get_register_sets(True,True)
def ddr_init_ddrc(self,force=False,warn=False): # will program to sequence 'MAIN' def ddr_init_ddrc(self,force=False,warn=False):
# ddrc_register_set=self.ddrc_register_sets['MAIN']
ddrc_register_set=self.ddrc_register_set ddrc_register_set=self.ddrc_register_set
is_LPDDR2= (self.features.get_par_value('MEMORY_TYPE')=='LPDDR2') is_LPDDR2= (self.features.get_par_value('MEMORY_TYPE')=='LPDDR2')
is_DDR3L= (self.features.get_par_value('MEMORY_TYPE')=='DDR3L') is_DDR3L= (self.features.get_par_value('MEMORY_TYPE')=='DDR3L')
...@@ -1322,6 +1324,23 @@ class EzynqDDR: ...@@ -1322,6 +1324,23 @@ class EzynqDDR:
),force,warn) ),force,warn)
########################################## ##########################################
def ddr_dci_calibrate(self,current_reg_sets,force=False,warn=False):
ddriob_register_set=self.ddriob_register_set
ddriob_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state
ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('reset',1),force,warn)
_ = ddriob_register_set.get_register_sets(True,True) # close previous register settings
ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('reset',0),force,warn)
_ = ddriob_register_set.get_register_sets(True,True) # close previous register settings
ddriob_register_set.set_bitfields('ddriob_dci_ctrl', (('reset', 1),
('enable',1),
('nref_opt1',0),
('nref_opt2',0),
('nref_opt4',1),
('pref_opt2',0),
('update_control',0)),force,warn)
return ddriob_register_set.get_register_sets(True,True) # close previous register settings, return new result
def ddr_init_ddriob(self,force=False,warn=False): # will program to sequence 'MAIN' def ddr_init_ddriob(self,force=False,warn=False): # will program to sequence 'MAIN'
# print 'ddr_init_ddriob\n' # print 'ddr_init_ddriob\n'
# ddriob_register_set=self.ddriob_register_sets['MAIN'] # ddriob_register_set=self.ddriob_register_sets['MAIN']
...@@ -1424,23 +1443,24 @@ class EzynqDDR: ...@@ -1424,23 +1443,24 @@ class EzynqDDR:
('slew_p', self.features.get_par_value('BIDIR_SLEW_POS')), ('slew_p', self.features.get_par_value('BIDIR_SLEW_POS')),
('drive_n',self.features.get_par_value('BIDIR_DRIVE_NEG')), ('drive_n',self.features.get_par_value('BIDIR_DRIVE_NEG')),
('drive_p',self.features.get_par_value('BIDIR_DRIVE_POS'))),force,warn) #0xf9861c ('drive_p',self.features.get_par_value('BIDIR_DRIVE_POS'))),force,warn) #0xf9861c
#Trying toggle feature (but actually for now it can be left in reset state - is this on/off/on needed? #
_ = ddriob_register_set.get_register_sets(True,True) # close previous register settings # #Trying toggle feature (but actually for now it can be left in reset state - is this on/off/on needed?
# ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('vrn_out',0),force,warn) # default value shows 1, actual settings - 0 (first time only?) # _ = ddriob_register_set.get_register_sets(True,True) # close previous register settings
# # # ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('vrn_out',0),force,warn) # default value shows 1, actual settings - 0 (first time only?)
# Do in u-boot. When moving - use UG585 table 10-7 to set options # #
# # # Do in u-boot. When moving - use UG585 table 10-7 to set options
ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('reset',1),force,warn) # #
_ = ddriob_register_set.get_register_sets(True,True) # close previous register settings # ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('reset',1),force,warn)
ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('reset',0),force,warn) # _ = ddriob_register_set.get_register_sets(True,True) # close previous register settings
_ = ddriob_register_set.get_register_sets(True,True) # close previous register settings # ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('reset',0),force,warn)
ddriob_register_set.set_bitfields('ddriob_dci_ctrl', (('reset', 1), # _ = ddriob_register_set.get_register_sets(True,True) # close previous register settings
('enable',1), # ddriob_register_set.set_bitfields('ddriob_dci_ctrl', (('reset', 1),
('nref_opt1',0), # ('enable',1),
('nref_opt2',0), # ('nref_opt1',0),
('nref_opt4',1), # ('nref_opt2',0),
('pref_opt2',0), # ('nref_opt4',1),
('update_control',0)),force,warn) # ('pref_opt2',0),
# ('update_control',0)),force,warn)
#TODO: Remove? #TODO: Remove?
......
ezynq_ddrc_defs.py
View file @ 2d6c690c
...@@ -25,7 +25,8 @@ __status__ = "Development" ...@@ -25,7 +25,8 @@ __status__ = "Development"
DDRC_DEFS={ #not all fields are defined currently DDRC_DEFS={ #not all fields are defined currently
'BASE_ADDR':(0xF8006000,), 'BASE_ADDR':(0xF8006000,),
'MODULE_NAME':('ddrc',), 'MODULE_NAME':('ddrc',),
'ddrc_ctrl': {'OFFS': 0x000,'DFLT':0x00000200,'RW':'RW','FIELDS':{ #0x81 'ddrc_ctrl': {'OFFS': 0x000,'DFLT':0x00000200,'RW':'RW','COMMENTS':'DDRC control: refresh, power down, initialize, debug',
'FIELDS':{ #0x81
'reg_ddrc_dis_auto_refresh':{'r':(16,16),'d':0,'c':'Dynamic. 1 - disable autorefresh'}, 'reg_ddrc_dis_auto_refresh':{'r':(16,16),'d':0,'c':'Dynamic. 1 - disable autorefresh'},
'reg_ddrc_dis_act_bypass': {'r':(15,15),'d':0,'c':'Debug. 1 - disable bypass for high priority read activity'}, 'reg_ddrc_dis_act_bypass': {'r':(15,15),'d':0,'c':'Debug. 1 - disable bypass for high priority read activity'},
'reg_ddrc_dis_rd_bypass': {'r':(14,14),'d':0,'c':'Debug. 1 - disable bypass for high priority read page hits'}, 'reg_ddrc_dis_rd_bypass': {'r':(14,14),'d':0,'c':'Debug. 1 - disable bypass for high priority read page hits'},
......
ezynq_registers.py
View file @ 2d6c690c
...@@ -41,13 +41,15 @@ def print_html_reg_footer(html_file): ...@@ -41,13 +41,15 @@ def print_html_reg_footer(html_file):
return return
html_file.write('</table>\n') html_file.write('</table>\n')
def print_html_registers(html_file, reg_sets, show_bit_fields=True, show_comments=True,filter_fields=True): def print_html_registers(html_file, reg_sets, from_index, show_bit_fields=True, show_comments=True,filter_fields=True,all_used_fields=False):
if not html_file: if not html_file:
return return
# new_sets.append((addr,data,mask,self.module_name,register_name,self.registers[register_name])) # new_sets.append((addr,data,mask,self.module_name,register_name,self.registers[register_name]))
current_reg_state={} #address: (data,mask) current_reg_state={} #address: (data,mask)
for addr, data, mask, module_name, register_name, r_def in reg_sets: for index, (addr, data, mask, module_name, register_name, r_def) in enumerate (reg_sets):
# if addr==0xf8000100:
# print 'index=',index,' addr=',hex(addr),' data=',hex(data),' mask=',hex(mask)
if mask!=0: if mask!=0:
try: try:
dflt_data=r_def['DFLT'] dflt_data=r_def['DFLT']
...@@ -59,13 +61,20 @@ def print_html_registers(html_file, reg_sets, show_bit_fields=True, show_comment ...@@ -59,13 +61,20 @@ def print_html_registers(html_file, reg_sets, show_bit_fields=True, show_comment
rw='RW' rw='RW'
try: try:
old_data,old_mask=current_reg_state[addr] old_data,old_mask=current_reg_state[addr]
if not all_used_fields:
old_mask=0
prev_sdata=hex(old_data) prev_sdata=hex(old_data)
except: except:
old_data=dflt_data old_data=dflt_data
old_mask=0 old_mask=0
prev_sdata='-' prev_sdata='-'
new_data=((old_data ^ data) & mask) ^ old_data new_data=((old_data ^ data) & mask) ^ old_data
new_mask= old_mask | mask new_mask= old_mask | mask
current_reg_state[addr]=(new_data,new_mask)
if index<from_index: # just accumulate previous history of the register mask/values, no output
continue
html_file.write('<tr>\n') html_file.write('<tr>\n')
try: try:
comments=r_def['COMMENTS'] comments=r_def['COMMENTS']
...@@ -114,7 +123,42 @@ def print_html_registers(html_file, reg_sets, show_bit_fields=True, show_comment ...@@ -114,7 +123,42 @@ def print_html_registers(html_file, reg_sets, show_bit_fields=True, show_comment
if show_comments: if show_comments:
html_file.write('<td>'+comments+'</td>') html_file.write('<td>'+comments+'</td>')
html_file.write('\n</tr>\n') html_file.write('\n</tr>\n')
current_reg_state[addr]=(new_data,new_mask)
# for i,_ in enumerate
# def set_initial_state(self,added_reg_sets, init=True):
# if init:
# self.initial_state={}
# self.previous_reg_sets=[]
# try:
# self.initial_register_count=len(added_reg_sets)
# except:
# self.initial_register_count=0
# if not added_reg_sets:
# return
# # print added_reg_sets
# self.previous_reg_sets+=added_reg_sets # appends, not overwrites
# for addr,data,mask,_,_,_ in added_reg_sets: # Do not need to care about default values - they will have 0 in the mask bits.
# if addr in self.initial_state:
# old_data,old_mask=self.initial_state[addr]
# data=((old_data ^ data) & mask) ^ old_data
# mask |= old_mask
# self.initial_state[addr]=(data,mask)
def accumulate_reg_data(reg_sets,accumulate_mask=False):
initial_state={}
cumulative_regs=[() for _ in reg_sets]
for index, (addr, data, mask, module_name, register_name, r_def) in enumerate (reg_sets):
if addr in initial_state:
old_data,old_mask=initial_state[addr]
data=((old_data ^ data) & mask) ^ old_data
if accumulate_mask:
mask |= old_mask
initial_state[addr]=(data,mask)
cumulative_regs[index]=(addr, data, mask, module_name, register_name, r_def)
return cumulative_regs
class EzynqRegisters: class EzynqRegisters:
...@@ -172,22 +216,34 @@ class EzynqRegisters: ...@@ -172,22 +216,34 @@ class EzynqRegisters:
self.previous_reg_sets+=added_reg_sets # appends, not overwrites self.previous_reg_sets+=added_reg_sets # appends, not overwrites
for addr,data,mask,_,_,_ in added_reg_sets: # Do not need to care about default values - they will have 0 in the mask bits. for addr,data,mask,_,_,_ in added_reg_sets: # Do not need to care about default values - they will have 0 in the mask bits.
if addr in self.initial_state: if addr in self.initial_state:
old_data,old_mask=self.initial_state[addr] # old_data,old_mask=self.initial_state[addr]
old_data,_=self.initial_state[addr]
data=((old_data ^ data) & mask) ^ old_data data=((old_data ^ data) & mask) ^ old_data
mask |= old_mask # mask |= old_mask
self.initial_state[addr]=(data,mask) # self.initial_state[addr]=(data,mask)
self.initial_state[addr]=(data,0) # ignoring old mask - only accumulating newely set bits in this set
def get_reg_names(self): def get_reg_names(self):
# name_offs=sorted([(name,self.registers[name]['OFFS']) for name in self.registers], key = lambda l: l[1])
# print '---self.registers=',self.registers
# unsorted_name_offs=[(name,self.defs[name]['OFFS']) for name in self.registers]
# print '---unsorted_name_offs=',unsorted_name_offs
# name_offs=sorted(unsorted_name_offs, key = lambda l: l[1])
# print '---name_offs=',name_offs
# return [n for n in name_offs]
# sort register names in the order of addresses
# return [n for n in sorted([(name,self.defs[name]['OFFS']) for name in self.registers], key = lambda l: l[1])]
return [n[0] for n in sorted([(name,self.defs[name]['OFFS']) for name in self.registers], key = lambda l: l[1])] return [n[0] for n in sorted([(name,self.defs[name]['OFFS']) for name in self.registers], key = lambda l: l[1])]
def get_register_comments(self,register_name):
try:
return self.defs[register_name]['COMMENTS']
except:
return ''
def get_bitfield_address_mask_comments(self,register_name,field_name): #channel is implied in self
try:
bit_field=self.defs[register_name]['FIELDS'][field_name]
except:
raise Exception (self.ERRORS['ERR_FIELD']+' '+register_name+'.'+field_name)
mask=self._mask(bit_field['r'])
try:
comments=bit_field['c']
except:
comments=''
addr=self.base_addr+self.defs[register_name]['OFFS']
return (addr,mask,comments)
#number of registers set before this module (can be removed from the result of get_register_sets(sort_addr=True,apply_new=True)) #number of registers set before this module (can be removed from the result of get_register_sets(sort_addr=True,apply_new=True))
def get_initial_count(self): def get_initial_count(self):
......
ezynqcfg.py
View file @ 2d6c690c
...@@ -28,6 +28,7 @@ import ezynq_ddr ...@@ -28,6 +28,7 @@ import ezynq_ddr
import ezynq_registers import ezynq_registers
import ezynq_mio import ezynq_mio
import ezynq_clk import ezynq_clk
import ezynq_uboot
parser = argparse.ArgumentParser() parser = argparse.ArgumentParser()
parser.add_argument('-v', '--verbosity', action='count', help='increase output verbosity') parser.add_argument('-v', '--verbosity', action='count', help='increase output verbosity')
parser.add_argument('-c', '--configs', help='Configuration file (such as autoconf.mk)') parser.add_argument('-c', '--configs', help='Configuration file (such as autoconf.mk)')
...@@ -35,7 +36,8 @@ parser.add_argument('-w', '--warn', help='Warn when the pin function is ove ...@@ -35,7 +36,8 @@ parser.add_argument('-w', '--warn', help='Warn when the pin function is ove
parser.add_argument('-o', '--outfile', help='Path to save the generated boot file') parser.add_argument('-o', '--outfile', help='Path to save the generated boot file')
parser.add_argument('--html', help='Generate HTML map of MIO, save to the specified file') parser.add_argument('--html', help='Generate HTML map of MIO, save to the specified file')
parser.add_argument('--html-mask', help='Bit mask of what data to include in the HTML MIO map') parser.add_argument('--html-mask', help='Bit mask of what data to include in the HTML MIO map')
parser.add_argument('-i', '--include', help='Generate include file for u-boot') #parser.add_argument('-i', '--include', help='Generate include file for u-boot')
parser.add_argument('-l', '--lowlevel', help='path to the lowlevel.c file to be generated for u-boot')
args = parser.parse_args() args = parser.parse_args()
#print args #print args
...@@ -276,17 +278,7 @@ def write_include(filename,reg_sets): ...@@ -276,17 +278,7 @@ def write_include(filename,reg_sets):
def write_image(image,name): def write_image(image,name):
bf=open(name,'wb') bf=open(name,'wb')
# data=struct.pack('<'+len(image)*'I', image)
# data=struct.pack('I' * len(image), *image)
# print tuple(image)
# data=struct.pack('I' * len(image), tuple(image))
# N=19
# print len(image[:N]), image[:N]
# data=struct.pack('I' * len(image), *image[0:10])
data=struct.pack('I' * len(image), *image) data=struct.pack('I' * len(image), *image)
# s=struct.Struct('I')
# data=s.pack(*image)
bf.write(data) bf.write(data)
bf.close() bf.close()
...@@ -354,6 +346,10 @@ reg_sets=[] ...@@ -354,6 +346,10 @@ reg_sets=[]
reg_sets=mio_regs.setregs_mio(reg_sets,force) # reg Sets include now MIO reg_sets=mio_regs.setregs_mio(reg_sets,force) # reg Sets include now MIO
num_mio_regs=len(reg_sets) num_mio_regs=len(reg_sets)
# should be always True, probably
clk_in_uboot= not (raw_config_value('CONFIG_EZYNQ_SKIP_CLK', raw_configs) is None)
#adding ddr registers #adding ddr registers
if raw_config_value('CONFIG_EZYNQ_SKIP_DDR', raw_configs) is None: if raw_config_value('CONFIG_EZYNQ_SKIP_DDR', raw_configs) is None:
ddr.ddr_init_memory(reg_sets,False,False) ddr.ddr_init_memory(reg_sets,False,False)
...@@ -368,46 +364,74 @@ num_ddr_regs=len(reg_sets)-num_mio_regs ...@@ -368,46 +364,74 @@ num_ddr_regs=len(reg_sets)-num_mio_regs
#initialize clocks #initialize clocks
# def clocks_rbl_setup(self,current_reg_sets,force=False,warn=False): # unlock slcr - it is locked by RBL, but attempt to unlock in RBL will fail (and hang the system)
#if raw_config_value('CONFIG_EZYNQ_SKIP_CLK', raw_configs) is None: clk.clocks_regs_setup(reg_sets,clk_in_uboot,force) # reg Sets include now MIO and CLK
clk.clocks_rbl_setup(reg_sets,force) # reg Sets include now MIO and CLK
reg_sets=clk.get_new_register_sets() # mio, ddr and clk reg_sets=clk.get_new_register_sets() # mio, ddr and clk
#else:
# print 'Debug mode: skipping CLK/PLL configuration'
num_clk_regs=len(reg_sets)-num_mio_regs-num_ddr_regs num_clk_regs=len(reg_sets)-num_mio_regs-num_ddr_regs
len_before_pll=len(reg_sets)
if raw_config_value('CONFIG_EZYNQ_SKIP_CLK', raw_configs) is None: len_before_dci_calibrate=len(reg_sets)
len_before_ddr_start=len(reg_sets)
if clk_in_uboot:
num_rbl_regs=len_before_pll-num_clk_regs
print 'Debug mode: CLK/PLL configuration by u-boot'
clk.clocks_pll_bypass_off(reg_sets,force) # reg Sets include now MIO and CLK
reg_sets=clk.get_new_register_sets() # mio, ddr and clk, pll
len_before_dci_calibrate=len(reg_sets)
num_pll_regs=len_before_dci_calibrate-len_before_pll
reg_sets=ddr.ddr_dci_calibrate(reg_sets,False,False)
len_before_ddr_start=len(reg_sets)
num_dci_init_regs=len_before_ddr_start-len_before_dci_calibrate
reg_sets=ddr.ddr_start(reg_sets,False,False)
else:
num_rbl_regs=len(reg_sets) num_rbl_regs=len(reg_sets)
print 'Debug mode: CLK/PLL configuration by RBL' print 'Debug mode: CLK/PLL configuration by RBL'
else: num_pll_regs=0
num_rbl_regs=len(reg_sets)-num_clk_regs
print 'Debug mode: CLK/PLL configuration by u-boot' #clocks_pll_bypass_off(self,force=False,warn=False):
# def clocks_pll_bypass_off(self,current_reg_sets,force=False,warn=False):
# make reg_sets data cumulative
reg_sets=ezynq_registers.accumulate_reg_data(reg_sets)
ezynq_registers.print_html_reg_header(f, 'MIO registers configuration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400) ezynq_registers.print_html_reg_header(f, 'MIO registers configuration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
#ezynq_registers.print_html_registers(f, reg_sets[:num_mio_regs], MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400) #ezynq_registers.print_html_registers(f, reg_sets[:num_mio_regs], MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_registers(f, reg_sets[:num_mio_regs], MIO_HTML_MASK & 0x800, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400) ezynq_registers.print_html_registers(f, reg_sets[:num_mio_regs], 0, MIO_HTML_MASK & 0x800, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_reg_footer(f) ezynq_registers.print_html_reg_footer(f)
ezynq_registers.print_html_reg_header(f, 'DDR Configuration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400) ezynq_registers.print_html_reg_header(f, 'DDR Configuration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_registers(f, reg_sets[num_mio_regs:num_mio_regs+num_ddr_regs], MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400) ezynq_registers.print_html_registers(f, reg_sets[:num_mio_regs+num_ddr_regs], num_mio_regs, MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_reg_footer(f) ezynq_registers.print_html_reg_footer(f)
ezynq_registers.print_html_reg_header(f, 'CLOCK registers configuration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400) ezynq_registers.print_html_reg_header(f, 'CLOCK registers configuration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_registers(f, reg_sets[num_mio_regs+num_ddr_regs:num_rbl_regs], MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400) ezynq_registers.print_html_registers(f, reg_sets[:num_rbl_regs], num_mio_regs+num_ddr_regs, MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_reg_footer(f) ezynq_registers.print_html_reg_footer(f)
if len(reg_sets)>num_rbl_regs: if len(reg_sets)>num_rbl_regs:
ezynq_registers.print_html_reg_header(f, 'Registers configuration in u-boot', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400) ezynq_registers.print_html_reg_header(f, 'Registers configuration in u-boot', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_registers(f, reg_sets[num_rbl_regs:], MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400) ezynq_registers.print_html_registers(f, reg_sets[:len_before_pll], num_rbl_regs, MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_reg_footer(f)
if len(reg_sets)>len_before_pll:
ezynq_registers.print_html_reg_header(f, 'Registers configuration in u-boot after PLLs are locked', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_registers(f, reg_sets[:len_before_dci_calibrate],len_before_pll, MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_reg_footer(f) ezynq_registers.print_html_reg_footer(f)
if len(reg_sets)>len_before_pll:
ezynq_registers.print_html_reg_header(f, 'Registers configuration in u-boot for DDR DCI calibration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_registers(f, reg_sets[:len_before_ddr_start],len_before_dci_calibrate, MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_reg_footer(f)
if len(reg_sets)>len_before_ddr_start:
ezynq_registers.print_html_reg_header(f, 'Registers configuration in u-boot to start DDR initialization', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_registers(f, reg_sets,len_before_ddr_start, MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_reg_footer(f)
#TODO: Need to be modified for the new format #TODO: Need to be modified for the new format
# if 'CONFIG_EZYNQ_UART_LOOPBACK_0' in raw_options: uart_remote_loopback(registers,f, 0,MIO_HTML_MASK) # if 'CONFIG_EZYNQ_UART_LOOPBACK_0' in raw_options: uart_remote_loopback(registers,f, 0,MIO_HTML_MASK)
...@@ -415,7 +439,7 @@ if len(reg_sets)>num_rbl_regs: ...@@ -415,7 +439,7 @@ if len(reg_sets)>num_rbl_regs:
if f: if f:
f.write('<h4>Total number of registers set up in the RBL header is <b>'+str(num_rbl_regs)+"</b> of maximal 256</h4>") f.write('<h4>Total number of registers set up in the RBL header is <b>'+str(num_rbl_regs)+"</b> of maximal 256</h4>")
if num_rbl_regs<len(reg_sets): if num_rbl_regs<len(reg_sets):
f.write('<h4>Number of registers set up in u-boot is <b>'+str(len(reg_sets)-num_rbl_regs)+"</b> of maximal 256</h4>") f.write('<h4>Number of registers set up in u-boot is <b>'+str(len(reg_sets)-num_rbl_regs)+"</b></h4>")
# #
if MIO_HTML: if MIO_HTML:
f.close f.close
...@@ -439,9 +463,16 @@ image_generator (image, ...@@ -439,9 +463,16 @@ image_generator (image,
int(raw_options['CONFIG_EZYNQ_START_EXEC'],0)) #start_exec) int(raw_options['CONFIG_EZYNQ_START_EXEC'],0)) #start_exec)
if args.outfile: if args.outfile:
write_image(image,args.outfile) write_image(image,args.outfile)
if args.include and (num_rbl_regs<len(reg_sets)):
write_include(args.include,reg_sets[num_rbl_regs:]) # if args.include and (num_rbl_regs<len(reg_sets)):
print 'Debug mode: writing u-boot setup registers to ',args.include # write_include(args.include,reg_sets[num_rbl_regs:])
# print int(hex(1234567),0) # works for decimal and hex # print 'Debug mode: writing u-boot setup registers to ',args.include
u_boot=ezynq_uboot.EzynqUBoot(args.verbosity)
u_boot.registers_setup (reg_sets[num_rbl_regs:len_before_pll],clk,num_rbl_regs)
u_boot.pll_setup (reg_sets[len_before_pll:len_before_dci_calibrate],clk)
u_boot.dci_calibration(reg_sets[len_before_dci_calibrate:len_before_ddr_start],ddr)
u_boot.ddr_start (reg_sets[len_before_ddr_start:],ddr)
u_boot.make_lowlevel_init()
u_boot.output_c_file(args.lowlevel)
#print u_boot.get_c_file()
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