Generating lowlevel.c for u-boot (2d6c690c) · Commits · Elphel / ezynq

ezynq_clk.py

+39 −14

Original line number	Diff line number	Diff line
		@@ -340,7 +340,8 @@ class EzynqClk:
		clk=self.iface_divs[name]
		if (not 'PLL' in clk ) and (not 'FREQ' in clk):
		self.iface_divs[name]['FREQ']=self.iface_divs[self.iface_divs[name]['SOURCE']]['FREQ'] # same frequency - possible to use 'VALUE' as scale

		def get_plls_used (self):
		return set([pll for pll in self.pll_fdivs])

		def html_list_clocks(self,html_file):
		def list_with_children(name):
		@@ -411,23 +412,26 @@ class EzynqClk:
		def get_new_register_sets(self):
		return self.clk_register_set.get_register_sets(True,True)

		def clocks_rbl_setup(self,current_reg_sets,force=False,warn=False):
		def clocks_regs_setup(self,current_reg_sets,unlock_needed=True,force=False,warn=False):
		clk_register_set=self.clk_register_set
		clk_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state
		if unlock_needed:
		self.slcr_unlock()
		_ = clk_register_set.get_register_sets(True,True) # close previous register settings
		# Bypass used PLL-s - stage 1 of PLL setup
		self.clocks_rbl_pll_bypass(force=False,warn=False)
		self.clocks_pll_bypass(force=False,warn=False)
		_ = clk_register_set.get_register_sets(True,True) # close previous register settings
		# Turn on PLL reset and program feedback - stage 2 of PLL setup
		self.clocks_rbl_pll_reset_and_fdiv(force=False,warn=False)
		self.clocks_pll_reset_and_fdiv(force=False,warn=False)
		_ = clk_register_set.get_register_sets(True,True) # close previous register settings
		# Configure PLL parameters - stage 3 of PLL setup
		self.clocks_rbl_pll_conf(force=False,warn=False)
		self.clocks_pll_conf(force=False,warn=False)
		_ = clk_register_set.get_register_sets(True,True) # close previous register settings
		# Release reset of the PLLs (let them start) - stage 4 of PLL setup
		self.clocks_rbl_pll_start(force=False,warn=False)
		self.clocks_pll_start(force=False,warn=False)
		_ = clk_register_set.get_register_sets(True,True) # close previous register settings
		# Do after PLL bypass and Reset - stage 5 of clocks setup
		self.clocks_rbl_program(force=False,warn=False)
		# stage 5 of clocks setup
		self.clocks_program(force=False,warn=False)

		# #Trying toggle feature (but actually for now it can be left in reset state - is this on/off/on needed?
		# _ = ddriob_register_set.get_register_sets(True,True) # close previous register settings
		@@ -445,8 +449,15 @@ class EzynqClk:



		#Unlock SLCR (if the code is running after RBL) - stage 0 of PLL setup
		def slcr_unlock(self):
		clk_register_set=self.clk_register_set
		if self.verbosity>0 :
		print 'Unlocking SLCR'
		clk_register_set.set_word('slcr_unlock',0xdf0d)

		#Bypass used PLL-s - stage 1 of PLL setup
		def clocks_rbl_pll_bypass(self,force=False,warn=False):
		def clocks_pll_bypass(self,force=False,warn=False):
		clk_register_set=self.clk_register_set
		if self.verbosity>0 :
		print 'pll_fdivs=', self.pll_fdivs
		@@ -464,7 +475,7 @@ class EzynqClk:
		('pll_bypass_force', 1)),force,warn)

		# Turn on PLL reset and program feedback - stage 2 of PLL setup
		def clocks_rbl_pll_reset_and_fdiv(self,force=False,warn=False):
		def clocks_pll_reset_and_fdiv(self,force=False,warn=False):
		clk_register_set=self.clk_register_set
		if 'DDR' in self.pll_fdivs:
		clk_register_set.set_bitfields('ddr_pll_ctrl',( #
		@@ -480,7 +491,7 @@ class EzynqClk:
		('pll_reset', 1)),force,warn)

		# Configure PLL parameters - stage 3 of PLL setup
		def clocks_rbl_pll_conf(self,force=False,warn=False):
		def clocks_pll_conf(self,force=False,warn=False):
		clk_register_set=self.clk_register_set
		if 'DDR' in self.pll_fdivs:
		ddr_fdiv=self.pll_fdivs['DDR']
		@@ -504,7 +515,7 @@ class EzynqClk:
		('pll_res', self.pll_pars[arm_fdiv]['PLL_RES']), # PLL loop filter resistor control
		),force,warn)
		# Release reset of the PLLs (let them start) - stage 4 of PLL setup
		def clocks_rbl_pll_start(self,force=False,warn=False):
		def clocks_pll_start(self,force=False,warn=False):
		clk_register_set=self.clk_register_set
		if 'DDR' in self.pll_fdivs:
		clk_register_set.set_bitfields('ddr_pll_ctrl',(('pll_reset', 0)),force,warn)
		@@ -513,9 +524,23 @@ class EzynqClk:
		if 'ARM' in self.pll_fdivs:
		clk_register_set.set_bitfields('arm_pll_ctrl',(('pll_reset', 0)),force,warn)

		# Release bypass the PLLs (PLLs should be locked already!)
		def clocks_pll_bypass_off(self,current_reg_sets,force=False,warn=False):
		clk_register_set=self.clk_register_set
		clk_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state

		if 'DDR' in self.pll_fdivs:
		clk_register_set.set_bitfields('ddr_pll_ctrl',(('pll_bypass_force', 0),
		('pll_bypass_qual', 0)),force,warn)
		if 'IO' in self.pll_fdivs:
		clk_register_set.set_bitfields('io_pll_ctrl', (('pll_bypass_force', 0),
		('pll_bypass_qual', 0)),force,warn)
		if 'ARM' in self.pll_fdivs:
		clk_register_set.set_bitfields('arm_pll_ctrl',(('pll_bypass_force', 0),
		('pll_bypass_qual', 0)),force,warn)

		# Do after PLL bypass and Reset - stage 5 of clocks setup
		def clocks_rbl_program(self,force=False,warn=False):
		#clocks setup
		def clocks_program(self,force=False,warn=False):
		clk_register_set=self.clk_register_set
		# PLLs are now bypassed and reset, now program
		# reg arm_clk_ctrl, offs=0x120 dflt:0x1f000400 actual: 0x1f000200

ezynq_ddr.py

+43 −23

Original line number	Diff line number	Diff line
		@@ -243,21 +243,24 @@ class EzynqDDR:
		return (address_mapping,page_mask)

		def get_new_register_sets(self):
		# return self.ddrc_register_sets['MAIN'].get_register_sets(True,True)
		return self.ddrc_register_set.get_register_sets(True,True)

		def get_ddr_type(self):
		return self.features.get_par_value('MEMORY_TYPE')

		# Start DDR initialization procedure (unlock DDRC)
		def ddr_start(self,current_reg_sets,force=False,warn=False):
		ddrc_register_set=self.ddrc_register_set
		ddrc_register_set.set_initial_state(current_reg_sets, True)
		ddrc_register_set.set_bitfields('ddrc_ctrl',(('reg_ddrc_soft_rstb', 0x1)),force,warn)
		return ddrc_register_set.get_register_sets(True,True)

		def ddr_init_memory(self,current_reg_sets,force=False,warn=False):
		# print 'ddr_init_memory, len(current_reg_sets)=',len(current_reg_sets),'\n'
		if not self.features.get_par_value('ENABLE'):
		print 'DDR configuration is disabled'
		# do some stuff (write regs, output)
		return

		# ddriob_register_set=self.ddriob_register_sets['MAIN']
		# ddrc_register_set= self.ddrc_register_sets['MAIN']
		ddriob_register_set=self.ddriob_register_set
		ddrc_register_set= self.ddrc_register_set
		ddriob_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state
		@@ -268,8 +271,7 @@ class EzynqDDR:
		self.ddr_init_ddrc(force,warn)
		return ddrc_register_set.get_register_sets(True,True)

		def ddr_init_ddrc(self,force=False,warn=False): # will program to sequence 'MAIN'
		# ddrc_register_set=self.ddrc_register_sets['MAIN']
		def ddr_init_ddrc(self,force=False,warn=False):
		ddrc_register_set=self.ddrc_register_set
		is_LPDDR2= (self.features.get_par_value('MEMORY_TYPE')=='LPDDR2')
		is_DDR3L= (self.features.get_par_value('MEMORY_TYPE')=='DDR3L')
		@@ -1322,6 +1324,23 @@ class EzynqDDR:
		),force,warn)
		##########################################

		def ddr_dci_calibrate(self,current_reg_sets,force=False,warn=False):
		ddriob_register_set=self.ddriob_register_set
		ddriob_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state
		ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('reset',1),force,warn)
		_ = ddriob_register_set.get_register_sets(True,True) # close previous register settings
		ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('reset',0),force,warn)
		_ = ddriob_register_set.get_register_sets(True,True) # close previous register settings
		ddriob_register_set.set_bitfields('ddriob_dci_ctrl', (('reset', 1),
		('enable',1),
		('nref_opt1',0),
		('nref_opt2',0),
		('nref_opt4',1),
		('pref_opt2',0),
		('update_control',0)),force,warn)
		return ddriob_register_set.get_register_sets(True,True) # close previous register settings, return new result


		def ddr_init_ddriob(self,force=False,warn=False): # will program to sequence 'MAIN'
		# print 'ddr_init_ddriob\n'
		# ddriob_register_set=self.ddriob_register_sets['MAIN']
		@@ -1424,23 +1443,24 @@ class EzynqDDR:
		('slew_p', self.features.get_par_value('BIDIR_SLEW_POS')),
		('drive_n',self.features.get_par_value('BIDIR_DRIVE_NEG')),
		('drive_p',self.features.get_par_value('BIDIR_DRIVE_POS'))),force,warn) #0xf9861c
		#Trying toggle feature (but actually for now it can be left in reset state - is this on/off/on needed?
		_ = ddriob_register_set.get_register_sets(True,True) # close previous register settings
		# ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('vrn_out',0),force,warn) # default value shows 1, actual settings - 0 (first time only?)
		#
		# Do in u-boot. When moving - use UG585 table 10-7 to set options
		#
		ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('reset',1),force,warn)
		_ = ddriob_register_set.get_register_sets(True,True) # close previous register settings
		ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('reset',0),force,warn)
		_ = ddriob_register_set.get_register_sets(True,True) # close previous register settings
		ddriob_register_set.set_bitfields('ddriob_dci_ctrl', (('reset', 1),
		('enable',1),
		('nref_opt1',0),
		('nref_opt2',0),
		('nref_opt4',1),
		('pref_opt2',0),
		('update_control',0)),force,warn)
		# #Trying toggle feature (but actually for now it can be left in reset state - is this on/off/on needed?
		# _ = ddriob_register_set.get_register_sets(True,True) # close previous register settings
		# # ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('vrn_out',0),force,warn) # default value shows 1, actual settings - 0 (first time only?)
		# #
		# # Do in u-boot. When moving - use UG585 table 10-7 to set options
		# #
		# ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('reset',1),force,warn)
		# _ = ddriob_register_set.get_register_sets(True,True) # close previous register settings
		# ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('reset',0),force,warn)
		# _ = ddriob_register_set.get_register_sets(True,True) # close previous register settings
		# ddriob_register_set.set_bitfields('ddriob_dci_ctrl', (('reset', 1),
		# ('enable',1),
		# ('nref_opt1',0),
		# ('nref_opt2',0),
		# ('nref_opt4',1),
		# ('pref_opt2',0),
		# ('update_control',0)),force,warn)

		#TODO: Remove?

ezynq_ddrc_defs.py

+2 −1

Original line number	Diff line number	Diff line
		@@ -25,7 +25,8 @@ __status__ = "Development"
		DDRC_DEFS={ #not all fields are defined currently
		'BASE_ADDR':(0xF8006000,),
		'MODULE_NAME':('ddrc',),
		'ddrc_ctrl': {'OFFS': 0x000,'DFLT':0x00000200,'RW':'RW','FIELDS':{ #0x81
		'ddrc_ctrl': {'OFFS': 0x000,'DFLT':0x00000200,'RW':'RW','COMMENTS':'DDRC control: refresh, power down, initialize, debug',
		'FIELDS':{ #0x81
		'reg_ddrc_dis_auto_refresh':{'r':(16,16),'d':0,'c':'Dynamic. 1 - disable autorefresh'},
		'reg_ddrc_dis_act_bypass': {'r':(15,15),'d':0,'c':'Debug. 1 - disable bypass for high priority read activity'},
		'reg_ddrc_dis_rd_bypass': {'r':(14,14),'d':0,'c':'Debug. 1 - disable bypass for high priority read page hits'},

ezynq_registers.py

+72 −16

Original line number	Diff line number	Diff line
		@@ -41,13 +41,15 @@ def print_html_reg_footer(html_file):
		return
		html_file.write('</table>\n')

		def print_html_registers(html_file, reg_sets, show_bit_fields=True, show_comments=True,filter_fields=True):
		def print_html_registers(html_file, reg_sets, from_index, show_bit_fields=True, show_comments=True,filter_fields=True,all_used_fields=False):
		if not html_file:
		return

		# new_sets.append((addr,data,mask,self.module_name,register_name,self.registers[register_name]))
		current_reg_state={} #address: (data,mask)
		for addr, data, mask, module_name, register_name, r_def in reg_sets:
		for index, (addr, data, mask, module_name, register_name, r_def) in enumerate (reg_sets):
		# if addr==0xf8000100:
		# print 'index=',index,' addr=',hex(addr),' data=',hex(data),' mask=',hex(mask)
		if mask!=0:
		try:
		dflt_data=r_def['DFLT']
		@@ -59,6 +61,8 @@ def print_html_registers(html_file, reg_sets, show_bit_fields=True, show_comment
		rw='RW'
		try:
		old_data,old_mask=current_reg_state[addr]
		if not all_used_fields:
		old_mask=0
		prev_sdata=hex(old_data)
		except:
		old_data=dflt_data
		@@ -66,6 +70,11 @@ def print_html_registers(html_file, reg_sets, show_bit_fields=True, show_comment
		prev_sdata='-'
		new_data=((old_data ^ data) & mask) ^ old_data
		new_mask= old_mask \| mask
		current_reg_state[addr]=(new_data,new_mask)

		if index<from_index: # just accumulate previous history of the register mask/values, no output
		continue

		html_file.write('<tr>\n')
		try:
		comments=r_def['COMMENTS']
		@@ -114,7 +123,42 @@ def print_html_registers(html_file, reg_sets, show_bit_fields=True, show_comment
		if show_comments:
		html_file.write('<td>'+comments+'</td>')
		html_file.write('\n</tr>\n')
		current_reg_state[addr]=(new_data,new_mask)


		# for i,_ in enumerate
		# def set_initial_state(self,added_reg_sets, init=True):
		# if init:
		# self.initial_state={}
		# self.previous_reg_sets=[]
		# try:
		# self.initial_register_count=len(added_reg_sets)
		# except:
		# self.initial_register_count=0
		# if not added_reg_sets:
		# return
		# # print added_reg_sets
		# self.previous_reg_sets+=added_reg_sets # appends, not overwrites
		# for addr,data,mask,_,_,_ in added_reg_sets: # Do not need to care about default values - they will have 0 in the mask bits.
		# if addr in self.initial_state:
		# old_data,old_mask=self.initial_state[addr]
		# data=((old_data ^ data) & mask) ^ old_data
		# mask \|= old_mask
		# self.initial_state[addr]=(data,mask)

		def accumulate_reg_data(reg_sets,accumulate_mask=False):
		initial_state={}
		cumulative_regs=[() for _ in reg_sets]
		for index, (addr, data, mask, module_name, register_name, r_def) in enumerate (reg_sets):
		if addr in initial_state:
		old_data,old_mask=initial_state[addr]
		data=((old_data ^ data) & mask) ^ old_data
		if accumulate_mask:
		mask \|= old_mask
		initial_state[addr]=(data,mask)
		cumulative_regs[index]=(addr, data, mask, module_name, register_name, r_def)
		return cumulative_regs




		class EzynqRegisters:
		@@ -172,23 +216,35 @@ class EzynqRegisters:
		self.previous_reg_sets+=added_reg_sets # appends, not overwrites
		for addr,data,mask,_,_,_ in added_reg_sets: # Do not need to care about default values - they will have 0 in the mask bits.
		if addr in self.initial_state:
		old_data,old_mask=self.initial_state[addr]
		# old_data,old_mask=self.initial_state[addr]
		old_data,_=self.initial_state[addr]
		data=((old_data ^ data) & mask) ^ old_data
		mask \|= old_mask
		self.initial_state[addr]=(data,mask)
		# mask \|= old_mask
		# self.initial_state[addr]=(data,mask)
		self.initial_state[addr]=(data,0) # ignoring old mask - only accumulating newely set bits in this set

		def get_reg_names(self):
		# name_offs=sorted([(name,self.registers[name]['OFFS']) for name in self.registers], key = lambda l: l[1])
		# print '---self.registers=',self.registers
		# unsorted_name_offs=[(name,self.defs[name]['OFFS']) for name in self.registers]
		# print '---unsorted_name_offs=',unsorted_name_offs
		# name_offs=sorted(unsorted_name_offs, key = lambda l: l[1])
		# print '---name_offs=',name_offs
		# return [n for n in name_offs]
		# sort register names in the order of addresses
		# return [n for n in sorted([(name,self.defs[name]['OFFS']) for name in self.registers], key = lambda l: l[1])]
		return [n[0] for n in sorted([(name,self.defs[name]['OFFS']) for name in self.registers], key = lambda l: l[1])]

		def get_register_comments(self,register_name):
		try:
		return self.defs[register_name]['COMMENTS']
		except:
		return ''

		def get_bitfield_address_mask_comments(self,register_name,field_name): #channel is implied in self
		try:
		bit_field=self.defs[register_name]['FIELDS'][field_name]
		except:
		raise Exception (self.ERRORS['ERR_FIELD']+' '+register_name+'.'+field_name)
		mask=self._mask(bit_field['r'])
		try:
		comments=bit_field['c']
		except:
		comments=''
		addr=self.base_addr+self.defs[register_name]['OFFS']
		return (addr,mask,comments)

		#number of registers set before this module (can be removed from the result of get_register_sets(sort_addr=True,apply_new=True))
		def get_initial_count(self):
		return self.initial_register_count

ezynqcfg.py

+63 −32

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