Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
E
eddr3
Project
Project
Details
Activity
Releases
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Wiki
Wiki
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Elphel
eddr3
Repository
c72a52a9b632e33e788a18374f9c6286200bc4e4
Switch branch/tag
eddr3
.settings
History
Find file
Select Archive Format
Source code
Download zip
Download tar.gz
Download tar.bz2
Download tar
write leveling done, working on write buffer
· 4bacb90a
Andrey Filippov
authored
10 years ago
4bacb90a
Name
Last commit
Last update
..
com.elphel.vdt.FPGA_project.prefs
added modules, simulating
10 years ago
com.elphel.vdt.VivadoBitstream.prefs
added missing files
10 years ago
com.elphel.vdt.VivadoPlace.prefs
working on ddr3 phy
10 years ago
com.elphel.vdt.VivadoSynthesis.prefs
added modules, simulating
10 years ago
com.elphel.vdt.VivadoTimimgSummaryReportSynthesis.prefs
working on ddr3 phy
10 years ago
com.elphel.vdt.VivadoTimingReportSynthesis.prefs
working on ddr3 phy
10 years ago
com.elphel.vdt.iverilog.prefs
write leveling done, working on write buffer
10 years ago
com.elphel.vdt.prefs
new subproject
10 years ago