just more code, debugging vdt in parallel

phy/byte_lane.v

@@ -25,7 +25,8 @@ module  byte_lane #(
     parameter IBUF_LOW_PWR ="TRUE",
     parameter IOSTANDARD_DQ = "SSTL15_T_DCI",
     parameter IOSTANDARD_DQS = "DIFF_SSTL15_T_DCI",
-    parameter SLEW = "SLOW",
+    parameter SLEW_DQ = "SLOW",
+    parameter SLEW_DQS = "SLOW",
     parameter real REFCLK_FREQUENCY = 300.0,
     parameter HIGH_PERFORMANCE_MODE = "FALSE"
 )(
@@ -47,7 +48,7 @@ module  byte_lane #(
     output [31:0] dout,            // parallel data received from DDR3 memory, 4 bits per DQ I/O
     input   [7:0] dly_data,        // delay value (3 LSB - fine delay)
     input   [4:0] dly_addr,        // select which delay to program
-    input         ld_delay,        // load delay data to selected iodelayl (clk_iv synchronous)
+    input         ld_delay,        // load delay data to selected iodelay (clk_div synchronous)
     input         set              // clk_div synchronous set all delays from previously loaded values
 );
 
@@ -96,7 +97,7 @@ generate
         .IODELAY_GRP(IODELAY_GRP),
         .IBUF_LOW_PWR(IBUF_LOW_PWR),
         .IOSTANDARD(IOSTANDARD_DQ),
-        .SLEW(SLEW),
+        .SLEW(SLEW_DQ),
         .REFCLK_FREQUENCY(REFCLK_FREQUENCY),
         .HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
     ) dq_i(
@@ -123,7 +124,7 @@ dq_single #(
         .IODELAY_GRP(IODELAY_GRP),
         .IBUF_LOW_PWR(IBUF_LOW_PWR),
         .IOSTANDARD(IOSTANDARD_DQ),
-        .SLEW(SLEW),
+        .SLEW(SLEW_DQ),
         .REFCLK_FREQUENCY(REFCLK_FREQUENCY),
         .HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
 ) dm_i(
@@ -148,7 +149,7 @@ dqs_single #(
         .IODELAY_GRP(IODELAY_GRP),
         .IBUF_LOW_PWR(IBUF_LOW_PWR),
         .IOSTANDARD(IOSTANDARD_DQS),
-        .SLEW(SLEW),
+        .SLEW(SLEW_DQS),
         .REFCLK_FREQUENCY(REFCLK_FREQUENCY),
         .HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
 ) dqs_i (

phy/cmd_addr.v

@@ -26,7 +26,7 @@ module  cmd_addr #(
     parameter SLEW =        "SLOW",
     parameter real REFCLK_FREQUENCY = 300.0,
     parameter HIGH_PERFORMANCE_MODE = "FALSE",
-    parameter ADDRESS_NUMBER=         15
+    parameter integer ADDRESS_NUMBER= 15
 )(
     output  [ADDRESS_NUMBER-1:0] ddr3_a,   // output address ports (14:0) for 4Gb device
     output  [2:0]                ddr3_ba,  // output bank address ports

phy/wrap/odelay_fine_pipe.v

@@ -23,7 +23,7 @@
 module  odelay_fine_pipe
 //SuppressWarnings VEditor - IODELAY_GRP used in (* *) construnt
 # ( parameter  IODELAY_GRP  = "IODELAY_MEMORY",
-    parameter integer DELAY_VALUE = 0,
+    parameter [7:0] DELAY_VALUE = 0,
     parameter real REFCLK_FREQUENCY = 200.0,
     parameter HIGH_PERFORMANCE_MODE    = "FALSE"
 ) (

phy/wrap/oserdes_mem.v

@@ -33,7 +33,7 @@ module  oserdes_mem #(
     output       tout_dly, // tristate out to be connected to odelay input
     output       tout_iob  // tristate out to be connected directly to the tristate control of the output buffer
 );
-localparam integer MODE_DDR_BIN=(MODE_DDR=="TRUE")?1:0;
+//localparam integer MODE_DDR_BIN=(MODE_DDR=="TRUE")?1:0;
 localparam         DATA_RATE=   (MODE_DDR=="TRUE")?"DDR":"SDR";
 localparam integer DATA_WIDTH=  (MODE_DDR=="TRUE")?4:2;
 localparam integer DDR3_DATA=   (MODE_DDR=="TRUE")?1:0;