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eddr3
Commit e61b4d60 authored by Andrey Filippov's avatar Andrey Filippov
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.project 0 → 100644
View file @ e61b4d60
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>eddr3</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>com.elphel.vdt.veditor.simulateBuilder</name>
<arguments>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.CleanCommand</key>
<value>echo &apos;Clean&apos;</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.buildOrder</key>
<value>0</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.command</key>
<value>echo &apos;No Build Configuration Specified&apos;</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.enable</key>
<value>true</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.name</key>
<value>Default</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.parser</key>
<value></value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.workFolder</key>
<value></value>
</dictionary>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>com.elphel.vdt.veditor.HdlNature</nature>
</natures>
</projectDescription>
.settings/com.elphel.vdt.prefs 0 → 100644
View file @ e61b4d60
com.elphel.store.context.=com.elphel.vdt.PROJECT_DESING_MENU<-@\#\#@->
com.elphel.vdt.PROJECT_DESING_MENU=MainDesignMenu
eclipse.preferences.version=1
unisims/AND2B1L.v 0 → 100644
View file @ e61b4d60
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 11.i (L.40)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Latch used as 2-input AND Gate
// /___/ /\ Filename : AND2B1L.v
// \ \ / \ Timestamp : Wed Apr 22 17:10:55 PDT 2009
// \___\/\___\
//
// Revision:
// 04/01/08 - Initial version.
// 04/14/09 - Invert SRI not DI (CR517897)
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module AND2B1L #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [0:0] IS_SRI_INVERTED = 1'b0
)(
output O,
input DI,
input SRI
);
tri0 GSR = glbl.GSR;
wire o_out, sri_b;
wire SRI_in;
assign O = (GSR) ? 0 : o_out;
not A0 (sri_b, SRI_in);
and A1 (o_out, sri_b, DI);
assign SRI_in = IS_SRI_INVERTED ^ SRI;
`ifdef XIL_TIMING
specify
(DI => O) = (0:0:0, 0:0:0);
(SRI => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
unisims/AUTOBUF.v 0 → 100644
View file @ e61b4d60
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/blanc/AUTOBUF.v,v 1.2 2008/09/04 22:14:49 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Clock Buffer
// /___/ /\ Filename : AUTOBUF.v
// \ \ / \ Timestamp :
// \___\/\___\
//
// Revision:
// 04/08/08 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module AUTOBUF (O, I);
parameter BUFFER_TYPE = "AUTO";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input I;
initial begin
case (BUFFER_TYPE)
"AUTO" : ;
"BUF" : ;
"BUFG" : ;
"BUFGP" : ;
"BUFH" : ;
"BUFIO" : ;
"BUFIO2" : ;
"BUFIO2FB" : ;
"BUFR" : ;
"IBUF" : ;
"IBUFG" : ;
"NONE" : ;
"OBUF" : ;
default : begin
$display("Attribute Syntax Error : The Attribute BUFFER_TYPE on AUTOBUF instance %m is set to %s. Legal values for this attribute are AUTO, BUF, BUFG, BUFGP, BUFH, BUFIO, BUFIO2, BUFIO2FB, BUFR, IBUF, IBUFG, NONE, and OBUF.", BUFFER_TYPE);
end
endcase
end
buf B1 (O, I);
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
unisims/BIBUF.v 0 → 100644
View file @ e61b4d60
// $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2012 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 14.1
// \ \ Description : Xilinx Simulation Library Component
// / / Bi-Directional IO
// /___/ /\ Filename : BIBUF.v
// \ \ / \ Timestamp :
// \___\/\___\
//
// Revision:
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BIBUF (PAD, IO);
inout PAD;
inout IO;
wire PAD_io;
wire IO_io;
assign #10 PAD_io = PAD;
assign #10 IO_io = IO;
assign (weak1, weak0) IO = PAD_io;
assign (weak1, weak0) PAD = IO_io;
endmodule
`endcelldefine
unisims/BITSLICE_CONTROL.v 0 → 100644
View file @ e61b4d60
This diff is collapsed.
unisims/BSCANE2.v 0 → 100644
View file @ e61b4d60
// $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Boundary Scan Logic Control Circuit for VIRTEX7
// /___/ /\ Filename : BSCANE2.v
// \ \ / \ Timestamp : Mon Feb 8 22:02:00 PST 2010
// \___\/\___\
//
// Revision:
// 02/08/10 - Initial version.
// 06/10/11 - CR 613789.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 11/13/13 - Update default value of JTAG_CHAIN to 1 (CR 759814).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BSCANE2 (
CAPTURE,
DRCK,
RESET,
RUNTEST,
SEL,
SHIFT,
TCK,
TDI,
TMS,
UPDATE,
TDO
);
parameter DISABLE_JTAG = "FALSE";
parameter integer JTAG_CHAIN = 1;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output CAPTURE;
output DRCK;
output RESET;
output RUNTEST;
output SEL;
output SHIFT;
output TCK;
output TDI;
output TMS;
output UPDATE;
input TDO;
reg SEL_zd;
pulldown (DRCK);
pulldown (RESET);
pulldown (SEL);
pulldown (SHIFT);
pulldown (TDI);
pulldown (UPDATE);
//--####################################################################
//--##### Initialization ###
//--####################################################################
initial begin
//-------- JTAG_CHAIN
if ((JTAG_CHAIN != 1) && (JTAG_CHAIN != 2) && (JTAG_CHAIN != 3) && (JTAG_CHAIN != 4)) begin
$display("Attribute Syntax Error : The attribute JTAG_CHAIN on BSCANE2 instance %m is set to %d. Legal values for this attribute are 1, 2, 3 or 4.", JTAG_CHAIN);
$finish;
end
end
//--####################################################################
//--##### Jtag_select ###
//--####################################################################
always@(glbl.JTAG_SEL1_GLBL or glbl.JTAG_SEL2_GLBL or glbl.JTAG_SEL3_GLBL or glbl.JTAG_SEL4_GLBL) begin
if (JTAG_CHAIN == 1) SEL_zd = glbl.JTAG_SEL1_GLBL;
else if (JTAG_CHAIN == 2) SEL_zd = glbl.JTAG_SEL2_GLBL;
else if (JTAG_CHAIN == 3) SEL_zd = glbl.JTAG_SEL3_GLBL;
else if (JTAG_CHAIN == 4) SEL_zd = glbl.JTAG_SEL4_GLBL;
end
//--####################################################################
//--####################################################################
//--##### USER_TDO ###
//--####################################################################
always@(TDO) begin
if (JTAG_CHAIN == 1) glbl.JTAG_USER_TDO1_GLBL = TDO;
else if (JTAG_CHAIN == 2) glbl.JTAG_USER_TDO2_GLBL = TDO;
else if (JTAG_CHAIN == 3) glbl.JTAG_USER_TDO3_GLBL = TDO;
else if (JTAG_CHAIN == 4) glbl.JTAG_USER_TDO4_GLBL = TDO;
end
//--####################################################################
//--##### Output ###
//--####################################################################
assign CAPTURE = glbl.JTAG_CAPTURE_GLBL;
assign #5 DRCK = ((SEL_zd & !glbl.JTAG_SHIFT_GLBL & !glbl.JTAG_CAPTURE_GLBL)
||
(SEL_zd & glbl.JTAG_SHIFT_GLBL & glbl.JTAG_TCK_GLBL)
||
(SEL_zd & glbl.JTAG_CAPTURE_GLBL & glbl.JTAG_TCK_GLBL));
assign RESET = glbl.JTAG_RESET_GLBL;
assign RUNTEST = glbl.JTAG_RUNTEST_GLBL;
assign SEL = SEL_zd;
assign SHIFT = glbl.JTAG_SHIFT_GLBL;
assign TDI = glbl.JTAG_TDI_GLBL;
assign TCK = glbl.JTAG_TCK_GLBL;
assign TMS = glbl.JTAG_TMS_GLBL;
assign UPDATE = glbl.JTAG_UPDATE_GLBL;
specify
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
unisims/BUF.v 0 → 100644
View file @ e61b4d60
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUF.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / General Purpose Buffer
// /___/ /\ Filename : BUF.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:13 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BUF (O, I);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input I;
buf B1 (O, I);
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
unisims/BUFCE_LEAF.v 0 → 100644
View file @ e61b4d60
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Clock Buffer
// /___/ /\ Filename : BUFCE_LEAF.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 05/15/12 - Initial version.
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFCE_LEAF #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter CE_TYPE = "SYNC",
parameter [0:0] IS_CE_INVERTED = 1'b0,
parameter [0:0] IS_I_INVERTED = 1'b0
)(
output O,
input CE,
input I
);
// define constants
localparam MODULE_NAME = "BUFCE_LEAF";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam CE_TYPE_ASYNC = 1;
localparam CE_TYPE_SYNC = 0;
`ifndef XIL_DR
localparam CE_TYPE_REG = CE_TYPE;
localparam IS_CE_INVERTED_REG = IS_CE_INVERTED;
localparam IS_I_INVERTED_REG = IS_I_INVERTED;
`endif
wire CE_TYPE_BIN;
wire IS_CE_INVERTED_BIN;
wire IS_I_INVERTED_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "BUFCE_LEAF_dr.v"
`endif
wire O_out;
wire O_delay;
wire CE_in;
wire I_in;
wire CE_delay;
wire I_delay;
wire ce_inv, ice, CE_TYPE_INV;
reg enable_clk;
// input output assignments
assign #(out_delay) O = O_delay;
assign #(in_delay) CE_delay = CE;
assign #(in_delay) I_delay = I;
assign O_delay = O_out;
assign CE_in = IS_CE_INVERTED_BIN ? ~CE_delay : CE_delay;
assign I_in = IS_I_INVERTED_BIN ? ~I_delay : I_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
assign CE_TYPE_BIN =
(CE_TYPE_REG == "SYNC") ? CE_TYPE_SYNC :
(CE_TYPE_REG == "ASYNC") ? CE_TYPE_ASYNC :
CE_TYPE_SYNC;
assign IS_CE_INVERTED_BIN = IS_CE_INVERTED_REG;
assign IS_I_INVERTED_BIN = IS_I_INVERTED_REG;
always @ (trig_attr) begin
#1;
case (CE_TYPE_REG) // string
"SYNC" : /* */;
"ASYNC" : /* */;
default : begin
$display("Attribute Syntax Error : The attribute CE_TYPE on %s instance %m is set to %s. Legal values for this attribute are SYNC or ASYNC.", MODULE_NAME, CE_TYPE_REG);
attr_err = 1'b1;
end
endcase
if ((IS_CE_INVERTED_REG >= 1'b0) && (IS_CE_INVERTED_REG <= 1'b1)) // binary
/* */;
else begin
$display("Attribute Syntax Error : The attribute IS_CE_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CE_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_I_INVERTED_REG >= 1'b0) && (IS_I_INVERTED_REG <= 1'b1)) // binary
/* */;
else begin
$display("Attribute Syntax Error : The attribute IS_I_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_I_INVERTED_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign CE_TYPE_INV = ~CE_TYPE_BIN;
assign ce_inv = ~CE_in;
assign ice = ~(CE_TYPE_INV & I_in);
always @(ice or ce_inv or glblGSR) begin
if (glblGSR)
enable_clk <= 1'b1;
else if (ice)
enable_clk <= ~ce_inv;
end
assign O_out = enable_clk & I_in ;
specify
`ifdef XIL_TIMING // Simprim
$period (negedge I, 0:0:0, notifier);
$period (posedge I, 0:0:0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
unisims/BUFCE_ROW.v 0 → 100644
View file @ e61b4d60
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Clock Buffer
// /___/ /\ Filename : BUFCE_ROW.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 05/15/12 - Initial version.
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFCE_ROW #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter CE_TYPE = "SYNC",
parameter [0:0] IS_CE_INVERTED = 1'b0,
parameter [0:0] IS_I_INVERTED = 1'b0
)(
output O,
input CE,
input I
);
// define constants
localparam MODULE_NAME = "BUFCE_ROW";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam CE_TYPE_ASYNC = 1;
localparam CE_TYPE_SYNC = 0;
`ifndef XIL_DR
localparam CE_TYPE_REG = CE_TYPE;
localparam IS_CE_INVERTED_REG = IS_CE_INVERTED;
localparam IS_I_INVERTED_REG = IS_I_INVERTED;
`endif
wire CE_TYPE_BIN;
wire IS_CE_INVERTED_BIN;
wire IS_I_INVERTED_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "BUFCE_ROW_dr.v"
`endif
wire O_out;
wire O_delay;
wire CE_in;
wire I_in;
wire CE_delay;
wire I_delay;
wire ce_inv, ice, CE_TYPE_INV;
reg enable_clk;
// input output assignments
assign #(out_delay) O = O_delay;
assign #(in_delay) CE_delay = CE;
assign #(in_delay) I_delay = I;
assign O_delay = O_out;
assign CE_in = IS_CE_INVERTED_BIN ? ~CE_delay : CE_delay;
assign I_in = IS_I_INVERTED_BIN ? ~I_delay : I_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
assign CE_TYPE_BIN =
(CE_TYPE_REG == "SYNC") ? CE_TYPE_SYNC :
(CE_TYPE_REG == "ASYNC") ? CE_TYPE_ASYNC :
CE_TYPE_SYNC;
assign IS_CE_INVERTED_BIN = IS_CE_INVERTED_REG;
assign IS_I_INVERTED_BIN = IS_I_INVERTED_REG;
always @ (trig_attr) begin
#1;
case (CE_TYPE_REG) // string
"SYNC" : /* */;
"ASYNC" : /* */;
default : begin
$display("Attribute Syntax Error : The attribute CE_TYPE on %s instance %m is set to %s. Legal values for this attribute are SYNC or ASYNC.", MODULE_NAME, CE_TYPE_REG);
attr_err = 1'b1;
end
endcase
if ((IS_CE_INVERTED_REG >= 1'b0) && (IS_CE_INVERTED_REG <= 1'b1)) // binary
/* */;
else begin
$display("Attribute Syntax Error : The attribute IS_CE_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CE_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_I_INVERTED_REG >= 1'b0) && (IS_I_INVERTED_REG <= 1'b1)) // binary
/* */;
else begin
$display("Attribute Syntax Error : The attribute IS_I_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_I_INVERTED_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign CE_TYPE_INV = ~CE_TYPE_BIN;
assign ce_inv = ~CE_in;
assign ice = ~(CE_TYPE_INV & I_in);
always @(ice or ce_inv or glblGSR) begin
if (glblGSR)
enable_clk <= 1'b1;
else if (ice)
enable_clk <= ~ce_inv;
end
assign O_out = enable_clk & I_in ;
specify
(CE *> O) = (0:0:0, 0:0:0);
(I *> O) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, I_delay, CE_delay);
$setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier,,, I_delay, CE_delay);
$setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, I_delay, CE_delay);
$setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier,,, I_delay, CE_delay);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
unisims/BUFG.v 0 → 100644
View file @ e61b4d60
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFG.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Global Clock Buffer
// /___/ /\ Filename : BUFG.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BUFG (O, I);
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
reg notifier;
`endif
output O;
input I;
buf B1 (O, I);
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
$period (posedge I, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
unisims/BUFGCE.v 0 → 100644
View file @ e61b4d60
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Clock Buffer
// /___/ /\ Filename : BUFGCE.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 05/15/12 - Initial version.
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFGCE #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter CE_TYPE = "SYNC",
parameter [0:0] IS_CE_INVERTED = 1'b0,
parameter [0:0] IS_I_INVERTED = 1'b0
)(
output O,
input CE,
input I
);
// define constants
localparam MODULE_NAME = "BUFGCE";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam CE_TYPE_ASYNC = 1;
localparam CE_TYPE_SYNC = 0;
`ifndef XIL_DR
localparam CE_TYPE_REG = CE_TYPE;
localparam IS_CE_INVERTED_REG = IS_CE_INVERTED;
localparam IS_I_INVERTED_REG = IS_I_INVERTED;
`endif
wire CE_TYPE_BIN;
wire IS_CE_INVERTED_BIN;
wire IS_I_INVERTED_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "BUFGCE_dr.v"
`endif
wire O_out;
wire O_delay;
wire CE_in;
wire I_in;
wire CE_delay;
wire I_delay;
wire ce_inv, ice, CE_TYPE_INV;
reg enable_clk;
// input output assignments
assign #(out_delay) O = O_delay;
`ifndef XIL_TIMING // Unisim
assign #(in_delay) CE_delay = CE;
assign #(in_delay) I_delay = I;
`endif
assign O_delay = O_out;
assign CE_in = IS_CE_INVERTED_BIN ? ~CE_delay : CE_delay;
assign I_in = IS_I_INVERTED_BIN ? ~I_delay : I_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
assign CE_TYPE_BIN =
(CE_TYPE_REG == "SYNC") ? CE_TYPE_SYNC :
(CE_TYPE_REG == "ASYNC") ? CE_TYPE_ASYNC :
CE_TYPE_SYNC;
assign IS_CE_INVERTED_BIN = IS_CE_INVERTED_REG;
assign IS_I_INVERTED_BIN = IS_I_INVERTED_REG;
always @ (trig_attr) begin
#1;
case (CE_TYPE_REG) // string
"SYNC" : /* */;
"ASYNC" : /* */;
default : begin
$display("Attribute Syntax Error : The attribute CE_TYPE on %s instance %m is set to %s. Legal values for this attribute are SYNC or ASYNC.", MODULE_NAME, CE_TYPE_REG);
attr_err = 1'b1;
end
endcase
if ((IS_CE_INVERTED_REG >= 1'b0) && (IS_CE_INVERTED_REG <= 1'b1)) // binary
/* */;
else begin
$display("Attribute Syntax Error : The attribute IS_CE_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CE_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_I_INVERTED_REG >= 1'b0) && (IS_I_INVERTED_REG <= 1'b1)) // binary
/* */;
else begin
$display("Attribute Syntax Error : The attribute IS_I_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_I_INVERTED_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign CE_TYPE_INV = ~CE_TYPE_BIN;
assign ce_inv = ~CE_in;
assign ice = ~(CE_TYPE_INV & I_in);
always @(ice or ce_inv or glblGSR) begin
if (glblGSR)
enable_clk <= 1'b1;
else if (ice)
enable_clk <= ~ce_inv;
end
assign O_out = enable_clk & I_in ;
specify
(CE *> O) = (0:0:0, 0:0:0);
(I *> O) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$period (negedge I, 0:0:0, notifier);
$period (posedge I, 0:0:0, notifier);
$setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, I_delay, CE_delay);
$setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier,,, I_delay, CE_delay);
$setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, I_delay, CE_delay);
$setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier,,, I_delay, CE_delay);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
unisims/BUFGCE_DIV.v 0 → 100644
View file @ e61b4d60
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Clock Buffer with Divide
// /___/ /\ Filename : BUFGCE_DIV.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 04/30/12 - Initial version.
// 02/28/13 - 703678 - update BUFGCE_DIVIDE attribute type.
// 06/20/13 - 723918 - Add latch on CE to match HW
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFGCE_DIV #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter integer BUFGCE_DIVIDE = 1,
parameter [0:0] IS_CE_INVERTED = 1'b0,
parameter [0:0] IS_CLR_INVERTED = 1'b0,
parameter [0:0] IS_I_INVERTED = 1'b0
)(
output O,
input CE,
input CLR,
input I
);
// define constants
localparam MODULE_NAME = "BUFGCE_DIV";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
`ifndef XIL_DR
localparam BUFGCE_DIVIDE_REG = BUFGCE_DIVIDE;
localparam IS_CE_INVERTED_REG = IS_CE_INVERTED;
localparam IS_CLR_INVERTED_REG = IS_CLR_INVERTED;
localparam IS_I_INVERTED_REG = IS_I_INVERTED;
`endif
wire BUFGCE_DIVIDE_BIN;
wire IS_CE_INVERTED_BIN;
wire IS_CLR_INVERTED_BIN;
wire IS_I_INVERTED_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "BUFGCE_DIV_dr.v"
`endif
wire O_out;
wire O_delay;
wire CE_in;
wire CLR_in;
wire I_in;
wire CE_delay;
wire CLR_delay;
wire I_delay;
integer clk_count=1, first_toggle_count=1, second_toggle_count=1;
reg first_rise, first_half_period;
reg o_out_divide = 0;
wire i_ce, i_inv;
reg ce_en;
// input output assignments
assign #(out_delay) O = O_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) I_delay = I;
assign #(in_delay) CE_delay = CE;
assign #(in_delay) CLR_delay = CLR;
`endif // `ifndef XIL_TIMING
assign O_delay = O_out;
assign CE_in = CE_delay ^ IS_CE_INVERTED_BIN;
assign CLR_in = CLR_delay ^ IS_CLR_INVERTED_BIN;
assign I_in = I_delay ^ IS_I_INVERTED_BIN;
initial begin
#1;
trig_attr = ~trig_attr;
end
assign BUFGCE_DIVIDE_BIN = BUFGCE_DIVIDE_REG;
assign IS_CE_INVERTED_BIN = IS_CE_INVERTED_REG;
assign IS_CLR_INVERTED_BIN = IS_CLR_INVERTED_REG;
assign IS_I_INVERTED_BIN = IS_I_INVERTED_REG;
always @ (trig_attr) begin
#1;
if ((BUFGCE_DIVIDE_REG < 1) && (BUFGCE_DIVIDE_REG > 8)) // decimal
begin
$display("Attribute Syntax Error : The attribute BUFGCE_DIVIDE on %s instance %m is set to %d. Legal values for this attribute are 1 to 8.", MODULE_NAME, BUFGCE_DIVIDE_REG);
attr_err = 1'b1;
end
if ((IS_CE_INVERTED_REG != 1'b0) && (IS_CE_INVERTED_REG != 1'b1)) // binary
begin
$display("Attribute Syntax Error : The attribute IS_CE_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CE_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_CLR_INVERTED_REG != 1'b0) && (IS_CLR_INVERTED_REG != 1'b1)) // binary
begin
$display("Attribute Syntax Error : The attribute IS_CLR_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CLR_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_I_INVERTED_REG != 1'b0) && (IS_I_INVERTED_REG != 1'b1)) // binary
begin
$display("Attribute Syntax Error : The attribute IS_I_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_I_INVERTED_REG);
attr_err = 1'b1;
end
case (BUFGCE_DIVIDE_REG)
1 : begin
first_toggle_count = 1;
second_toggle_count = 1;
end
2 : begin
first_toggle_count = 2;
second_toggle_count = 2;
end
3 : begin
first_toggle_count = 2;
second_toggle_count = 4;
end
4 : begin
first_toggle_count = 4;
second_toggle_count = 4;
end
5 : begin
first_toggle_count = 4;
second_toggle_count = 6;
end
6 : begin
first_toggle_count = 6;
second_toggle_count = 6;
end
7 : begin
first_toggle_count = 6;
second_toggle_count = 8;
end
8 : begin
first_toggle_count = 8;
second_toggle_count = 8;
end
endcase // case(BUFGCE_DIV)
if (attr_err == 1'b1) $finish;
end
always begin
if (glblGSR == 1'b1) begin
assign o_out_divide = 1'b0;
assign clk_count = 0;
assign first_rise = 1'b1;
assign first_half_period = 1'b0;
end
else if (glblGSR == 1'b0) begin
deassign o_out_divide;
deassign clk_count;
deassign first_rise;
deassign first_half_period;
end
@(glblGSR);
end
assign i_inv = ~I_in;
always @(glblGSR, CLR_in, I_in, CE_in)
begin
if(glblGSR || CLR_in)
ce_en <= 1'b0;
else if (~I_in)
ce_en <= CE_in;
end
assign i_ce = I_in & ce_en;
always @(i_ce or posedge glblGSR or posedge CLR_in) begin
if (first_toggle_count == 1) begin
o_out_divide = i_ce;
end
else begin
if(CLR_in == 1'b1 || glblGSR == 1'b1) begin
o_out_divide = 1'b0;
clk_count = 1;
first_half_period = 1'b1;
first_rise = 1'b1;
end
else if(CLR_in == 1'b0 && glblGSR == 1'b0) begin
if (i_ce == 1'b1 && first_rise == 1'b1) begin
o_out_divide = 1'b1;
clk_count = 1;
first_half_period = 1'b1;
first_rise = 1'b0;
end
else if (clk_count == second_toggle_count && first_half_period == 1'b0) begin
o_out_divide = ~o_out_divide;
clk_count = 1;
first_half_period = 1'b1;
end
else if (clk_count == first_toggle_count && first_half_period == 1'b1) begin
o_out_divide = ~o_out_divide;
clk_count = 1;
first_half_period = 1'b0;
end
else if (first_rise == 1'b0) begin
clk_count = clk_count + 1;
end
end
end
end
// assign O_out = (period_toggle == 0) ? I_in : o_out_divide;
assign O_out = o_out_divide;
specify
( CLR *> O) = (0:0:0, 0:0:0);
( I *> O) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$period (negedge I, 0:0:0, notifier);
$period (posedge I, 0:0:0, notifier);
$recrem ( negedge CLR, negedge I, 0:0:0, 0:0:0, notifier,,, CLR_delay, I_delay);
$recrem ( negedge CLR, posedge I, 0:0:0, 0:0:0, notifier,,, CLR_delay, I_delay);
$recrem ( posedge CLR, negedge I, 0:0:0, 0:0:0, notifier,,, CLR_delay, I_delay);
$recrem ( posedge CLR, posedge I, 0:0:0, 0:0:0, notifier,,, CLR_delay, I_delay);
$setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, I_delay, CE_delay);
$setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier,,, I_delay, CE_delay);
$setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, I_delay, CE_delay);
$setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier,,, I_delay, CE_delay);
// not needed ?
$setuphold (negedge I, negedge CLR, 0:0:0, 0:0:0, notifier,,, I_delay, CLR_delay);
$setuphold (negedge I, posedge CLR, 0:0:0, 0:0:0, notifier,,, I_delay, CLR_delay);
$setuphold (posedge I, negedge CLR, 0:0:0, 0:0:0, notifier,,, I_delay, CLR_delay);
$setuphold (posedge I, posedge CLR, 0:0:0, 0:0:0, notifier,,, I_delay, CLR_delay);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
unisims/BUFGCTRL.v 0 → 100644
View file @ e61b4d60
This diff is collapsed.
unisims/BUFGP.v 0 → 100644
View file @ e61b4d60
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFGP.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Primary Global Buffer for Driving Clocks or Long Lines
// /___/ /\ Filename : BUFGP.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BUFGP (O, I);
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
`endif
output O;
input I;
buf B1 (O, I);
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
unisims/BUFG_GT.v 0 → 100644
View file @ e61b4d60
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Clock Buffer with Divide
// /___/ /\ Filename : BUFG_GT.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 03/20/13 - Initial version.
// 05/06/13 - 716311 - match with hardware
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFG_GT #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [0:0] IS_CLR_INVERTED = 1'b0
)(
output O,
input CE,
input CEMASK,
input CLR,
input CLRMASK,
input [2:0] DIV,
input I
);
// define constants
localparam MODULE_NAME = "BUFG_GT";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
`ifndef XIL_DR
localparam [0:0] IS_CLR_INVERTED_REG = IS_CLR_INVERTED;
`endif
wire IS_CLR_INVERTED_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "BUFG_GT_dr.v"
`endif
wire O_out;
wire O_delay;
wire CEMASK_in;
wire CE_in;
wire CLRMASK_in;
wire CLR_in;
wire I_in;
wire [2:0] DIV_in;
wire CEMASK_delay;
wire CE_delay;
wire CLRMASK_delay;
wire CLR_delay;
wire I_delay;
wire [2:0] DIV_delay;
integer clk_count=1, first_toggle_count=1, second_toggle_count=1;
reg first_rise, first_half_period;
reg O_out_gl = 0;
wire i_ce, i_inv, clr_inv;
wire ce_masked, clrmask_inv, clr_masked;
reg ce_en;
reg ce_sync1, ce_sync, clr_sync1, clr_sync;
assign #(out_delay) O = O_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) I_delay = I;
assign #(in_delay) CEMASK_delay = CEMASK;
assign #(in_delay) CE_delay = CE;
assign #(in_delay) CLRMASK_delay = CLRMASK;
assign #(in_delay) DIV_delay = DIV;
`endif // `ifndef XIL_TIMING
// inputs with no timing checks
assign #(in_delay) CLR_delay = CLR;
assign O_delay = O_out;
assign CEMASK_in = CEMASK_delay;
assign CE_in = CE_delay;
assign CLRMASK_in = CLRMASK_delay;
assign CLR_in = CLR_delay ^ IS_CLR_INVERTED_BIN;
assign DIV_in = DIV_delay;
assign I_in = I_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
assign IS_CLR_INVERTED_BIN = IS_CLR_INVERTED_REG;
always @ (trig_attr) begin
#1;
if ((IS_CLR_INVERTED_REG != 1'b0) && (IS_CLR_INVERTED_REG != 1'b1)) begin
$display("Attribute Syntax Error : The attribute IS_CLR_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CLR_INVERTED_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
always@(DIV_in)
begin
case (DIV_in)
3'b000 : begin
first_toggle_count = 1;
second_toggle_count = 1;
end
3'b001 : begin
first_toggle_count = 2;
second_toggle_count = 2;
end
3'b010 : begin
first_toggle_count = 2;
second_toggle_count = 4;
end
3'b011 : begin
first_toggle_count = 4;
second_toggle_count = 4;
end
3'b100 : begin
first_toggle_count = 4;
second_toggle_count = 6;
end
3'b101 : begin
first_toggle_count = 6;
second_toggle_count = 6;
end
3'b110 : begin
first_toggle_count = 6;
second_toggle_count = 8;
end
3'b111 : begin
first_toggle_count = 8;
second_toggle_count = 8;
end
endcase // case(BUFG_GT)
end //
always
begin
if (glblGSR == 1'b1) begin
assign O_out_gl = 1'b0;
assign clk_count = 0;
assign first_rise = 1'b1;
assign first_half_period = 1'b0;
end
else if (glblGSR == 1'b0) begin
deassign O_out_gl;
deassign clk_count;
deassign first_rise;
deassign first_half_period;
end
@(glblGSR);
end
always @(posedge I_in, negedge glblGSR)
begin
if (glblGSR == 1'b1)
begin
ce_sync1 <= 1'b0;
ce_sync <= 1'b0;
end
else
begin
ce_sync1 <= CE_in;
ce_sync <= ce_sync1;
end
end
assign clr_inv = ~CLR_in;
always @(posedge I_in, negedge clr_inv)
begin
if(~clr_inv)
begin
clr_sync1 <= 1'b0;
clr_sync <= 1'b0;
end
else
{clr_sync, clr_sync1} <= {clr_sync1, 1'b1};
end
assign clr_out = ~clr_sync;
assign i_inv = ~I_in;
assign clrmask_inv = ~CLRMASK_in;
assign ce_masked = ce_sync | CEMASK_in;
assign clr_masked = clr_out & clrmask_inv;
always @(i_inv, glblGSR, ce_masked, clr_masked)
begin
if (glblGSR || clr_masked)
ce_en <= 1'b0;
else if (i_inv)
ce_en <= ce_masked;
end
assign i_ce = I_in & ce_en;
always @(i_ce or posedge glblGSR or posedge clr_masked) begin
if (first_toggle_count == 1) begin
O_out_gl = i_ce;
end
else begin
if(clr_masked == 1'b1 || glblGSR == 1'b1) begin
O_out_gl = 1'b0;
clk_count = 1;
first_half_period = 1'b1;
first_rise = 1'b1;
end
else if(clr_masked == 1'b0 && glblGSR == 1'b0) begin
if (i_ce == 1'b1 && first_rise == 1'b1) begin
O_out_gl = 1'b1;
clk_count = 1;
first_half_period = 1'b1;
first_rise = 1'b0;
end
else if (clk_count == second_toggle_count && first_half_period == 1'b0) begin
O_out_gl = ~O_out_gl;
clk_count = 1;
first_half_period = 1'b1;
end
else if (clk_count == first_toggle_count && first_half_period == 1'b1) begin
O_out_gl = ~O_out_gl;
clk_count = 1;
first_half_period = 1'b0;
end
else if (first_rise == 1'b0) begin
clk_count = clk_count + 1;
end
end
end
end
assign #1 O_out = O_out_gl;
specify
( CLR *> O) = (0:0:0, 0:0:0);
( CLRMASK *> O) = (0:0:0, 0:0:0);
( I *> O) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING // Simprim
$recrem ( negedge CLRMASK, posedge I, 0:0:0, 0:0:0);
$setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, I_delay, CE_delay);
$setuphold (posedge I, negedge CEMASK, 0:0:0, 0:0:0, notifier,,, I_delay, CEMASK_delay);
$setuphold (posedge I, negedge CLRMASK, 0:0:0, 0:0:0, notifier,,, I_delay, CLRMASK_delay);
$setuphold (posedge I, negedge DIV, 0:0:0, 0:0:0, notifier,,, I_delay, DIV_delay);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
unisims/BUFH.v 0 → 100644
View file @ e61b4d60
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/blanc/BUFH.v,v 1.3 2008/11/11 21:41:06 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / H Clock Buffer
// /___/ /\ Filename : BUFH.v
// \ \ / \ Timestamp :
// \___\/\___\
//
// Revision:
// 04/08/08 - Initial version.
// 09//9/08 - Change to use BUFHCE according to yaml.
// 11/11/08 - Change to not use BUFHCE.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BUFH (O, I);
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
reg notifier;
`endif
output O;
input I;
buf B1 (O, I);
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
$period (posedge I, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
unisims/BUFHCE.v 0 → 100644
View file @ e61b4d60
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.i
// \ \ Description : Xilinx Timing Simulation Library Component
// / / H Clock Buffer with Active High Enable
// /___/ /\ Filename : BUFHCE.v
// \ \ / \ Timestamp : Wed Apr 22 17:10:55 PDT 2009
// \___\/\___\
//
// Revision:
// 04/08/08 - Initial version.
// 09/19/08 - Add GSR
// 10/19/08 - Recoding to same as BUFGCE according to hardware.
// 11/15/10 - Add CE_TYPE attribute (CR578114)
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 05/24/12 - 661573 - Remove 100 ps delay
// 10/12/12 - 681696 - fix preselect behavior.
// 10/30/12 - 684744 - match mapping with ISE.
// End Revision
`timescale 1 ps/1 ps
`celldefine
module BUFHCE #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter CE_TYPE = "SYNC",
parameter integer INIT_OUT = 0,
parameter [0:0] IS_CE_INVERTED = 1'b0
)(
output O,
input CE,
input I
);
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
wire del_I, delCE;
wire NCE, o_bufg_o, o_bufg1_o;
reg CE_TYPE_BINARY;
reg INIT_OUT_BINARY;
reg IS_CE_INVERTED_BIN = IS_CE_INVERTED;
initial begin
case (CE_TYPE)
"SYNC" : CE_TYPE_BINARY = 1'b0;
"ASYNC" : CE_TYPE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute CE_TYPE on BUFHCE instance %m is set to %s. Legal values for this attribute are SYNC, or ASYNC.", CE_TYPE);
$finish;
end
endcase
if ((INIT_OUT >= 0) && (INIT_OUT <= 1))
INIT_OUT_BINARY = INIT_OUT;
else begin
$display("Attribute Syntax Error : The Attribute INIT_OUT on BUFHCE instance %m is set to %d. Legal values for this attribute are 0 to 1.", INIT_OUT);
$finish;
end
end
BUFGCTRL bufgctrl0_inst (.O(o_bufg_o),
.CE0(~NCE),
.CE1(NCE),
.I0(del_I),
.I1(1'b0),
.IGNORE0(CE_TYPE_BINARY),
.IGNORE1(1'b0),
.S0(1'b1),
.S1(1'b1));
defparam bufgctrl0_inst.INIT_OUT = 1'b0;
defparam bufgctrl0_inst.PRESELECT_I0 = "TRUE";
defparam bufgctrl0_inst.PRESELECT_I1 = "FALSE";
INV I1 (.I(delCE ^ IS_CE_INVERTED_BIN),
.O(NCE));
BUFGCTRL bufgctrl1_inst (.O(o_bufg1_o),
.CE0(~NCE),
.CE1(NCE),
.I0(del_I),
.I1(1'b1),
.IGNORE0(CE_TYPE_BINARY),
.IGNORE1(1'b0),
.S0(1'b1),
.S1(1'b1));
defparam bufgctrl1_inst.INIT_OUT = 1'b0;
defparam bufgctrl1_inst.PRESELECT_I0 = "TRUE";
defparam bufgctrl1_inst.PRESELECT_I1 = "FALSE";
assign O = (INIT_OUT == 1) ? o_bufg1_o : o_bufg_o;
`ifndef XIL_TIMING
assign del_I = I;
assign delCE = CE;
`endif
specify
(I => O) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$period (posedge I, 0:0:0, notifier);
$setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, del_I, delCE);
$setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier,,, del_I, delCE);
$setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, del_I, delCE);
$setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier,,, del_I, delCE);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
unisims/BUFIO.v 0 → 100644
View file @ e61b4d60
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/virtex4/BUFIO.v,v 1.4 2007/06/01 22:41:59 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Local Clock Buffer for I/O
// /___/ /\ Filename : BUFIO.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:43 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/30/07 - change timescale to 1ps/1ps.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BUFIO (O, I);
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
reg notifier;
`endif
output O;
input I;
buf B1 (O, I);
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
$period (posedge I, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`timescale 1 ps / 1 ps
`endcelldefine
unisims/BUFMR.v 0 → 100644
View file @ e61b4d60
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/fuji/BUFMR.v,v 1.1 2009/12/21 21:08:16 yanx Exp $
///////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 12.1
// \ \ Description :
// / /
// /__/ /\ Filename : BUFMR.v
// \ \ / \
// \__\/\__ \
//
// Revision: 1.0
// 05/24/12 - 661573 - Remove 100 ps delay
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFMR (
O,
I
);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
reg notifier;
`endif
output O;
input I;
buf B1 (O, I);
specify
( I => O) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$period (posedge I, 0:0:0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
unisims/BUFMRCE.v 0 → 100644
View file @ e61b4d60
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/versclibs/data/fuji/BUFMRCE.v,v 1.1 2010/04/28 21:43:11 yanx Exp $
///////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 12.1
// \ \ Description :
// / /
// /__/ /\ Filename : BUFMRCE.v
// \ \ / \
// \__\/\__ \
//
// Revision: 1.0
// 05/24/12 - 661573 - Remove 100 ps delay
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFMRCE #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter CE_TYPE = "SYNC",
parameter integer INIT_OUT = 0,
parameter [0:0] IS_CE_INVERTED = 1'b0
)(
output O,
input CE,
input I
);
wire NCE, o_bufg_o, o_bufg1_o;
reg CE_TYPE_BINARY;
reg INIT_OUT_BINARY;
reg IS_CE_INVERTED_BIN = IS_CE_INVERTED;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
wire O_OUT;
wire delay_CE;
wire delay_I;
initial begin
case (CE_TYPE)
"SYNC" : CE_TYPE_BINARY = 1'b0;
"ASYNC" : CE_TYPE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute CE_TYPE on BUFMRCE instance %m is set to %s. Legal values for this attribute are SYNC, or ASYNC.", CE_TYPE);
$finish;
end
endcase
if ((INIT_OUT >= 0) && (INIT_OUT <= 1))
INIT_OUT_BINARY = INIT_OUT;
else begin
$display("Attribute Syntax Error : The Attribute INIT_OUT on BUFMRCE instance %m is set to %d. Legal values for this attribute are 0 to 1.", INIT_OUT);
$finish;
end
end
BUFGCTRL #(.INIT_OUT(1'b0), .PRESELECT_I0("TRUE"), .PRESELECT_I1("FALSE")) B1
(.O(o_bufg_o), .CE0(~NCE), .CE1(NCE), .I0(delay_I), .I1(1'b0), .IGNORE0(1'b0), .IGNORE1(1'b0), .S0(1'b1), .S1(1'b1));
INV I1 (.I(delay_CE ^ IS_CE_INVERTED_BIN), .O(NCE));
BUFGCTRL #(.INIT_OUT(1'b1), .PRESELECT_I0("TRUE"), .PRESELECT_I1("FALSE")) B2
(.O(o_bufg1_o), .CE0(~NCE), .CE1(NCE), .I0(delay_I), .I1(1'b1), .IGNORE0(1'b0), .IGNORE1(1'b0), .S0(1'b1), .S1(1'b1));
assign O = (INIT_OUT == 1) ? o_bufg1_o : o_bufg_o;
`ifndef XIL_TIMING
assign delay_I = I;
assign delay_CE = CE;
`endif
specify
( I => O) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$period (posedge I, 0:0:0, notifier);
$setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, delay_I, delay_CE);
$setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier,,, delay_I, delay_CE);
$setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, delay_I, delay_CE);
$setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier,,, delay_I, delay_CE);
`endif // `ifdef XIL_TIMING
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
unisims/BUFR.v 0 → 100644
View file @ e61b4d60
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/versclibs/data/fuji/BUFR.v,v 1.6 2011/08/09 22:45:10 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.i (O.72)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Regional Clock Buffer
// /___/ /\ Filename : BUFR.v
// \ \ / \ Timestamp : Thu Mar 11 16:44:06 PST 2005
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Added LOC parameter, removed GSR ports and initialized outpus.
// 04/04/2005 - Add SIM_DEVICE paramter to support rainier. CE pin has 4 clock
// latency for Virtex 4 and none for Rainier
// 07/25/05 - Updated names to Virtex5
// 08/31/05 - Add ce_en to sensitivity list of i_in which make ce asynch.
// 05/23/06 - Add count =0 and first_rise=1 when CE = 0 (CR232206).
// 07/19/06 - Add wire declaration for undeclared wire signals.
// 04/01/09 - CR 517236 -- Added VIRTEX6 support
// 11/13/09 - Added VIRTEX7
// 01/20/10 - Change VIRTEX7 to FUJI (CR545223)
// 02/23/10 - Use assign for o_out (CR543271)
// 06/09/10 - Change FUJI to 7_SERIES
// 08/18/10 - Change 7_SERIES to 7SERIES (CR571653)
// 08/09/11 - Add 7SERIES to ce_en logic (CR620544)
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 03/15/12 - Match with hardware (CR 650440)
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BUFR (O, CE, CLR, I);
output O;
input CE;
input CLR;
input I;
parameter BUFR_DIVIDE = "BYPASS";
parameter SIM_DEVICE = "VIRTEX4";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
integer count, period_toggle, half_period_toggle;
reg first_rise, half_period_done;
reg notifier;
reg o_out_divide = 0;
wire o_out;
reg ce_enable1, ce_enable2, ce_enable3, ce_enable4;
tri0 GSR = glbl.GSR;
wire i_in, ce_in, clr_in, gsr_in, ce_en, i_ce;
buf buf_i (i_in, I);
buf buf_ce (ce_in, CE);
buf buf_clr (clr_in, CLR);
buf buf_gsr (gsr_in, GSR);
buf buf_o (O, o_out);
initial begin
case (BUFR_DIVIDE)
"BYPASS" : period_toggle = 0;
"1" : begin
period_toggle = 1;
half_period_toggle = 1;
end
"2" : begin
period_toggle = 2;
half_period_toggle = 2;
end
"3" : begin
period_toggle = 4;
half_period_toggle = 2;
end
"4" : begin
period_toggle = 4;
half_period_toggle = 4;
end
"5" : begin
period_toggle = 6;
half_period_toggle = 4;
end
"6" : begin
period_toggle = 6;
half_period_toggle = 6;
end
"7" : begin
period_toggle = 8;
half_period_toggle = 6;
end
"8" : begin
period_toggle = 8;
half_period_toggle = 8;
end
default : begin
$display("Attribute Syntax Error : The attribute BUFR_DIVIDE on BUFR instance %m is set to %s. Legal values for this attribute are BYPASS, 1, 2, 3, 4, 5, 6, 7 or 8.", BUFR_DIVIDE);
$finish;
end
endcase // case(BUFR_DIVIDE)
case (SIM_DEVICE)
"VIRTEX4" : ;
"VIRTEX5" : ;
"VIRTEX6" : ;
"7SERIES" : ;
default : begin
$display("Attribute Syntax Error : The attribute SIM_DEVICE on BUFR instance %m is set to %s. Legal values for this attribute are VIRTEX4 or VIRTEX5 or VIRTEX6 or 7SERIES.", SIM_DEVICE);
$finish;
end
endcase
end // initial begin
always @(gsr_in or clr_in)
if (gsr_in == 1'b1 || clr_in == 1'b1) begin
assign o_out_divide = 1'b0;
assign count = 0;
assign first_rise = 1'b1;
assign half_period_done = 1'b0;
if (gsr_in == 1'b1) begin
assign ce_enable1 = 1'b0;
assign ce_enable2 = 1'b0;
assign ce_enable3 = 1'b0;
assign ce_enable4 = 1'b0;
end
end
else if (gsr_in == 1'b0 || clr_in == 1'b0) begin
deassign o_out_divide;
deassign count;
deassign first_rise;
deassign half_period_done;
if (gsr_in == 1'b0) begin
deassign ce_enable1;
deassign ce_enable2;
deassign ce_enable3;
deassign ce_enable4;
end
end
always @(negedge i_in)
begin
ce_enable1 <= ce_in;
ce_enable2 <= ce_enable1;
ce_enable3 <= ce_enable2;
ce_enable4 <= ce_enable3;
end
assign ce_en = ((SIM_DEVICE == "VIRTEX5") || (SIM_DEVICE == "VIRTEX6") || (SIM_DEVICE == "7SERIES")) ? ce_in : ce_enable4;
assign i_ce = i_in & ce_en;
generate
case (SIM_DEVICE)
"VIRTEX4" : begin
always @(i_in or ce_en)
if (ce_en == 1'b1) begin
if (i_in == 1'b1 && first_rise == 1'b1) begin
o_out_divide = 1'b1;
first_rise = 1'b0;
end
else if (count == half_period_toggle && half_period_done == 1'b0) begin
o_out_divide = ~o_out_divide;
half_period_done = 1'b1;
count = 0;
end
else if (count == period_toggle && half_period_done == 1'b1) begin
o_out_divide = ~o_out_divide;
half_period_done = 1'b0;
count = 0;
end
if (first_rise == 1'b0)
count = count + 1;
end // if (ce_in == 1'b1)
else begin
count = 0;
first_rise = 1;
end
end
"VIRTEX5","VIRTEX6","7SERIES" : begin
always @(i_ce)
begin
if (i_ce == 1'b1 && first_rise == 1'b1) begin
o_out_divide = 1'b1;
first_rise = 1'b0;
end
else if (count == half_period_toggle && half_period_done == 1'b0) begin
o_out_divide = ~o_out_divide;
half_period_done = 1'b1;
count = 0;
end
else if (count == period_toggle && half_period_done == 1'b1) begin
o_out_divide = ~o_out_divide;
half_period_done = 1'b0;
count = 0;
end
if (first_rise == 1'b0) begin
count = count + 1;
end // if (ce_in == 1'b1)
end
end
endcase
endgenerate
assign o_out = (period_toggle == 0) ? i_in : o_out_divide;
//*** Timing Checks Start here
always @(notifier) begin
o_out_divide <= 1'bx;
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(CLR => O) = (0:0:0, 0:0:0);
$setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier);
$setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier);
$period (posedge I, 0:0:0, notifier);
$width (posedge CLR, 0:0:0, 0, notifier);
$width (posedge I, 0:0:0, 0, notifier);
$width (negedge I, 0:0:0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule // BUFR
`endcelldefine
unisims/CAPTUREE2.v 0 → 100644
View file @ e61b4d60
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/versclibs/data/fuji/CAPTUREE2.v,v 1.1 2010/05/27 18:53:42 yanx Exp $
///////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 12.1
// \ \ Description :
// / /
// /__/ /\ Filename : CAPTUREE2.v
// \ \ / \
// \__\/\__ \
//
// Generated by : /home/chen/xfoundry/HEAD/env/Databases/CAEInterfaces/LibraryWriters/bin/ltw.pl
// Revision: 1.0
// 05/09/12 - removed GSR reference (CR 659430).
// End Revision
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module CAPTUREE2 (
CAP,
CLK
);
parameter ONESHOT = "TRUE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
input CAP;
input CLK;
reg [0:0] ONESHOT_BINARY;
reg notifier;
wire CAP_IN;
wire CLK_IN;
wire CAP_INDELAY;
wire CLK_INDELAY;
initial begin
case (ONESHOT)
"TRUE" : ONESHOT_BINARY = 1'b1;
"FALSE" : ONESHOT_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute ONESHOT on CAPTUREE2 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", ONESHOT);
$finish;
end
endcase
end
buf B_CAP (CAP_IN, CAP);
buf B_CLK (CLK_IN, CLK);
specify
`ifdef XIL_TIMING
$period (posedge CLK, 0:0:0, notifier);
$setuphold (posedge CLK, negedge CAP, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_CAP);
$setuphold (posedge CLK, posedge CAP, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_CAP);
`endif // `ifdef XIL_TIMING
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
unisims/CARRY4.v 0 → 100644
View file @ e61b4d60
// $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1i (K.17)
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Fast Carry Logic with Look Ahead
// /___/ /\ Filename : CARRY4.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 04/11/05 - Initial version.
// 05/06/05 - Unused CYINT or CI pin need grounded instead of open (CR207752)
// 05/31/05 - Change pin order, remove connection check for CYINIT and CI.
// 12/21/05 - Add timing path.
// 04/13/06 - Add full timing path for DI to O (CR228786)
// 06/04/07 - Add wire definition.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/13/12 - CR655410 - add pulldown, CI, CYINIT, sync uni/sim/unp
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module CARRY4 (CO, O, CI, CYINIT, DI, S);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output [3:0] CO;
output [3:0] O;
input CI;
input CYINIT;
input [3:0] DI;
input [3:0] S;
wire [3:0] di_in, s_in, o_out, co_out;
wire ci_or_cyinit;
wire ci_in, cyinit_in;
pulldown P1 (CI);
pulldown P2 (CYINIT);
assign ci_in = CI;
assign cyinit_in = CYINIT;
assign di_in = DI;
assign s_in = S;
assign O = o_out;
assign CO = co_out;
assign o_out = s_in ^ {co_out[2:0], ci_or_cyinit};
assign co_out[0] = s_in[0] ? ci_or_cyinit : di_in[0];
assign co_out[1] = s_in[1] ? co_out[0] : di_in[1];
assign co_out[2] = s_in[2] ? co_out[1] : di_in[2];
assign co_out[3] = s_in[3] ? co_out[2] : di_in[3];
assign ci_or_cyinit = ci_in | cyinit_in;
`ifdef XIL_TIMING
specify
(CI => O[0]) = (0:0:0, 0:0:0);
(CI => O[1]) = (0:0:0, 0:0:0);
(CI => O[2]) = (0:0:0, 0:0:0);
(CI => O[3]) = (0:0:0, 0:0:0);
(CI => CO[0]) = (0:0:0, 0:0:0);
(CI => CO[1]) = (0:0:0, 0:0:0);
(CI => CO[2]) = (0:0:0, 0:0:0);
(CI => CO[3]) = (0:0:0, 0:0:0);
(CYINIT => O[0]) = (0:0:0, 0:0:0);
(CYINIT => O[1]) = (0:0:0, 0:0:0);
(CYINIT => O[2]) = (0:0:0, 0:0:0);
(CYINIT => O[3]) = (0:0:0, 0:0:0);
(CYINIT => CO[0]) = (0:0:0, 0:0:0);
(CYINIT => CO[1]) = (0:0:0, 0:0:0);
(CYINIT => CO[2]) = (0:0:0, 0:0:0);
(CYINIT => CO[3]) = (0:0:0, 0:0:0);
(S[0] => O[0]) = (0:0:0, 0:0:0);
(S[0] => O[1]) = (0:0:0, 0:0:0);
(S[0] => O[2]) = (0:0:0, 0:0:0);
(S[0] => O[3]) = (0:0:0, 0:0:0);
(S[1] => O[0]) = (0:0:0, 0:0:0);
(S[1] => O[1]) = (0:0:0, 0:0:0);
(S[1] => O[2]) = (0:0:0, 0:0:0);
(S[1] => O[3]) = (0:0:0, 0:0:0);
(S[2] => O[0]) = (0:0:0, 0:0:0);
(S[2] => O[1]) = (0:0:0, 0:0:0);
(S[2] => O[2]) = (0:0:0, 0:0:0);
(S[2] => O[3]) = (0:0:0, 0:0:0);
(S[3] => O[0]) = (0:0:0, 0:0:0);
(S[3] => O[1]) = (0:0:0, 0:0:0);
(S[3] => O[2]) = (0:0:0, 0:0:0);
(S[3] => O[3]) = (0:0:0, 0:0:0);
(S[0] => CO[0]) = (0:0:0, 0:0:0);
(S[0] => CO[1]) = (0:0:0, 0:0:0);
(S[0] => CO[2]) = (0:0:0, 0:0:0);
(S[0] => CO[3]) = (0:0:0, 0:0:0);
(S[1] => CO[0]) = (0:0:0, 0:0:0);
(S[1] => CO[1]) = (0:0:0, 0:0:0);
(S[1] => CO[2]) = (0:0:0, 0:0:0);
(S[1] => CO[3]) = (0:0:0, 0:0:0);
(S[2] => CO[0]) = (0:0:0, 0:0:0);
(S[2] => CO[1]) = (0:0:0, 0:0:0);
(S[2] => CO[2]) = (0:0:0, 0:0:0);
(S[2] => CO[3]) = (0:0:0, 0:0:0);
(S[3] => CO[0]) = (0:0:0, 0:0:0);
(S[3] => CO[1]) = (0:0:0, 0:0:0);
(S[3] => CO[2]) = (0:0:0, 0:0:0);
(S[3] => CO[3]) = (0:0:0, 0:0:0);
(DI[0] => CO[0]) = (0:0:0, 0:0:0);
(DI[0] => CO[1]) = (0:0:0, 0:0:0);
(DI[0] => CO[2]) = (0:0:0, 0:0:0);
(DI[0] => CO[3]) = (0:0:0, 0:0:0);
(DI[1] => CO[0]) = (0:0:0, 0:0:0);
(DI[1] => CO[1]) = (0:0:0, 0:0:0);
(DI[1] => CO[2]) = (0:0:0, 0:0:0);
(DI[1] => CO[3]) = (0:0:0, 0:0:0);
(DI[2] => CO[0]) = (0:0:0, 0:0:0);
(DI[2] => CO[1]) = (0:0:0, 0:0:0);
(DI[2] => CO[2]) = (0:0:0, 0:0:0);
(DI[2] => CO[3]) = (0:0:0, 0:0:0);
(DI[3] => CO[0]) = (0:0:0, 0:0:0);
(DI[3] => CO[1]) = (0:0:0, 0:0:0);
(DI[3] => CO[2]) = (0:0:0, 0:0:0);
(DI[3] => CO[3]) = (0:0:0, 0:0:0);
(DI[0] => O[0]) = (0:0:0, 0:0:0);
(DI[0] => O[1]) = (0:0:0, 0:0:0);
(DI[0] => O[2]) = (0:0:0, 0:0:0);
(DI[0] => O[3]) = (0:0:0, 0:0:0);
(DI[1] => O[0]) = (0:0:0, 0:0:0);
(DI[1] => O[1]) = (0:0:0, 0:0:0);
(DI[1] => O[2]) = (0:0:0, 0:0:0);
(DI[1] => O[3]) = (0:0:0, 0:0:0);
(DI[2] => O[0]) = (0:0:0, 0:0:0);
(DI[2] => O[1]) = (0:0:0, 0:0:0);
(DI[2] => O[2]) = (0:0:0, 0:0:0);
(DI[2] => O[3]) = (0:0:0, 0:0:0);
(DI[3] => O[0]) = (0:0:0, 0:0:0);
(DI[3] => O[1]) = (0:0:0, 0:0:0);
(DI[3] => O[2]) = (0:0:0, 0:0:0);
(DI[3] => O[3]) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
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unisims/CFGLUT5.v 0 → 100644
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///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / 5-input Dynamically Reconfigurable Look-Up-Table with Carry and Clock Enable
// /___/ /\ Filename : CFGLUT5.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:40 PST 2004
// \___\/\___\
//
// Revision:
// 12/27/05 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 05/13/13 - add IS_CLK_INVERTED
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module CFGLUT5 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [31:0] INIT = 32'h00000000,
parameter [0:0] IS_CLK_INVERTED = 1'b0
)(
output CDO,
output O5,
output O6,
input I4,
input I3,
input I2,
input I1,
input I0,
input CDI,
input CE,
input CLK
);
reg [31:0] data;
wire [4:0] addr;
wire CDI_dly, CE_dly, CLK_dly;
wire CDI_in, CE_in, CLK_in;
wire clk_is_inverted;
reg notifier;
reg first_time = 1'b1;
initial
begin
assign data = INIT;
first_time <= #100000 1'b0;
while ((CLK_in !== 1'b0) && (first_time == 1'b1)) #1000;
deassign data;
end
assign addr = {I4, I3, I2, I1, I0};
always @(posedge CLK_in)
if (CE_in == 1'b1)
data <= #100 {data[30:0], CDI_in};
assign O6 = data[addr[4:0]];
assign O5 = data[addr[3:0]];
assign CDO = data[31];
`ifndef XIL_TIMING
assign CDI_dly = CDI;
assign CLK_dly = CLK;
assign CE_dly = CE;
`endif
assign clk_is_inverted = IS_CLK_INVERTED;
assign CLK_in = clk_is_inverted ^ CLK_dly;
assign CDI_in = CDI_dly;
assign CE_in = CE_dly;
`ifdef XIL_TIMING
specify
(I0 => O5) = (0:0:0, 0:0:0);
(I1 => O5) = (0:0:0, 0:0:0);
(I2 => O5) = (0:0:0, 0:0:0);
(I3 => O5) = (0:0:0, 0:0:0);
(I0 => O6) = (0:0:0, 0:0:0);
(I1 => O6) = (0:0:0, 0:0:0);
(I2 => O6) = (0:0:0, 0:0:0);
(I3 => O6) = (0:0:0, 0:0:0);
(I4 => O6) = (0:0:0, 0:0:0);
(I0 => CDO) = (0:0:0, 0:0:0);
(I1 => CDO) = (0:0:0, 0:0:0);
(I2 => CDO) = (0:0:0, 0:0:0);
(I3 => CDO) = (0:0:0, 0:0:0);
(I4 => CDO) = (0:0:0, 0:0:0);
$setuphold (posedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$setuphold (posedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$setuphold (posedge CLK, posedge CDI, 0:0:0, 0:0:0, notifier,,,CLK_dly,CDI_dly);
$setuphold (posedge CLK, negedge CDI, 0:0:0, 0:0:0, notifier,,,CLK_dly,CDI_dly);
$period (posedge CLK, 0:0:0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
$width (negedge CLK, 0:0:0, 0, notifier);
$setuphold (negedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$setuphold (negedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$setuphold (negedge CLK, posedge CDI, 0:0:0, 0:0:0, notifier,,,CLK_dly,CDI_dly);
$setuphold (negedge CLK, negedge CDI, 0:0:0, 0:0:0, notifier,,,CLK_dly,CDI_dly);
$period (negedge CLK, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
unisims/CMAC.v 0 → 100644
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unisims/DCIRESET.v 0 → 100644
View file @ e61b4d60
// $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Reset for DCI State Machine
// /___/ /\ Filename : DCIRESET.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:43 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module DCIRESET (LOCKED, RST);
output LOCKED;
input RST;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
time sample_rising, sample_falling;
always @(RST)
begin
if (RST)
sample_rising = $time;
else if (!RST)
sample_falling = $time;
if (sample_falling - sample_rising < 100000)
$display ("Timing Violation Error : The high pulse of RST signal at time %.3f ns in DCIRESET has to be greater than 100 ns", $time/1000.0);
if (sample_rising - sample_falling < 100000)
$display ("Timing Violation Error : The low pulse of RST signal at time %.3f ns in DCIRESET has to be greater than 100 ns", $time/1000.0);
end // always @ (RST)
assign #(100000, 0) LOCKED = RST ? 1'b0 : 1'b1;
`ifdef XIL_TIMING
specify
(RST => LOCKED) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
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unisims/DCM_SP.v 0 → 100644
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unisims/DIFFINBUF.v 0 → 100644
View file @ e61b4d60
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : DIFFINBUF.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module DIFFINBUF #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter DQS_BIAS = "FALSE",
parameter IBUF_LOW_PWR = "TRUE",
parameter ISTANDARD = "UNUSED",
parameter integer SIM_INPUT_BUFFER_OFFSET = 0
)(
output O,
output O_B,
input DIFF_IN_N,
input DIFF_IN_P,
input [3:0] OSC,
input [1:0] OSC_EN,
input VREF
);
// define constants
localparam MODULE_NAME = "DIFFINBUF";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam DQS_BIAS_FALSE = 0;
localparam DQS_BIAS_TRUE = 1;
localparam IBUF_LOW_PWR_FALSE = 1;
localparam IBUF_LOW_PWR_TRUE = 0;
localparam ISTANDARD_UNUSED = 0;
// `ifndef XIL_DR
localparam [40:1] DQS_BIAS_REG = DQS_BIAS;
localparam [40:1] IBUF_LOW_PWR_REG = IBUF_LOW_PWR;
localparam [56:1] ISTANDARD_REG = ISTANDARD;
localparam integer SIM_INPUT_BUFFER_OFFSET_REG = SIM_INPUT_BUFFER_OFFSET;
// `endif
wire DQS_BIAS_BIN;
wire IBUF_LOW_PWR_BIN;
wire ISTANDARD_BIN;
wire [5:0] SIM_INPUT_BUFFER_OFFSET_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
// `ifdef XIL_DR
// `include "DIFFINBUF_dr.v"
// `endif
reg O_B_out;
reg O_out;
reg O_OSC_in;
reg O_B_OSC_in;
wire O_B_delay;
wire O_delay;
wire DIFF_IN_N_in;
wire DIFF_IN_P_in;
wire VREF_in;
wire [1:0] OSC_EN_in;
wire [3:0] OSC_in;
wire DIFF_IN_N_delay;
wire DIFF_IN_P_delay;
wire VREF_delay;
wire [1:0] OSC_EN_delay;
wire [3:0] OSC_delay;
// input output assignments
assign #(out_delay) O = O_delay;
assign #(out_delay) O_B = O_B_delay;
// inputs with no timing checks
assign #(in_delay) DIFF_IN_N_delay = DIFF_IN_N;
assign #(in_delay) DIFF_IN_P_delay = DIFF_IN_P;
assign #(in_delay) OSC_EN_delay = OSC_EN;
assign #(in_delay) OSC_delay = OSC;
assign #(in_delay) VREF_delay = VREF;
assign O_B_delay = (OSC_EN_in === 2'b11) ? O_B_OSC_in : (OSC_EN_in === 2'b10 || OSC_EN_in === 2'b01) ? 1'bx : O_B_out;
assign O_delay = (OSC_EN_in === 2'b11) ? O_OSC_in : (OSC_EN_in === 2'b10 || OSC_EN_in === 2'b01) ? 1'bx : O_out;
assign DIFF_IN_N_in = DIFF_IN_N_delay;
assign DIFF_IN_P_in = DIFF_IN_P_delay;
assign OSC_EN_in = OSC_EN_delay;
assign OSC_in = OSC_delay;
assign VREF_in = VREF_delay;
integer OSC_int = 0;
always @ (OSC_in or OSC_EN_in) begin
OSC_int = OSC_in[2:0] * 5;
if (OSC_in[3] == 1'b0 )
OSC_int = -1*OSC_int;
if(OSC_EN_in === 2'b11) begin
if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) < 0) begin
O_OSC_in <= 1'b0;
O_B_OSC_in <= 1'b1;
end
else if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) > 0) begin
O_OSC_in <= 1'b1;
O_B_OSC_in <= 1'b0;
end
else if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) == 0) begin
O_OSC_in <= ~O_OSC_in;
O_B_OSC_in <= ~O_B_OSC_in;
end
end
end
initial begin
if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) < 0) begin
O_OSC_in <= 1'b0;
O_B_OSC_in <= 1'b1;
end
else if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) > 0) begin
O_OSC_in <= 1'b1;
O_B_OSC_in <= 1'b0;
end
else if ((SIM_INPUT_BUFFER_OFFSET_REG + OSC_int) == 0) begin
O_OSC_in <= 1'bx;
O_B_OSC_in <= 1'bx;
end
end
initial begin
`ifndef XIL_TIMING
$display("ERROR: SIMPRIM primitive %s instance %m is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the SIMPRIM library.", MODULE_NAME);
$finish;
`endif
#1;
trig_attr = ~trig_attr;
end
assign DQS_BIAS_BIN =
(DQS_BIAS_REG == "FALSE") ? DQS_BIAS_FALSE :
(DQS_BIAS_REG == "TRUE") ? DQS_BIAS_TRUE :
DQS_BIAS_FALSE;
assign IBUF_LOW_PWR_BIN =
(IBUF_LOW_PWR_REG == "TRUE") ? IBUF_LOW_PWR_TRUE :
(IBUF_LOW_PWR_REG == "FALSE") ? IBUF_LOW_PWR_FALSE :
IBUF_LOW_PWR_TRUE;
assign ISTANDARD_BIN =
(ISTANDARD_REG == "UNUSED") ? ISTANDARD_UNUSED :
ISTANDARD_UNUSED;
assign SIM_INPUT_BUFFER_OFFSET_BIN = SIM_INPUT_BUFFER_OFFSET_REG;
always @ (trig_attr) begin
#1;
if ((DQS_BIAS_REG != "FALSE") &&
(DQS_BIAS_REG != "TRUE")) begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, DQS_BIAS_REG);
attr_err = 1'b1;
end
if (IBUF_LOW_PWR_REG != "TRUE" && IBUF_LOW_PWR_REG != "FALSE") begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR_REG);
attr_err = 1'b1;
end
if ((ISTANDARD_REG != "UNUSED") && (ISTANDARD_REG != "DEFAULT")) begin
$display("Attribute Syntax Error : The attribute ISTANDARD on %s instance %m is set to %s. Legal values for this attribute are UNUSED.", MODULE_NAME, ISTANDARD_REG);
attr_err = 1'b1;
end
if ((SIM_INPUT_BUFFER_OFFSET_REG < -50) || (SIM_INPUT_BUFFER_OFFSET_REG > 50)) begin
$display("Attribute Syntax Error : The attribute SIM_INPUT_BUFFER_OFFSET on %s instance %m is set to %d. Legal values for this attribute are -50 to 50.", MODULE_NAME, SIM_INPUT_BUFFER_OFFSET_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
always @(DIFF_IN_P_in or DIFF_IN_N_in) begin
// if(IOB_TYPE_REG == "MASTER")
O_out <= DIFF_IN_P_in;
// else
O_B_out <= DIFF_IN_N_in;
end
specify
(DIFF_IN_N => O) = (0:0:0, 0:0:0);
(DIFF_IN_N => O_B) = (0:0:0, 0:0:0);
(DIFF_IN_P => O) = (0:0:0, 0:0:0);
(DIFF_IN_P => O_B) = (0:0:0, 0:0:0);
(OSC_EN *> O) = (0:0:0, 0:0:0);
(OSC_EN *> O_B) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
unisims/DNA_PORT.v 0 → 100644
View file @ e61b4d60
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 8.1i
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Device DNA Data Access Port
// /___/ /\ Filename : DNA_PORT.v
// \ \ / \ Timestamp : Mon Oct 10 14:55:34 PDT 2005
// \___\/\___\
//
// Revision:
// 10/10/05 - Initial version.
// 05/29/07 - Added wire declaration for internal signals
// 04/07/08 - CR 469973 -- Header Description fix
// 06/04/08 - CR 472697 -- added check for SIM_DNA_VALUE[56:55]
// 09/18/08 - CR 488646 -- added period check for simprim
// 10/28/08 - IR 494079 -- Shifting of dna_value is corrected to MSB first out
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 07/27/12 - Removed DRC warning for SIM_DNA_VALUE (CR 669726).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module DNA_PORT (DOUT, CLK, DIN, READ, SHIFT);
parameter [56:0] SIM_DNA_VALUE = 57'h0;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output DOUT;
input CLK, DIN, READ, SHIFT;
tri0 GSR = glbl.GSR;
localparam MAX_DNA_BITS = 57;
localparam MSB_DNA_BITS = MAX_DNA_BITS - 1;
reg [MSB_DNA_BITS:0] dna_val = SIM_DNA_VALUE;
reg dout_out;
reg notifier;
wire clk_in, din_in, gsr_in, read_in, shift_in;
buf b_dout (DOUT, dout_out);
buf b_clk (clk_in, CLK);
buf b_din (din_in, DIN);
buf buf_gsr (gsr_in, GSR);
buf b_read (read_in, READ);
buf b_shift (shift_in, SHIFT);
// GSR has no effect
always @(posedge clk_in) begin
if(read_in == 1'b1) begin
dna_val = SIM_DNA_VALUE;
dout_out = 1'b1;
end // read_in == 1'b1
else if(read_in == 1'b0)
if(shift_in == 1'b1) begin
// IR 494079
// dna_val = {din_in, dna_val[MSB_DNA_BITS :1]};
dna_val = {dna_val[MSB_DNA_BITS-1 : 0], din_in};
dout_out = dna_val[MSB_DNA_BITS];
end // shift_in == 1'b1
end // always @ (posedge clk_in)
specify
(CLK => DOUT) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (posedge CLK, 0:0:0, notifier);
$setuphold (posedge CLK, posedge DIN, 0:0:0, 0:0:0, notifier);
$setuphold (posedge CLK, negedge DIN, 0:0:0, 0:0:0, notifier);
$setuphold (posedge CLK, posedge READ, 0:0:0, 0:0:0, notifier);
$setuphold (posedge CLK, negedge READ, 0:0:0, 0:0:0, notifier);
$setuphold (posedge CLK, posedge SHIFT, 0:0:0, 0:0:0, notifier);
$setuphold (posedge CLK, negedge SHIFT, 0:0:0, 0:0:0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule // DNA_PORT
`endcelldefine
unisims/DNA_PORTE2.v 0 → 100644
View file @ e61b4d60
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2013.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : DNA_PORTE2.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 06/07/13 - Initial version.
// 08/27/13 - Added timing support.
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
//`celldefine
module DNA_PORTE2 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [95:0] SIM_DNA_VALUE = 96'h000000000000000000000000
)(
output DOUT,
input CLK,
input DIN,
input READ,
input SHIFT
);
reg [95:0] SIM_DNA_VALUE_reg = SIM_DNA_VALUE;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "DNA_PORTE2_dr.v"
`endif
tri0 GSR = glbl.GSR;
localparam MAX_DNA_BITS = 96;
localparam MSB_DNA_BITS = MAX_DNA_BITS - 1;
reg [MSB_DNA_BITS:0] dna_val = SIM_DNA_VALUE;
reg dout_out;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
wire clk_in;
wire din_in;
wire read_in;
wire shift_in;
wire clk_delay;
wire din_delay;
wire read_delay;
wire shift_delay;
assign DOUT = dout_out;
`ifdef XIL_TIMING // inputs with timing checks
assign clk_in = clk_delay;
assign din_in = din_delay;
assign read_in = read_delay;
assign shift_in = shift_delay;
`endif // `ifdef XIL_TIMING
`ifndef XIL_TIMING // inputs with timing checks
assign clk_in = CLK;
assign din_in = DIN;
assign read_in = READ;
assign shift_in = SHIFT;
`endif // `ifndef XIL_TIMING
always @(posedge clk_in) begin
if(read_in == 1'b1) begin
dna_val = SIM_DNA_VALUE_reg;
dout_out = 1'b1;
end // read_in == 1'b1
else if(read_in == 1'b0)
if(shift_in == 1'b1) begin
dna_val = {dna_val[MSB_DNA_BITS-1 : 0], din_in};
dout_out = dna_val[MSB_DNA_BITS];
end // shift_in == 1'b1
end // always @ (posedge clk_in)
specify
(CLK => DOUT) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING // Simprim
$setuphold (posedge CLK, negedge DIN, 0:0:0, 0:0:0, notifier,,, clk_delay, din_delay);
$setuphold (posedge CLK, negedge READ, 0:0:0, 0:0:0, notifier,,, clk_delay, read_delay);
$setuphold (posedge CLK, negedge SHIFT, 0:0:0, 0:0:0, notifier,,, clk_delay, shift_delay);
$setuphold (posedge CLK, posedge DIN, 0:0:0, 0:0:0, notifier,,, clk_delay, din_delay);
$setuphold (posedge CLK, posedge READ, 0:0:0, 0:0:0, notifier,,, clk_delay, read_delay);
$setuphold (posedge CLK, posedge SHIFT, 0:0:0, 0:0:0, notifier,,, clk_delay, shift_delay);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
//`endcelldefine
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