// parameter EXTRA_ADDR = 'h824, // address to set extra parameters (currently just inv_clk_div)
// parameter EXTRA_ADDR_MASK = 'hbff // address mask for extra parameters
parameterDLY_LD_REL='h080,// address to generate delay load
parameterDLY_LD_REL_MASK='h380,// address mask to generate delay load
parameterDLY_SET_REL='h070,// address to generate delay set
parameterDLY_SET_REL_MASK='h3ff,// address mask to generate delay set
parameterRUN_CHN_REL='h000,// address to set sequnecer channel and run (4 LSB-s - channel)
parameterRUN_CHN_REL_MASK='h3f0,// address mask to generate sequencer channel/run
parameterPATTERNS_REL='h020,// address to set DQM and DQS patterns (16'h0055)
parameterPATTERNS_REL_MASK='h3ff,// address mask to set DQM and DQS patterns
parameterPAGES_REL='h021,// address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
parameterPAGES_REL_MASK='h3ff,// address mask to set DQM and DQS patterns
parameterCMDA_EN_REL='h022,// address to enable('h823)/disable('h822) command/address outputs
parameterCMDA_EN_REL_MASK='h3fe,// address mask for command/address outputs
parameterEXTRA_REL='h024,// address to set extra parameters (currently just inv_clk_div)
parameterEXTRA_REL_MASK='h3ff// address mask for extra parameters
)(
inputclk,
inputmclk,
...
...
@@ -46,7 +83,7 @@ module ddrc_control #(
output[7:0]dly_data,// 8-bit IDELAY/ODELAY (fine) and MMCM phase shift
output[6:0]dly_addr,// address to select delay register
outputld_delay,// write dly_data to dly_address, one mclk active pulse
outputset,// transfer (activate) all delays simultaneosly, 1 mclk pulse
outputdly_set,// transfer (activate) all delays simultaneosly, 1 mclk pulse
// control: additional signals
outputcmda_tri,// tri-state all command and address lines to DDR chip
outputinv_clk_div,// invert clk_div to ISERDES
...
...
@@ -59,11 +96,122 @@ module ddrc_control #(
output[1:0]port1_int_page// port 1 PHY-side buffer read page (to be controlled by arbiter later, set to 2'b0)
);
localparamDLY_LD_ADDR=CONTROL_ADDR|DLY_LD_REL;// address to generate delay load
localparamDLY_LD_ADDR_MASK=CONTROL_ADDR_MASK|DLY_LD_REL_MASK;// address mask to generate delay load
localparamDLY_SET_ADDR=CONTROL_ADDR|DLY_SET_REL;// address to generate delay set
localparamDLY_SET_ADDR_MASK=CONTROL_ADDR_MASK|DLY_SET_REL_MASK;// address mask to generate delay set
localparamRUN_CHN_ADDR=CONTROL_ADDR|RUN_CHN_REL;// address to set sequnecer channel and run (4 LSB-s - channel)
localparamRUN_CHN_ADDR_MASK=CONTROL_ADDR_MASK|RUN_CHN_REL_MASK;// address mask to generate sequencer channel/run
localparamPATTERNS_ADDR=CONTROL_ADDR|PATTERNS_REL;// address to set DQM and DQS patterns (16'h0055)
localparamPATTERNS_ADDR_MASK=CONTROL_ADDR_MASK|PATTERNS_REL_MASK;// address mask to set DQM and DQS patterns
localparamPAGES_ADDR=CONTROL_ADDR|PAGES_REL;// address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
localparamPAGES_ADDR_MASK=CONTROL_ADDR_MASK|PAGES_REL_MASK;// address mask to set DQM and DQS patterns
localparamCMDA_EN_ADDR=CONTROL_ADDR|CMDA_EN_REL;// address to enable('h823)/disable('h822) command/address outputs
localparamCMDA_EN_ADDR_MASK=CONTROL_ADDR_MASK|CMDA_EN_REL_MASK;// address mask for command/address outputs
localparamEXTRA_ADDR=CONTROL_ADDR|EXTRA_REL;// address to set extra parameters (currently just inv_clk_div)
localparamEXTRA_ADDR_MASK=CONTROL_ADDR_MASK|EXTRA_REL_MASK;// address mask for extra parameters
regbusy_r=0;
regselected_r=0;
regselected=0;
regselected_busy=0;
(*keep="true"*)wirefifo_half_empty;// just debugging with (* keep = "true" *)
wire[AXI_WR_ADDR_BITS-1:0]waddr_fifo_out;
wire[31:0]wdata_fifo_out;
// reg fifo_re; // wrong, need to have (fifo!=1) || !re
wirefifo_nempty;
wirefifo_re=fifo_nempty;// try simpler
reg[AXI_WR_ADDR_BITS-1:0]waddr_fifo_out_r;
reg[31:0]wdata_fifo_out_r;
regdly_ld_r=0;
regdly_set_r=0;
regrun_seq_r=0;
reg[7:0]dqs_pattern_r;// DQS pattern during write (normally 8'h55)
reg[7:0]dqm_pattern_r;// DQM pattern (just for testing, should be 8'h0)
reg[1:0]port0_page_r;// port 0 buffer read page (to be controlled by arbiter later, set to 2'b0)
reg[1:0]port0_int_page_r;// port 0 PHY-side write to buffer page (to be controlled by arbiter later, set to 2'b0)
reg[1:0]port1_page_r;// port 1 buffer write page (to be controlled by arbiter later, set to 2'b0)
reg[1:0]port1_int_page_r;// port 1 PHY-side buffer read page (to be controlled by arbiter later, set to 2'b0)
regcmda_en_r;// enable (tri-state off) all command and address lines to DDR chip
reginv_clk_div_r;// invert clk_div to ISERDES
assignld_delay=dly_ld_r;
assigndly_set=dly_set_r;
assigndly_data=wdata_fifo_out_r[7:0];// WARNING: [Synth 8-3936] Found unconnected internal register 'wdata_fifo_out_r_reg' and it is trimmed from '32' to '11' bits. [ddrc_control.v:100]
assigndly_addr=waddr_fifo_out_r[6:0];//WARNING: [Synth 8-3936] Found unconnected internal register 'waddr_fifo_out_r_reg' and it is trimmed from '12' to '7' bits. [ddrc_control.v:101]
