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Elphel
eddr3
Commits
c72a52a9
Commit
c72a52a9
authored
May 31, 2014
by
Andrey Filippov
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added warnings for illegal fine delays
parent
4bacb90a
Changes
2
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+10
-0
idelay_fine_pipe.v
wrap/idelay_fine_pipe.v
+5
-0
odelay_fine_pipe.v
wrap/odelay_fine_pipe.v
+5
-0
No files found.
wrap/idelay_fine_pipe.v
View file @
c72a52a9
...
...
@@ -43,6 +43,11 @@ module idelay_fine_pipe
if
(
rst
)
fdly
<=
DELAY_VALUE
[
2
:
0
]
;
else
if
(
set
)
fdly
<=
fdly_pre
;
end
`ifdef
IVERILOG
always
@
(
fdly_pre
)
begin
if
(
fdly_pre
>
3'h4
)
$
display
(
"ERROR: fine idelay value should be <5, specified %d @ %t"
,
fdly_pre
,
$
time
)
;
end
`endif
(
*
IODELAY_GROUP
=
IODELAY_GRP
*
)
IDELAYE2_FINEDELAY
#(
.
CINVCTRL_SEL
(
"FALSE"
)
,
...
...
wrap/odelay_fine_pipe.v
View file @
c72a52a9
...
...
@@ -42,6 +42,11 @@ module odelay_fine_pipe
if
(
rst
)
fdly
<=
DELAY_VALUE
[
2
:
0
]
;
else
if
(
set
)
fdly
<=
fdly_pre
;
end
`ifdef
IVERILOG
always
@
(
fdly_pre
)
begin
if
(
fdly_pre
>
3'h4
)
$
display
(
"ERROR: fine odelay value should be <5, specified %d @ %t"
,
fdly_pre
,
$
time
)
;
end
`endif
(
*
IODELAY_GROUP
=
IODELAY_GRP
*
)
ODELAYE2_FINEDELAY
#(
...
...
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