addint top level module to test pasrt of ddr controller

axi/axibram_read.v

@@ -18,11 +18,12 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/> .
  *******************************************************************************/
-module  axibram_read#(
+module  axibram_read #(
     parameter ADDRESS_BITS = 10 // number of memory address bits
 )(
    input         aclk,    // clock - should be buffered
-   input         aresetn, // reset, active low
+//   input         aresetn, // reset, active low
+   input         rst, // reset, active high
 // AXI Read Address   
    input  [31:0] araddr,  // ARADDR[31:0], input 
    input         arvalid, // ARVALID, input
@@ -42,7 +43,12 @@ module  axibram_read#(
    output reg [11:0] rid,     // RID[11:0], output
    output reg    rlast,   // RLAST, output
    output [ 1:0] rresp,
-// BRAM interface   
+// External memory synchronization
+   output [ADDRESS_BITS-1:0] pre_araddr, // same as awaddr_out, early address to decode and return dev_ready
+   output        start_burst, // start of read burst, valid pre_araddr, save externally to control ext. dev_ready multiplexer
+   input         dev_ready,   // extrernal combinatorial ready signal, multiplexed from different sources according to pre_araddr@start_burst
+   
+// External memory interface   
    output        bram_rclk,  //      .rclk(aclk),                  // clock for read port
    output  [ADDRESS_BITS-1:0] bram_raddr, //   .raddr(read_in_progress?read_address[9:0]:10'h3ff),    // read address
    output        bram_ren,   //      .ren(bram_reg_re_w) ,      // read port enable
@@ -60,7 +66,7 @@ module  axibram_read#(
     wire [ 3:0] arlen_out;
     wire [ADDRESS_BITS-1:0] araddr_out;
     wire [11:0] arid_out;
-    wire rst=~aresetn;
+//    wire rst=~aresetn;
     reg  read_in_progress=0;
     reg  read_in_progress_d=0; // delayed by one active cycle (not skipped)
     reg  read_in_progress_or=0; // read_in_progress || read_in_progress_d
@@ -101,17 +107,25 @@ module  axibram_read#(
     wire pre_rvalid_w;
     assign  pre_rvalid_w=bram_reg_re_w || (rvalid && !rready);
     
-    reg bram_reg_re_0;
-
     wire pre_left_zero_w;
+    // TODO: Speed up by moving registers
+    // SuppressWarnings VEditor all - not yet used 
+    reg bram_reg_re_0;
+    // SuppressWarnings VEditor all - not yet used 
     reg last_in_burst_1;
+    // SuppressWarnings VEditor all - not yet used 
     reg last_in_burst_0;
+    // SuppressWarnings VEditor all - not yet used 
     reg start_read_burst_0;
+    // SuppressWarnings VEditor all - not yet used 
     reg start_read_burst_1;
     reg [11:0] pre_rid0;
     reg [11:0] pre_rid;
-
-// Block RAM interface
+// External memory interface - synchronization with ready
+   assign pre_araddr=  araddr_out[ADDRESS_BITS-1:0];
+   assign start_burst= start_read_burst_w;
+   //input dev_ready,   // extrernal combinatorial ready signal, multiplexed from different sources according to pre_araddr@start_burst 
+// External memory interface
    assign  bram_rclk =  aclk;  // clock for read port
    assign  bram_raddr = read_in_progress?read_address[ADDRESS_BITS-1:0]:{ADDRESS_BITS{1'b1}};  // read address
    assign  bram_ren =   bram_reg_re_w;     // read port enable
@@ -184,7 +198,7 @@ module  axibram_read#(
     assign  pre_left_zero_w=start_read_burst_w?(arlen_out[3:0]==4'b0):(bram_reg_re_w && (read_left==4'b0001));
 //    assign bram_reg_re_w=     read_in_progress && (!rvalid || rready);
 
-    assign bram_reg_re_w=   read_in_progress_or && (!rvalid || rready); // slower/simplier
+    assign bram_reg_re_w=   dev_ready && read_in_progress_or && (!rvalid || rready); // slower/simplier
 //    assign bram_reg_re_w=   rready? read_in_progress : bram_reg_re_0; // faster - more verification
     
     

axi/axibram_write.v

@@ -19,11 +19,12 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/> .
  *******************************************************************************/
-module  axibram_write#(
+module  axibram_write #(
     parameter ADDRESS_BITS = 10 // number of memory address bits
 )(
    input         aclk,    // clock - should be buffered
-   input         aresetn, // reset, active low
+//   input         aresetn, // reset, active low
+   input         rst,     // reset, active highw
    
 // AXI Write Address
    input  [31:0] awaddr,  // AWADDR[31:0], input
@@ -50,14 +51,18 @@ module  axibram_write#(
    output [11:0] bid,     // BID[11:0], output
    output [ 1:0] bresp,    // BRESP[1:0], output
    
-// BRAM interface   
+// BRAM (and other write modules) interface
+   output [ADDRESS_BITS-1:0] pre_awaddr, // same as awaddr_out, early address to decode and return dev_ready
+   output        start_burst, // start of write burst, valid pre_awaddr, save externally to control ext. dev_ready multiplexer
+   input         dev_ready,   // extrernal combinatorial ready signal, multiplexed from different sources according to pre_awaddr@start_burst
+    
    output        bram_wclk,
    output  [ADDRESS_BITS-1:0] bram_waddr,
-   output        bram_wen,
+   output        bram_wen,    // external memory wreite enable, (internally combined with registered dev_ready
    output  [3:0] bram_wstb, 
    output [31:0] bram_wdata
 );
-    wire rst=~aresetn;
+//    wire rst=~aresetn;
 // **** Write channel: ****
     wire aw_nempty;
     wire aw_half_full;
@@ -87,12 +92,13 @@ module  axibram_write#(
     wire        bram_we_w;          // write BRAM memory 
     wire        start_write_burst_w;
     wire        write_in_progress_w;
+    reg         dev_ready_r;        // device, selected at start burst
     assign      next_wr_address_w=
       wburst[1]?
         (wburst[0]? {ADDRESS_BITS{1'b0}}:((write_address[ADDRESS_BITS-1:0]+1) & {{(ADDRESS_BITS-4){1'b1}}, ~wlen[3:0]})):
         (wburst[0]? (write_address[ADDRESS_BITS-1:0]+1):(write_address[ADDRESS_BITS-1:0]));
         
-    assign      bram_we_w= w_nempty &&  write_in_progress;
+    assign      bram_we_w= w_nempty &&  write_in_progress && dev_ready_r;
     assign start_write_burst_w=aw_nempty && (!write_in_progress || (w_nempty && (write_left[3:0]==4'b0)));
     assign write_in_progress_w=aw_nempty || (write_in_progress && !(w_nempty && (write_left[3:0]==4'b0))); 
     
@@ -113,6 +119,9 @@ module  axibram_write#(
       if   (rst)                    write_address <= {ADDRESS_BITS{1'b0}};
       else if (start_write_burst_w) write_address <= awaddr_out[ADDRESS_BITS-1:0]; // precedence over inc
       else if (bram_we_w)           write_address <= next_wr_address_w;
+      
+      if (rst) dev_ready_r <= 1'b0;
+      else     dev_ready_r <= dev_ready;
     end
 // **** Write responce channel ****    
     wire [ 1:0] bresp_in;
@@ -132,7 +141,10 @@ module  axibram_write#(
     end
 */
 
-// BRAM interface   
+// external memory interface (write only)
+   assign pre_awaddr=awaddr_out[ADDRESS_BITS-1:0];
+   assign start_burst=start_write_burst_w;
+   
    assign  bram_wclk  = aclk;
    assign  bram_waddr = write_address[ADDRESS_BITS-1:0];
    assign  bram_wen   = bram_we_w; 

phy/ddr3c16.v → phy/ddrc_sequencer.v

 /*******************************************************************************
- * Module: ddr3c16
+ * Module: ddrc_sequencer
  * Date:2014-05-16  
  * Author: Andrey Filippov
- * Description: ddr3 controller, 16 channel
+ * Description: ddr3 sequnecer
  *
  * Copyright (c) 2014 Elphel, Inc.
- * ddr3c16.v is free software; you can redistribute it and/or modify
+ * ddrc_sequencer.v is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation, either version 3 of the License, or
  * (at your option) any later version.
  *
- *  ddr3c16.v is distributed in the hope that it will be useful,
+ *  ddrc_sequencer.v is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
@@ -20,7 +20,7 @@
  *******************************************************************************/
 `timescale 1ns/1ps
 
-module  ddr3c16   #(
+module  ddrc_sequencer   #(
     parameter PHASE_WIDTH =     8,
     parameter SLEW_DQ =         "SLOW",
     parameter SLEW_DQS =        "SLOW",