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doxverilog
Commit 99433b3d authored by Dimitri van Heesch's avatar Dimitri van Heesch
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Replaced the VHDL parser with the VHDL scanner from 1.7.5 to avoid potential licensing issues

parent 28f40b3a
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Showing with 2813 additions and 6519 deletions
src/Makefile.in
View file @ 99433b3d
......@@ -48,7 +48,6 @@ distclean: clean
ce_parse.cpp ce_parse.h tag.cpp commentscan.cpp \
declinfo.cpp defargs.cpp commentcnv.cpp doctokenizer.cpp \
pycode.cpp pyscanner.cpp fortrancode.cpp fortranscanner.cpp \
vhdlscanner.cpp vhdlcode.cpp tclscanner.cpp vhdlparser.h \
vhdlparser.cpp
vhdlscanner.cpp vhdlcode.cpp tclscanner.cpp
FORCE:
src/context.cpp
View file @ 99433b3d
......@@ -23,6 +23,7 @@
#include "membername.h"
#include "parserintf.h"
#include "portable.h"
#include "arguments.h"
// TODO: pass the current file to Dot*::writeGraph, so the user can put dot graphs in other
// files as well
......
src/docparser.cpp
View file @ 99433b3d
......@@ -2904,8 +2904,6 @@ void DocVhdlFlow::parse()
DBG(("DocVhdlFlow::parse() end\n"));
DocNode *n=g_nodeStack.pop();
ASSERT(n==this);
VhdlDocGen::createFlowChart(g_memberDef);
}
......
src/doxygen.cpp
View file @ 99433b3d
......@@ -11049,7 +11049,7 @@ void parseInput()
flushUnresolvedRelations();
if (Config_getBool("OPTIMIZE_OUTPUT_VHDL"))
{
VhdlDocGen::computeVhdlComponentRelations();
VhdlDocGen::computeVhdlComponentRelations();
}
computeClassRelations();
g_classEntries.clear();
......@@ -11192,13 +11192,6 @@ void parseInput()
g_s.begin("Adding members to index pages...\n");
addMembersToIndex();
g_s.end();
if (Config_getBool("OPTIMIZE_OUTPUT_VHDL") &&
Config_getBool("HAVE_DOT") &&
Config_getEnum("DOT_IMAGE_FORMAT")=="svg")
{
VhdlDocGen::writeOverview();
}
}
void generateOutput()
......
src/htmldocvisitor.cpp
View file @ 99433b3d
......@@ -1773,35 +1773,14 @@ void HtmlDocVisitor::visitPost(DocHtmlBlockQuote *b)
forceStartParagraph(b);
}
void HtmlDocVisitor::visitPre(DocVhdlFlow *vf)
void HtmlDocVisitor::visitPre(DocVhdlFlow *)
{
if (m_hide) return;
if (VhdlDocGen::getFlowMember()) // use VHDL flow chart creator
{
forceEndParagraph(vf);
QCString fname=FlowChart::convertNameToFileName();
m_t << "<p>";
m_t << "flowchart: " ; // TODO: translate me
m_t << "<a href=\"";
m_t << fname.data();
m_t << ".svg\">";
m_t << VhdlDocGen::getFlowMember()->name().data();
m_t << "</a>";
if (vf->hasCaption())
{
m_t << "<br />";
}
}
}
void HtmlDocVisitor::visitPost(DocVhdlFlow *vf)
void HtmlDocVisitor::visitPost(DocVhdlFlow *)
{
if (m_hide) return;
if (VhdlDocGen::getFlowMember()) // use VHDL flow chart creator
{
m_t << "</p>";
forceStartParagraph(vf);
}
}
void HtmlDocVisitor::visitPre(DocParBlock *)
......
src/index.cpp
View file @ 99433b3d
......@@ -2053,10 +2053,6 @@ static void writeAnnotatedIndex(OutputList &ol)
QCString title = lne ? lne->title() : theTranslator->trCompoundList();
bool addToIndex = lne==0 || lne->visible();
if (Config_getBool("OPTIMIZE_OUTPUT_VHDL"))
{
VhdlDocGen::findConstraintFile(lne);
}
startFile(ol,"annotated",0,title,HLI_Annotated);
......
src/libdoxygen.pro.in
View file @ 99433b3d
......@@ -201,7 +201,6 @@ SOURCES = arguments.cpp \
../generated_src/doxygen/ce_parse.cpp \
../generated_src/doxygen/constexp.cpp \
../generated_src/doxygen/vhdlcode.cpp \
../generated_src/doxygen/vhdlparser.cpp \
../generated_src/doxygen/vhdlscanner.cpp \
../generated_src/doxygen/code.cpp \
../generated_src/doxygen/commentcnv.cpp \
......
src/libdoxygen.t.in
View file @ 99433b3d
......@@ -111,16 +111,9 @@ sub GenerateLex {
$(YACC) -l -d -p ce_parsexpYY constexp.y -o \$(GENERATED_SRC)/ce_parse.c
-rm $(GENERATED_SRC)/ce_parse.c
#$ GenerateDep("\$(GENERATED_SRC)/vhdlscanner.cpp","vhdlscanner.l","\$(GENERATED_SRC)/vhdlparser.h");
#$ GenerateDep("\$(GENERATED_SRC)/vhdlscanner.cpp","vhdlscanner.l");
#$ GenerateLex("vhdlscanner",1);
#$ GenerateDep("\$(GENERATED_SRC)/vhdlparser.cpp","vhdlparser.y");
$(YACC) -l -p vhdlscannerYY vhdlparser.y -o \$(GENERATED_SRC)/vhdlparser.cpp
#$ GenerateDep("\$(GENERATED_SRC)/vhdlparser.h","vhdlparser.y");
$(YACC) -l -d -p vhdlscannerYY vhdlparser.y -o \$(GENERATED_SRC)/vhdlparser.c
-rm $(GENERATED_SRC)/vhdlparser.c
TO_C_CMD=$(PYTHON) to_c_cmd.py < $< > $@
#$ GenerateDep("layout.cpp","\$(GENERATED_SRC)/layout_default.xml.h");
......
src/outputlist.cpp
View file @ 99433b3d
......@@ -169,8 +169,6 @@ void OutputList::writeDoc(DocRoot *root,Definition *ctx,MemberDef *md)
// ctx?ctx->getDefFileExtension().data():"<null>");
if (og->isEnabled()) og->writeDoc(root,ctx,md);
}
VhdlDocGen::setFlowMember(0);
}
bool OutputList::parseText(const QCString &textStr)
......
src/vhdldocgen.cpp
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src/vhdldocgen.h
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src/vhdlparser.y deleted 100644 → 0
View file @ 28f40b3a
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src/vhdlscanner.h
View file @ 99433b3d
......@@ -28,8 +28,9 @@
#include <unistd.h>
#include <qfile.h>
#include <qdict.h>
#include "vhdldocgen.h"
#include "entry.h"
#include "memberlist.h"
class Entry;
class ClassSDict;
......@@ -37,10 +38,9 @@ class FileStorage;
class ClassDef;
class MemberDef;
class QStringList;
class MemberList;
/** VHDL parser using state-based lexical scanning.
/** \brief VHDL parser using state-based lexical scanning.
*
* This is the VHDL language parser for doxygen.
*/
......@@ -50,8 +50,8 @@ class VHDLLanguageScanner : public ParserInterface
virtual ~VHDLLanguageScanner() {}
void startTranslationUnit(const char *) {}
void finishTranslationUnit() {}
void parseInput(const char * fileName,
const char *fileBuf,
void parseInput(const char * fileName,
const char *fileBuf,
Entry *root,
bool sameTranslationUnit,
QStrList &filesInSameTranslationUnit);
......@@ -75,73 +75,8 @@ class VHDLLanguageScanner : public ParserInterface
void parsePrototype(const char *text);
};
/** Container for vhdlscanner */
struct VhdlContainer
{
int yyLineNr; // current line no
int iLine; // line no of last t_identifier
QCString qstr; // t_identifier
QCString fileName; // current file
Entry* root; // root
};
/** Configuration node for VHDL */
struct VhdlConfNode
{
VhdlConfNode(const char* a,const char* b,const char* config,const char* cs,bool leaf)
{
arch=a; // architecture e.g. for iobuffer
arch=arch.lower();
binding=b; // binding e.g. use entiy work.xxx(bev)
binding=binding.lower();
confVhdl=config; // configuration foo is bar
compSpec=cs;
isInlineConf=false; // primary configuration?
isLeaf=leaf;
};
QCString confVhdl;
QCString arch;
QCString binding;
QCString compSpec;
int level;
bool isLeaf;
bool isInlineConf;
};
// returns the current conpound entity,architecture, package,package body
Entry* getVhdlCompound();
// return the current parsed entry
Entry* getCurrentVhdlEntry();
void newVhdlEntry();
void initVhdlParser();
struct VhdlContainer* getVhdlCont();
// returns the parsed line
// @ param object index of vhdl keyword like t_Identifier t_Entity
int getParsedLine(int object);
void vhdlscanFreeScanner();
void vhdlParse();
// return the list of component instantiations e.g. foo: component bar
QList<Entry> & getVhdlInstList();
// returns configuration list
QList<VhdlConfNode>& getVhdlConfiguration();
// returns library/used list
QList<Entry> & getLibUse();
void isVhdlDocPending();
//---------------------------------------------------------------------------------
#endif
src/vhdlscanner.l
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winbuild/Doxygen.vcproj
View file @ 99433b3d
......@@ -926,14 +926,6 @@
RelativePath="..\src\vhdldocgen.cpp"
>
</File>
<File
RelativePath="$(IntDir)\vhdlparser.cpp"
>
</File>
<File
RelativePath="$(IntDir)\vhdlparser.h"
>
</File>
<File
RelativePath="..\src\xmldocvisitor.cpp"
>
......@@ -991,50 +983,6 @@
/>
</FileConfiguration>
</File>
<File
RelativePath="..\src\vhdlparser.y"
>
<FileConfiguration
Name="Debug|Win32"
>
<Tool
Name="VCCustomBuildTool"
Description="Running bison on vhdlparser.y"
CommandLine="bison -l -d -p vhdlscannerYY $(InputPath) -o $(IntDir)\vhdlparser.c&#x0D;&#x0A;bison -l -p vhdlscannerYY $(InputPath) -o $(IntDir)\vhdlparser.cpp&#x0D;&#x0A;del $(IntDir)\vhdlparser.c&#x0D;&#x0A;"
Outputs="$(IntDir)\vhdlparser.cpp"
/>
</FileConfiguration>
<FileConfiguration
Name="Debug|x64"
>
<Tool
Name="VCCustomBuildTool"
Description="Running bison on vhdlparser.y"
CommandLine="bison -l -d -p vhdlscannerYY $(InputPath) -o $(IntDir)\vhdlparser.c&#x0D;&#x0A;bison -l -p vhdlscannerYY $(InputPath) -o $(IntDir)\vhdlparser.cpp&#x0D;&#x0A;del $(IntDir)\vhdlparser.c&#x0D;&#x0A;"
Outputs="$(IntDir)\vhdlparser.cpp"
/>
</FileConfiguration>
<FileConfiguration
Name="Release|Win32"
>
<Tool
Name="VCCustomBuildTool"
Description="Running bison on vhdlparser.y"
CommandLine="bison -l -d -p vhdlscannerYY $(InputPath) -o $(IntDir)\vhdlparser.c&#x0D;&#x0A;bison -l -p vhdlscannerYY $(InputPath) -o $(IntDir)\vhdlparser.cpp&#x0D;&#x0A;del $(IntDir)\vhdlparser.c&#x0D;&#x0A;"
Outputs="$(IntDir)\vhdlparser.cpp"
/>
</FileConfiguration>
<FileConfiguration
Name="Release|x64"
>
<Tool
Name="VCCustomBuildTool"
Description="Running bison on vhdlparser.y"
CommandLine="bison -l -d -p vhdlscannerYY $(InputPath) -o $(IntDir)\vhdlparser.c&#x0D;&#x0A;bison -l -p vhdlscannerYY $(InputPath) -o $(IntDir)\vhdlparser.cpp&#x0D;&#x0A;del $(IntDir)\vhdlparser.c&#x0D;&#x0A;"
Outputs="$(IntDir)\vhdlparser.cpp"
/>
</FileConfiguration>
</File>
</Filter>
<Filter
Name="Lex Files"
......
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