Commit 85c46d2a authored by mk's avatar mk
Browse files

some changes

parent ed39dab5

src/Makefile.in

+1 −1
Original line number Original line Diff line number Diff line
@@ -48,6 +48,6 @@ distclean: clean 
	       ce_parse.cpp ce_parse.h tag.cpp commentscan.cpp \

	       ce_parse.cpp ce_parse.h tag.cpp commentscan.cpp \

	       declinfo.cpp defargs.cpp commentcnv.cpp doctokenizer.cpp \

	       declinfo.cpp defargs.cpp commentcnv.cpp doctokenizer.cpp \

	       pycode.cpp pyscanner.cpp fortrancode.cpp fortranscanner.cpp \

	       pycode.cpp pyscanner.cpp fortrancode.cpp fortranscanner.cpp \

	       vhdlscanner.cpp vhdlcode.cpp tclscanner.cpp

	       vhdlscanner.cpp vhdlcode.cpp tclscanner.cpp verilogscanner.cpp VPreLex.cpp





FORCE:
 
FORCE:

src/VPreLex.l

0 → 100644
+636 −0

File added.

Preview size limit exceeded, changes collapsed.

src/classdef.cpp

+20 −6

File changed.

Preview size limit exceeded, changes collapsed.

src/config.l

+7 −0
Original line number Original line Diff line number Diff line
@@ -1441,6 +1441,7 @@ void Config::check() 
    filePatternList.append("*.for");

    filePatternList.append("*.for");

    filePatternList.append("*.vhd");

    filePatternList.append("*.vhd");

    filePatternList.append("*.vhdl");

    filePatternList.append("*.vhdl");

    filePatternList.append("*.v");

    filePatternList.append("*.tcl");

    filePatternList.append("*.tcl");

    filePatternList.append("*.md");

    filePatternList.append("*.md");

    filePatternList.append("*.markdown");

    filePatternList.append("*.markdown");
@@ -1463,6 +1464,7 @@ void Config::check() 
      filePatternList.append("*.PY");

      filePatternList.append("*.PY");

      filePatternList.append("*.F90");

      filePatternList.append("*.F90");

      filePatternList.append("*.F");

      filePatternList.append("*.F");

	   filePatternList.append("*.V");

      filePatternList.append("*.VHD");

      filePatternList.append("*.VHD");

      filePatternList.append("*.VHDL");

      filePatternList.append("*.VHDL");

      filePatternList.append("*.TCL");

      filePatternList.append("*.TCL");
@@ -1583,6 +1585,11 @@ void Config::check() 
    annotationFromBrief.append("the");

    annotationFromBrief.append("the");

  }

  }

  

  

   if (Config_getBool("OPTIMIZE_OUTPUT_VERILOG"))

  {

   Config_getBool("OPTIMIZE_OUTPUT_VHDL")       = TRUE;

  }



  // some default settings for vhdl

  // some default settings for vhdl

  if (Config_getBool("OPTIMIZE_OUTPUT_VHDL") && 

  if (Config_getBool("OPTIMIZE_OUTPUT_VHDL") && 

      (Config_getBool("INLINE_INHERITED_MEMB") || 

      (Config_getBool("INLINE_INHERITED_MEMB") ||

src/config.xml

+17 −0

File changed.

Preview size limit exceeded, changes collapsed.