some changes

src/Makefile.in

@@ -48,6 +48,6 @@ distclean: clean
 	       ce_parse.cpp ce_parse.h tag.cpp commentscan.cpp \
 	       declinfo.cpp defargs.cpp commentcnv.cpp doctokenizer.cpp \
 	       pycode.cpp pyscanner.cpp fortrancode.cpp fortranscanner.cpp \
-	       vhdlscanner.cpp vhdlcode.cpp tclscanner.cpp
+	       vhdlscanner.cpp vhdlcode.cpp tclscanner.cpp verilogscanner.cpp VPreLex.cpp
 
 FORCE:

src/classdef.cpp

@@ -44,6 +44,7 @@
 #include "filedef.h"
 #include "namespacedef.h"
 #include "membergroup.h"
+#include "verilogdocgen.h"
 
 //-----------------------------------------------------------------------------
 
@@ -311,7 +312,7 @@ QCString ClassDef::displayName(bool includeScope) const
   SrcLangExt lang = getLanguage();
   //static bool vhdlOpt = Config_getBool("OPTIMIZE_OUTPUT_VHDL");
   QCString n;
-  if (lang==SrcLangExt_VHDL)
+  if (lang==SrcLangExt_VHDL || lang==SrcLangExt_VERILOG)
   {
     n = VhdlDocGen::getClassName(this);
   }
@@ -418,7 +419,7 @@ void ClassDef::internalInsertMember(MemberDef *md,
   //printf("insertInternalMember(%s) isHidden()=%d\n",md->name().data(),md->isHidden());
   if (md->isHidden()) return;
 
-  if (getLanguage()==SrcLangExt_VHDL)
+  if (getLanguage()==SrcLangExt_VHDL || getLanguage()==SrcLangExt_VERILOG)
   {
     QCString title=VhdlDocGen::trVhdlType(md->getMemberSpecifiers(),FALSE);
     if (!m_impl->vhdlSummaryTitles.find(title))
@@ -1476,7 +1477,13 @@ void ClassDef::endMemberDeclarations(OutputList &ol)
   static bool inlineInheritedMembers = Config_getBool("INLINE_INHERITED_MEMB");
   if (!inlineInheritedMembers && countAdditionalInheritedMembers()>0)
   {
-    ol.startMemberHeader("inherited");
+      if(Config_getBool("OPTIMIZE_OUTPUT_VERILOG"))
+	  {	
+		  ol.endMemberSections();
+	    	return;
+	  }
+
+	ol.startMemberHeader("inherited");
     ol.parseText(theTranslator->trAdditionalInheritedMembers());
     ol.endMemberHeader();
     writeAdditionalInheritedMembers(ol);
@@ -1857,9 +1864,12 @@ void ClassDef::writeDeclarationLink(OutputList &ol,bool &found,const char *heade
       {
         ol.parseText(header);
       }
-      else if (lang==SrcLangExt_VHDL)
+      else if (lang==SrcLangExt_VHDL || lang==SrcLangExt_VERILOG)
       {
-        ol.parseText(VhdlDocGen::trVhdlType(VhdlDocGen::ARCHITECTURE,FALSE));
+         if(lang==SrcLangExt_VERILOG)
+		 ol.parseText("Modules");
+	  else
+		  ol.parseText(VhdlDocGen::trVhdlType(VhdlDocGen::ARCHITECTURE,FALSE));
       }
       else
       {
@@ -1876,6 +1886,10 @@ void ClassDef::writeDeclarationLink(OutputList &ol,bool &found,const char *heade
     QCString ctype = compoundTypeString();
     QCString cname = displayName(!localNames);
 
+    
+	 if(lang==SrcLangExt_VERILOG)
+	   ctype=VhdlDocGen::getProtectionName((VhdlDocGen::VhdlClasses)protection());
+	
     if (lang!=SrcLangExt_VHDL) // for VHDL we swap the name and the type
     {
       ol.writeString(ctype);
@@ -2436,7 +2450,7 @@ void ClassDef::writeMemberList(OutputList &ol)
         {
           ol.writeString("<span class=\"mlabel\">");
           QStrList sl;
-          if (lang==SrcLangExt_VHDL)
+          if (lang==SrcLangExt_VHDL || lang==SrcLangExt_VERILOG)
           {
             sl.append(VhdlDocGen::trVhdlType(md->getMemberSpecifiers())); //append vhdl type
           }

src/config.l

@@ -1441,6 +1441,7 @@ void Config::check()
     filePatternList.append("*.for");
     filePatternList.append("*.vhd");
     filePatternList.append("*.vhdl");
+    filePatternList.append("*.v");
     filePatternList.append("*.tcl");
     filePatternList.append("*.md");
     filePatternList.append("*.markdown");
@@ -1463,6 +1464,7 @@ void Config::check()
       filePatternList.append("*.PY");
       filePatternList.append("*.F90");
       filePatternList.append("*.F");
+	   filePatternList.append("*.V");
       filePatternList.append("*.VHD");
       filePatternList.append("*.VHDL");
       filePatternList.append("*.TCL");
@@ -1582,6 +1584,11 @@ void Config::check()
     annotationFromBrief.append("an");
     annotationFromBrief.append("the");
   }
+  
+   if (Config_getBool("OPTIMIZE_OUTPUT_VERILOG"))
+  {
+   Config_getBool("OPTIMIZE_OUTPUT_VHDL")       = TRUE;
+  }
 
   // some default settings for vhdl
   if (Config_getBool("OPTIMIZE_OUTPUT_VHDL") && 

src/config.xml

@@ -577,6 +577,21 @@ Go to the <a href="commands.html">next</a> section or return to the
 <![CDATA[
  Set the \c OPTIMIZE_OUTPUT_VHDL tag to \c YES if your project consists of VHDL 
  sources. Doxygen will then generate output that is tailored for VHDL.
+]]>
+      </docs>
+    </option>
+    <option type='bool' id='OPTIMIZE_OUTPUT_VERILOG' defval='0'>
+      <docs>
+        <![CDATA[
+ Set the \c OPTIMIZE_OUTPUT_VERILOG tag to \c YES if your project consists of VERILOG 
+ sources. Doxygen will then generate output that is tailored for VERILOG.
+]]>
+      </docs>
+    </option>
+    <option type='bool' id='HIDE_PORT' defval='0'>
+      <docs>
+        <![CDATA[
+ Set the \c HIDE_PORT tag to \c YES ports are not displayed.
 ]]>
       </docs>
     </option>
@@ -1306,6 +1321,8 @@ FILE_VERSION_INFO = "cleartool desc -fmt \%Vn"
       <value name='*.tcl'/>
       <value name='*.vhd'/>
       <value name='*.vhdl'/>
+      <value name='*.v'/>
+      <value name='*.V'/>
       <value name='*.ucf'/>
       <value name='*.qsf'/>
       <value name='*.as'/>

src/doxygen.cpp

@@ -25,7 +25,7 @@
 #include <stdlib.h>
 #include <sys/stat.h>
 #include <qtextcodec.h>
-#include <unistd.h>
+//#include <unistd.h>
 #include <errno.h>
 #include <qptrdict.h>
 #include <qtextstream.h>
@@ -99,6 +99,8 @@
 #include "settings.h"
 #include "context.h"
 #include "fileparser.h"
+#include "VPreProc.h"
+#include "verilogscanner.h"
 
 // provided by the generated file resources.cpp
 extern void initResources();
@@ -9330,7 +9332,7 @@ static ParserInterface *getParserForFile(const char *fn)
   {
     extension = ".no_extension";
   }
-
+  fprintf(stderr,"\n search parse for extension \n",extension.data());
   return Doxygen::parserManager->getParser(extension);
 }
 
@@ -9357,15 +9359,44 @@ static void parseFile(ParserInterface *parser,
 
   QFileInfo fi(fileName);
   BufStr preBuf(fi.size()+4096);
+  
 
+  bool jk=Config_getBool("ENABLE_PREPROCESSING");
+  bool ks=parser->needsPreprocessing(extension);
+  
+  msg("parse file mit extension %s %s %d %d",extension.data(),parser->name.data(),jk,ks);
   if (Config_getBool("ENABLE_PREPROCESSING") && 
       parser->needsPreprocessing(extension))
   {
     BufStr inBuf(fi.size()+4096);
-    msg("Preprocessing %s...\n",fn);
+    fprintf(stderr,"\nPreprocessing %s...\n",fn);
+    BufStr strBuf(fi.size()+4096);
+    SrcLangExt lang = getLanguageFromFileName(fn);
+  
+    bool optVerilog = lang==SrcLangExt_VHDL || lang==SrcLangExt_VERILOG;
+ 
+	if(optVerilog) 
+	 {
+	 VerilogPreProc defProc;
+     readInputFile(fileName,strBuf);
+      QCString s=defProc.performPreprocessing(fi,true).data();
+  #if 0
+   // deleteVerilogChars(bb,"\0");
+        printf("\n++++++++++++++++######++++++++++++++++++++++++++++");
+         printf("\n %s",s.data());    
+           printf("\n+++++++++++++++++++++++++++++++++++++");
+   // exit(0);
+   //  defProc.printDict();
+ #endif
+ 
+ preBuf.addArray(s.data(),s.length()); 
+	 }
+	 else 
+	 {
     readInputFile(fileName,inBuf);
     preprocessFile(fileName,inBuf,preBuf);
   }
+  }
   else // no preprocessing
   {
     msg("Reading %s...\n",fn);
@@ -9479,8 +9510,9 @@ static void parseFiles(Entry *root,EntryNav *rootNav)
       QStrList filesInSameTu;
       FileDef *fd=findFileDef(Doxygen::inputNameDict,s->data(),ambig);
       ASSERT(fd!=0);
+	  
       ParserInterface * parser = getParserForFile(s->data());
-      parser->startTranslationUnit(s->data());
+	  parser->startTranslationUnit(s->data());
       parseFile(parser,root,rootNav,fd,s->data(),FALSE,filesInSameTu);
     }
   }
@@ -10013,6 +10045,8 @@ void initDoxygen()
   Doxygen::parserManager->registerParser("dbusxml",      new DBusXMLScanner);
   Doxygen::parserManager->registerParser("tcl",          new TclLanguageScanner);
   Doxygen::parserManager->registerParser("md",           new MarkdownFileParser);
+  Doxygen::parserManager->registerParser("v", new VerilogScanner("verilog"));
+
 
   // register any additional parsers here...
 

src/index.cpp

@@ -47,6 +47,8 @@
 #include "classlist.h"
 #include "namespacedef.h"
 #include "filename.h"
+#include "verilogdocgen.h"
+
 
 #define MAX_ITEMS_BEFORE_MULTIPAGE_INDEX 200
 #define MAX_ITEMS_BEFORE_QUICK_INDEX 30
@@ -434,7 +436,7 @@ static void writeClassTree(OutputList &ol,const BaseClassList *bcl,bool hideSupe
     }
 
     bool b;
-    if (cd->getLanguage()==SrcLangExt_VHDL)
+    if (cd->getLanguage()==SrcLangExt_VHDL || cd->getLanguage()==SrcLangExt_VERILOG)
     {
       b=hasVisibleRoot(cd->subClasses());
     }
@@ -509,7 +511,7 @@ static void writeClassTree(OutputList &ol,const BaseClassList *bcl,bool hideSupe
         //printf("Class %s at %p visited=%d\n",cd->name().data(),cd,cd->visited);
         bool wasVisited=cd->visited;
         cd->visited=TRUE;
-        if (cd->getLanguage()==SrcLangExt_VHDL)	
+        if (cd->getLanguage()==SrcLangExt_VHDL|| cd->getLanguage()==SrcLangExt_VERILOG)	
         {
           writeClassTree(ol,cd->baseClasses(),wasVisited,level+1,ftv,addToIndex);
         }
@@ -809,7 +811,7 @@ static void writeClassTreeForList(OutputList &ol,ClassSDict *cl,bool &started,FT
     //              cd->isVisibleInHierarchy()
     //      );
     bool b;
-    if (cd->getLanguage()==SrcLangExt_VHDL)
+    if (cd->getLanguage()==SrcLangExt_VHDL || cd->getLanguage()==SrcLangExt_VERILOG)
     {
       if ((VhdlDocGen::VhdlClasses)cd->protection()!=VhdlDocGen::ENTITYCLASS)
       {
@@ -875,7 +877,7 @@ static void writeClassTreeForList(OutputList &ol,ClassSDict *cl,bool &started,FT
             ftv->addContentsItem(hasChildren,cd->displayName(),0,0,0,FALSE,FALSE,cd); 
           }
         }
-        if (cd->getLanguage()==SrcLangExt_VHDL && hasChildren) 
+        if ((cd->getLanguage()==SrcLangExt_VHDL || cd->getLanguage()==SrcLangExt_VERILOG ) && hasChildren) 
         {
           writeClassTree(ol,cd->baseClasses(),cd->visited,1,ftv,addToIndex);
           cd->visited=TRUE;
@@ -2267,7 +2269,12 @@ void addClassMemberNameToIndex(MemberDef *md)
   static bool hideFriendCompounds = Config_getBool("HIDE_FRIEND_COMPOUNDS");
   ClassDef *cd=0;
 
- 
+ if ( md->getLanguage()==SrcLangExt_VERILOG) // &&  (VhdlDocGen::isRecord(md) || VhdlDocGen::isUnit(md)))
+  {
+    VerilogDocGen::adjustMemberName(md);
+  }
+  
+
   
   if (md->isLinkableInProject() && 
       (cd=md->getClassDef())    && 

src/libdoxygen.pro.in

@@ -122,6 +122,12 @@ HEADERS      =	arguments.h \
                 xmlgen.h \
                 docbookvisitor.h \
                 docbookgen.h \
+		verilogscanner.h \
+		verilogdocgen.h \
+		verilogparser.hpp \
+		VFileLine.h \
+		VPreLex.h \
+		VPreProc.h \
 		vhdljjparser.h 
 		
 
@@ -206,9 +212,16 @@ SOURCES      =	arguments.cpp \
                 docbookvisitor.cpp \
                 docbookgen.cpp \
                 vhdljjparser.cpp \
+		verilogparser.cpp \
+		verilogdocgen.cpp \
+		VFileLine.cpp \
+			VPreProc.cpp \
+
 	        ../generated_src/doxygen/ce_parse.cpp \
                 ../generated_src/doxygen/constexp.cpp \
 		../generated_src/doxygen/vhdlcode.cpp \
+		../generated_src/doxygen/verilogscanner.cpp \
+		../generated_src/doxygen/VPreLex.cpp \
 		../generated_src/doxygen/code.cpp \
 		../generated_src/doxygen/commentcnv.cpp \
 		../generated_src/doxygen/commentscan.cpp \

src/libdoxygen.t.in

@@ -110,6 +110,17 @@ sub GenerateLex {
 #$ GenerateDep("\$(GENERATED_SRC)/ce_parse.h","constexp.y");
 	$(YACC) -l -d -p ce_parsexpYY constexp.y -o \$(GENERATED_SRC)/ce_parse.c 
 	-rm $(GENERATED_SRC)/ce_parse.c
+	
+#$ GenerateDep("verilogscanner.cpp","verilogscanner.l");
+	$(LEX)  -8  -PverilogScanYY -t verilogscanner.l | $(INCBUFSIZE) >verilogscanner.cpp
+
+#$ GenerateDep("verilogparser.cpp","verilogparser.y");
+	$(YACC)  -v -d verilogparser.y -o verilogparser.cpp 
+
+#$ GenerateDep("VPreLex.cpp","VPreLex.l");
+	$(LEX) -PVPreLex -t VPreLex.l | $(INCBUFSIZE) >VPreLex.cpp 
+	
+
 
 #$ GenerateDep("layout.cpp","\$(GENERATED_SRC)/layout_default.xml.h");
 

src/memberdef.cpp

@@ -1943,8 +1943,9 @@ void MemberDef::getLabels(QStrList &sl,Definition *container) const
     //ol.writeLatexSpacing();
     //ol.startTypewriter();
     //ol.docify(" [");
-    SrcLangExt lang = getLanguage();
-    bool optVhdl = lang==SrcLangExt_VHDL;
+	  SrcLangExt lang = getLanguage();
+  
+    bool optVhdl = lang==SrcLangExt_VHDL || lang==SrcLangExt_VERILOG;
     bool extractPrivate = Config_getBool("EXTRACT_PRIVATE");
     if (optVhdl)
     {
@@ -2532,7 +2533,7 @@ void MemberDef::writeDocumentation(MemberList *ml,OutputList &ol,
 
   SrcLangExt lang = getLanguage();
   //printf("member=%s lang=%d\n",name().data(),lang);
-  bool optVhdl = lang==SrcLangExt_VHDL;
+  bool optVhdl = (lang==SrcLangExt_VHDL) || (lang==SrcLangExt_VERILOG);
   QCString sep = getLanguageSpecificSeparator(lang,TRUE);
 
   QCString scopeName = scName;

src/parserintf.h

@@ -130,7 +130,7 @@ class ParserInterface
      *  comment block parser was invoked.
      */
     virtual void parsePrototype(const char *text) = 0;
-
+	QCString name;
 };
 
 //-----------------------------------------------------------------------------
@@ -174,9 +174,9 @@ class ParserManager
     bool registerExtension(const char *extension, const char *parserName)
     {
       if (parserName==0 || extension==0) return FALSE;
-      ParserInterface *intf = m_parsers.find(parserName);
-      if (intf==0) return FALSE;
-      if (m_extensions.find(extension)!=0) // extension already exists
+      ParserInterface *intf = m_parsers.find(parserName);     
+	  if (intf==0) return FALSE;
+	   if (m_extensions.find(extension)!=0) // extension already exists
       {
         m_extensions.remove(extension); // remove it
       }
@@ -193,9 +193,10 @@ class ParserManager
       QCString ext = QCString(extension).lower();
       if (ext.isEmpty()) ext=".no_extension";
       ParserInterface *intf = m_extensions.find(ext);
-      if (intf==0 && ext.length()>4)
+   //   fprintf(stderr,"\n get parser for extension %s  \n",ext.data());
+	  if (intf==0 && ext.length()>4)
       {
-        intf = m_extensions.find(ext.left(4));
+      	  intf = m_extensions.find(ext.left(4));
       }
       return intf ? intf : m_defaultParser;
     }

src/translator_en.h

@@ -1853,15 +1853,26 @@ class TranslatorEnglish : public Translator
 
     /*! Used file list for a Java enum */
     virtual QCString trEnumGeneratedFromFiles(bool single)
-    { QCString result = "The documentation for this enum was generated from the following file";
-      if (!single) result += "s";
+    { 
+    
+		QCString result;
+	  if(Config_getBool("OPTIMIZE_OUTPUT_VERILOG"))
+      result = "The documentation for this module was generated from the following file";
+      else
+     result = "The documentation for this enum was generated from the following file";
+  
+	if (!single) result += "s";
       result+=":";
       return result;
     }
 
     /*! Header of a Java enum page (Java enums are represented as classes). */
     virtual QCString trEnumReference(const char *name)
-    { return QCString(name)+" Enum Reference"; }
+    { 
+		 if(Config_getBool("OPTIMIZE_OUTPUT_VERILOG"))	
+		return QCString(name)+" Module Reference";
+
+		return QCString(name)+" Enum Reference"; }
 
     /*! Used for a section containing inherited members */
     virtual QCString trInheritedFrom(const char *members,const char *what)

src/types.h

@@ -54,7 +54,9 @@ enum SrcLangExt
   SrcLangExt_VHDL     = 0x02000,
   SrcLangExt_XML      = 0x04000,
   SrcLangExt_Tcl      = 0x08000,
-  SrcLangExt_Markdown = 0x10000
+  SrcLangExt_Markdown = 0x10000,
+  SrcLangExt_VERILOG = 0x20000
+
 };
 
 /** Grouping info */

src/util.cpp

@@ -5139,7 +5139,7 @@ bool classHasVisibleChildren(ClassDef *cd)
 {
   BaseClassList *bcl;
 
-  if (cd->getLanguage()==SrcLangExt_VHDL) // reverse baseClass/subClass relation
+  if (cd->getLanguage()==SrcLangExt_VERILOG) // reverse baseClass/subClass relation
   {
     if (cd->baseClasses()==0) return FALSE;
     bcl=cd->baseClasses();
@@ -6744,7 +6744,10 @@ g_lang2extMap[] =
   { "vhdl",        "vhdl",          SrcLangExt_VHDL     },
   { "dbusxml",     "dbusxml",       SrcLangExt_XML      },
   { "tcl",         "tcl",           SrcLangExt_Tcl      },
-  { "md",          "md",            SrcLangExt_Markdown },
+  { "ucf",        "v",    SrcLangExt_VERILOG   },
+  { "qsf",        "v",    SrcLangExt_VERILOG   },
+  { "v",        "v",    SrcLangExt_VERILOG    },
+ { "md",          "md",            SrcLangExt_Markdown },
   { 0,             0,              (SrcLangExt)0        }
 };
 
@@ -6835,6 +6838,8 @@ void initDefaultExtensionMapping()
   updateLanguageMapping(".ucf",      "vhdl");
   updateLanguageMapping(".qsf",      "vhdl");
   updateLanguageMapping(".md",       "md");
+  updateLanguageMapping(".v",       "v");
+  updateLanguageMapping(".V",       "v");
   updateLanguageMapping(".markdown", "md");
 
   //updateLanguageMapping(".xml",   "dbusxml");
@@ -7832,6 +7837,7 @@ QCString langToString(SrcLangExt lang)
     case SrcLangExt_Python:   return "Python";
     case SrcLangExt_Fortran:  return "Fortran";
     case SrcLangExt_VHDL:     return "VHDL";
+	case SrcLangExt_VERILOG:     return "VERILOG";
     case SrcLangExt_XML:      return "XML";
     case SrcLangExt_Tcl:      return "Tcl";
     case SrcLangExt_Markdown: return "Markdown";
@@ -7842,7 +7848,7 @@ QCString langToString(SrcLangExt lang)
 /** Returns the scope separator to use given the programming language \a lang */
 QCString getLanguageSpecificSeparator(SrcLangExt lang,bool classScope)
 {
-  if (lang==SrcLangExt_Java || lang==SrcLangExt_CSharp || lang==SrcLangExt_VHDL || lang==SrcLangExt_Python)
+  if (lang==SrcLangExt_Java || lang==SrcLangExt_CSharp || lang==SrcLangExt_VERILOG || lang==SrcLangExt_VHDL || lang==SrcLangExt_Python)
   {
     return ".";
   }

src/vhdlcode.l

@@ -190,8 +190,8 @@ static void startCodeLine()
     //QCString lineNumber,lineAnchor;
     //lineNumber.sprintf("%05d",g_yyLineNr);
     //lineAnchor.sprintf("l%05d",g_yyLineNr);
-    //  if ((g_yyLineNr % 500) == 0) 
-    //         fprintf(stderr,"\n starting Line %d:",g_yyLineNr);
+     // if ((g_yyLineNr % 50) == 0) 
+           //  fprintf(stderr,"\n starting Line %d:",g_yyLineNr);
     Definition *d   = g_sourceFileDef->getSourceDefinition(g_yyLineNr);
     //printf("startCodeLine %d d=%s\n", g_yyLineNr,d ? d->name().data() : "<null>");
     if (!g_includeCodeFragment && d)

src/vhdldocgen.h

@@ -245,8 +245,14 @@ class VhdlDocGen
              cu->spec==VhdlDocGen::ARCHITECTURE ||
              cu->spec==VhdlDocGen::PACKAGE_BODY;
     }
-
-  static void resetCodeVhdlParserState();
+	
+ static bool membersHaveSpecificType(MemberList *ml,uint64 type);
+ static void resetCodeVhdlParserState();
+
+public:
+	 static void writeUCFLink(const MemberDef* mdef,OutputList &ol);
+public:
+	static void startFonts(const QCString& q, const char *keyword,OutputList& ol);
 
   private:
     static void findAllArchitectures(QList<QCString>& ql,const ClassDef *cd);

src/vhdljjparser.cpp

@@ -202,7 +202,6 @@ void VHDLLanguageScanner::parseInput(const char *fileName,const char *fileBuf,En
 
   if (!inLine)
   VhdlParser::mapLibPackage(root);
-
   delete[] lineParse;
   yyFileName.resize(0);
   libUse.clear();

winbuild/Doxygen.sln

 
-Microsoft Visual Studio Solution File, Format Version 10.00
-# Visual C++ Express 2008
-Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Doxygen", "Doxygen.vcproj", "{309C9A4A-94D2-4837-9A11-45B0A6CF35C3}"
-	ProjectSection(ProjectDependencies) = postProject
-		{B6BB4771-8A4E-4656-AC08-1EF8AC182F64} = {B6BB4771-8A4E-4656-AC08-1EF8AC182F64}
-	EndProjectSection
+Microsoft Visual Studio Solution File, Format Version 12.00
+# Visual Studio Express 2012 for Windows Desktop
+Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Doxygen", "Doxygen.vcxproj", "{309C9A4A-94D2-4837-9A11-45B0A6CF35C3}"
 EndProject
-Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "qtools", "qtools.vcproj", "{B6BB4771-8A4E-4656-AC08-1EF8AC182F64}"
+Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "qtools", "qtools.vcxproj", "{B6BB4771-8A4E-4656-AC08-1EF8AC182F64}"
 EndProject
 Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "doxywizard", "Doxywizard.vcproj", "{77C9C2D3-EA3F-3D59-8B4C-0ED852890172}"
 EndProject
 Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "doxysearch", "doxysearch.vcproj", "{F3F3408F-F6F7-46C7-BF1E-1FA056E0AE20}"
 EndProject
-Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "doxyindexer", "doxyindexer.vcproj", "{E543983A-D5BF-4865-B4A1-6D7EF2E1051C}"
-	ProjectSection(ProjectDependencies) = postProject
-		{B6BB4771-8A4E-4656-AC08-1EF8AC182F64} = {B6BB4771-8A4E-4656-AC08-1EF8AC182F64}
-	EndProjectSection
+Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "doxyindexer", "doxyindexer.vcxproj", "{E543983A-D5BF-4865-B4A1-6D7EF2E1051C}"
 EndProject
 Global
 	GlobalSection(SolutionConfigurationPlatforms) = preSolution
@@ -59,7 +53,6 @@ Global
 		{E543983A-D5BF-4865-B4A1-6D7EF2E1051C}.Debug|Win32.ActiveCfg = Debug|Win32
 		{E543983A-D5BF-4865-B4A1-6D7EF2E1051C}.Debug|Win32.Build.0 = Debug|Win32
 		{E543983A-D5BF-4865-B4A1-6D7EF2E1051C}.Debug|x64.ActiveCfg = Debug|x64
-		{E543983A-D5BF-4865-B4A1-6D7EF2E1051C}.Debug|x64.Build.0 = Debug|x64
 		{E543983A-D5BF-4865-B4A1-6D7EF2E1051C}.Release|Win32.ActiveCfg = Release|Win32
 		{E543983A-D5BF-4865-B4A1-6D7EF2E1051C}.Release|Win32.Build.0 = Release|Win32
 		{E543983A-D5BF-4865-B4A1-6D7EF2E1051C}.Release|x64.ActiveCfg = Release|x64