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Elphel
doxverilog
Commits
14f88af1
Commit
14f88af1
authored
Aug 13, 2014
by
Dimitri van Heesch
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Bug 734704 Sigsegv while generating XML output
parent
3b8fea2f
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fileparser.cpp
src/fileparser.cpp
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src/fileparser.cpp
View file @
14f88af1
...
@@ -42,7 +42,7 @@ void FileParser::parseCode(CodeOutputInterface &codeOutIntf,
...
@@ -42,7 +42,7 @@ void FileParser::parseCode(CodeOutputInterface &codeOutIntf,
QCString
lineStr
=
input
.
mid
(
i
,
j
-
i
);
QCString
lineStr
=
input
.
mid
(
i
,
j
-
i
);
codeOutIntf
.
startCodeLine
(
showLineNumbers
);
codeOutIntf
.
startCodeLine
(
showLineNumbers
);
if
(
showLineNumbers
)
codeOutIntf
.
writeLineNumber
(
0
,
0
,
0
,
lineNr
);
if
(
showLineNumbers
)
codeOutIntf
.
writeLineNumber
(
0
,
0
,
0
,
lineNr
);
codeOutIntf
.
codify
(
lineStr
);
if
(
!
lineStr
.
isEmpty
())
codeOutIntf
.
codify
(
lineStr
);
codeOutIntf
.
endCodeLine
();
codeOutIntf
.
endCodeLine
();
lineNr
++
;
lineNr
++
;
i
=
j
+
1
;
i
=
j
+
1
;
...
...
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