Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
D
doxverilog
Project
Project
Details
Activity
Releases
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Commits
Open sidebar
Elphel
doxverilog
Commits
14f88af1
Commit
14f88af1
authored
Aug 13, 2014
by
Dimitri van Heesch
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Bug 734704 Sigsegv while generating XML output
parent
3b8fea2f
Changes
1
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
1 addition
and
1 deletion
+1
-1
fileparser.cpp
src/fileparser.cpp
+1
-1
No files found.
src/fileparser.cpp
View file @
14f88af1
...
...
@@ -42,7 +42,7 @@ void FileParser::parseCode(CodeOutputInterface &codeOutIntf,
QCString
lineStr
=
input
.
mid
(
i
,
j
-
i
);
codeOutIntf
.
startCodeLine
(
showLineNumbers
);
if
(
showLineNumbers
)
codeOutIntf
.
writeLineNumber
(
0
,
0
,
0
,
lineNr
);
codeOutIntf
.
codify
(
lineStr
);
if
(
!
lineStr
.
isEmpty
())
codeOutIntf
.
codify
(
lineStr
);
codeOutIntf
.
endCodeLine
();
lineNr
++
;
i
=
j
+
1
;
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment