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.settings removed unused/unmaintained files
ahci fixing ifdef for debug features
device Added compact input primitives logging and FPGA-based profiling of the host/device communication
generated modified py393sata/ahci_fsm_sequence.py, rebuilt
host fixing ifdef for debug features
includes modified py393sata/ahci_fsm_sequence.py, rebuilt
input_data added missing files
py393sata fixing ifdef for debug features
simcoco Major update
synt Axi registers test synthesis
tb modified py393sata/ahci_fsm_sequence.py, rebuilt
wrapper This version tested with AHCI controller
x393 eliminating use of PLL with GTX
.editor_defines Updated with vdt, adding comments/debug features, implemented required support for CONTp primitive
.gitignore added .project to gitignore
.gitmodules Removed x393 as submodule, copied needed files only (to resolve future recursion)
.project fixing ifdef for debug features
.pydevproject started hardware testing
LICENSE Initial commit
README.md Update README.md
ahci_timing.xdc fixing ifdef for debug features
copy_from_x393.sh Removed x393 as submodule, copied needed files only (to resolve future recursion)
install.sh scriptpath
system_defines.vh fixing ifdef for debug features
tb_ahci_01.sav Added compact input primitives logging and FPGA-based profiling of the host/device communication
tb_top.sav Loading commit data...
tb_top_03.sav Loading commit data...
top.v Loading commit data...
top.xdc Loading commit data...
x393_sata.bit Loading commit data...

x393_sata

SATA controller for x393 camera Board: Zynq 7z30 FPGA: Kintex-7

Install VDT plugin

See instructions on https://github.com/Elphel/vdt-plugin

Clone

git clone https://github.com/Elphel/x393_sata

Working on remote PC

  1. sudo apt-get install ssh-askpass
  2. ssh-copy-id user@ip

Simulation

  • Xilinx unisims license prevents it from re-distribution, so you need to get these files from
  • VDT has a tool (Vivado Tools -> Vivado utilities -> Copy Xilinx Vivado primitives library to the local project) that does this
  • Refresh project (Select it and press F5 key), the files will be re-scanned

Synthesis

  • Add constraints file through Synthesis parameters
  • Bitstream Tool parameters - check Force(overwrite)