Name
Last commit
Last update
.settings started hardware testing
ahci FSM modifications, first time driver recognized disk
ddr3 Few more changes to make the project synth in vdt enviroment
device debugging h2d dma
dma project setup
generated FSM modifications, first time driver recognized disk
helpers FSM modifications, first time driver recognized disk
host debugging with the driver
includes FSM modifications, first time driver recognized disk
input_data added missing files
py393sata fixed dd_read_dma for non-128B aligned CT
simcoco Major update
synt Axi registers test synthesis
tb FSM modifications, first time driver recognized disk
wrapper debugging with the driver
x393 @ 1e167c27 Loading commit data...
.editor_defines Updated with vdt, adding comments/debug features, implemented required support for CONTp primitive
.gitignore added .project to gitignore
.gitmodules VDT-only support added. For non-VDT applications, see non-vdt branch
.project FSM modifications, first time driver recognized disk
.pydevproject started hardware testing
LICENSE Initial commit
README.md Continue on AHCI implementation - processing received FIS
ahci_timing.xdc modifying RX input settings
system_defines.vh more debugging
tb_ahci_01.sav FSM modifications, first time driver recognized disk
tb_top.sav Loading commit data...
tb_top_03.sav Loading commit data...
top.xdc Loading commit data...
top_timing.xdc Loading commit data...

x393_sata

SATA controller for x393 camera Board: Zynq 7z30 FPGA: Kintex-7

Clone

git clone https://github.com/Elphel/x393_sata --recursive

Working on remote PC

  1. sudo apt-get install ssh-askpass
  2. ssh-copy-id user@ip

Swtich between synthesis & simulation

See update below

Edit .editor_defines:

  • simulation: define SIMULATION 1define CHECKERS_ENABLED 1 define OPEN_SOURCE_ONLY 1define PRELOAD_BRAMS
  • synthesis: //define SIMULATION 1 //define CHECKERS_ENABLED 1 //define OPEN_SOURCE_ONLY 1define PRELOAD_BRAMS

Refresh the project and update hierarchy (or rescan)

Update: Not needed anymore with updated VDT plugin - it now calculates closure per-tool and per-top file defines, so .editor_defines is now just for the editor (which branches to parse). No refresh/rescan is required.

Simulation

  • Get unisims library - refresh project files otherwise nothing will work

Synthesis

  • Add constraints file through Synthesis parameters
  • Bitstream Tool parameters - check Force(overwrite)

Current step in try2 branch:

Not yet tested in hardware, started AHCI implementation (currently coded registers and DMA engine, that processes command table/PRD list, Transfers data between clock domains, re-aligns between WORD size granularity, HBA 32-bit data and 64-bit AXI accesses.

Current step in main branch:

Testing basic functionallity of a host.
Trying out pio access.
Fullfilling device-side drivers and monitors via tasks.
Tests are mostly manual, relied on a common sense and waveforms instpection. Still, complatible both with gtx-gpl and unisims/gtx

Going to do afterwards:

Test dma functionallity of the host.
Make cocotb testbench - gtx-gpl only - random payload high-level verification testing purposes.
Create a base of regression tests, containing lower-level tests - both gtx-gpl and unisims/gtx.
Improve an implementation of DMA control module.
Finally decide what to do with a driver and modify application level (actally, write it from scrap) correspodning to driver's interfaces.