eliminated all phy errors, working on remaining in ll

.project

@@ -52,87 +52,87 @@
 		<link>
 			<name>vivado_logs/VivadoBitstream.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160213012011614.log</location>
+			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160214170313831.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOpt.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160213012011614.log</location>
+			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160214170313831.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPhys.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160213012011614.log</location>
+			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160214170313831.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPower.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160213012011614.log</location>
+			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160214170313831.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoPlace.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160213012011614.log</location>
+			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160214170313831.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoRoute.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160213012011614.log</location>
+			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160214170313831.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160213012011614.log</location>
+			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160214170151284.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160213012011614.log</location>
+			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160214170313831.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160213012011614.log</location>
+			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160214170151284.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimingReportImplemented.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160213012011614.log</location>
+			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160214170313831.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160213012011614.log</location>
+			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160214170151284.log</location>
 		</link>
 		<link>
 			<name>vivado_state/x393_sata-opt-phys.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160213012011614.dcp</location>
+			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160214170313831.dcp</location>
 		</link>
 		<link>
 			<name>vivado_state/x393_sata-opt-power.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160213012011614.dcp</location>
+			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160214170313831.dcp</location>
 		</link>
 		<link>
 			<name>vivado_state/x393_sata-opt.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160213012011614.dcp</location>
+			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160214170313831.dcp</location>
 		</link>
 		<link>
 			<name>vivado_state/x393_sata-place.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160213012011614.dcp</location>
+			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160214170313831.dcp</location>
 		</link>
 		<link>
 			<name>vivado_state/x393_sata-route.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160213012011614.dcp</location>
+			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160214170313831.dcp</location>
 		</link>
 		<link>
 			<name>vivado_state/x393_sata-synth.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160213012011614.dcp</location>
+			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160214170151284.dcp</location>
 		</link>
 	</linkedResources>
 </projectDescription>

ahci/ahci_fis_receive.v

@@ -182,10 +182,10 @@ localparam DATA_TYPE_ERR =      3;
     wire                reg_we_w;
 
     reg           [3:0] store_sig;
-    reg           [5:0] reg_ds;
+    reg           [5:0] reg_ds;     //Unused?
     reg           [4:0] reg_ps;
-    reg                 reg_d2h;    
-    reg           [1:0] reg_sdb;    
+    reg                 reg_d2h;    //unused?
+    reg           [1:0] reg_sdb;    //unused?
     reg          [31:2] xfer_cntr_r;
     reg          [31:2] prdbc_r;
     

ahci/ahci_fis_transmit.v

@@ -53,7 +53,7 @@ module  ahci_fis_transmit #(
     input                         xmit_err,     // 
     input                         syncesc_recv, // These two inputs interrupt transmit
     input                         xrdy_collision, 
-    output                 [ 2:0] dx_err,       // bit 0 - syncesc_recv, 1 - xmit_err, 2 - collision  (valid @ xmit_err and later, reset by new command)
+    output                 [ 2:0] dx_err,       // bit 0 - syncesc_recv, 1 - R_ERR (was xmit_err), 2 - collision  (valid @ xmit_err and later, reset by new command)
     
     output                 [15:0] ch_prdtl,    // Physical region descriptor table length (in entries, 0 is 0)
     output                        ch_c,        // Clear busy upon R_OK for this FIS

ahci/ahci_fsm.v

@@ -225,7 +225,7 @@ module  ahci_fsm
 //    output                        dmaCntrZero, // DMA counter is zero - would be a duplicate to the one in receive module and dwords_sent output
 //    input                         syncesc_recv, // These two inputs interrupt transmit
 //    input                         xmit_err,     // 
-    input                  [ 2:0] dx_err,       // bit 0 - syncesc_recv, 1 - xmit_err, 2 - X_RDY/X_RDY collision (valid @ xmit_err and later, reset by new command)
+    input                  [ 2:0] dx_err,       // bit 0 - syncesc_recv, 1 - R_ERR (was xmit_err), 2 - X_RDY/X_RDY collision (valid @ xmit_err and later, reset by new command)
     
 ///    input                  [15:0] ch_prdtl,    // Physical region descriptor table length (in entries, 0 is 0)
     input                         ch_c,        // Clear busy upon R_OK for this FIS

ahci/ahci_sata_layers.v

@@ -27,7 +27,11 @@ module  ahci_sata_layers #(
     parameter DATASCOPE_POST_MEAS =  16, // number of measurements to perform after event
 `endif        
     parameter BITS_TO_START_XMIT =    6,   // wait H2D FIFO to have 1 << BITS_TO_START_XMIT to start FIS transmission (or all FIS fits)
-    parameter  DATA_BYTE_WIDTH =      4
+    parameter DATA_BYTE_WIDTH =       4,
+    parameter ELASTIC_DEPTH =         4, //5, With 4/7 got infrequent overflows!
+    parameter ELASTIC_OFFSET =        7, //  5 //10
+    parameter FREQ_METER_WIDTH =     12
+    
 )(
     input              exrst,   // master reset that resets PLL and GTX
     input              reliable_clk, // use aclk that runs independently of the GTX
@@ -114,9 +118,10 @@ module  ahci_sata_layers #(
     output              drp_rdy,
     output       [15:0] drp_do ,
 `endif    
-    
+    output  [FREQ_METER_WIDTH - 1:0] xclk_period,      // relative (to 2*clk) xclk period
     output       [31:0] debug_phy,
-    output       [31:0] debug_link
+    output       [31:0] debug_link,
+    input               hclk // just for testing
     
     
 );
@@ -202,11 +207,11 @@ module  ahci_sata_layers #(
 
     wire                           rxelsfull; 
     wire                           rxelsempty; 
-
+    wire                           xclk;             // output receive clock, just to measure frequency
+//    wire  [FREQ_METER_WIDTH - 1:0] xclk_period;      // relative (to 2*clk) xclk period
     
     wire debug_detected_alignp; // oob detects ALIGNp, but not the link layer
-    
-    
+    wire                    [31:0] debug_phy0;
 //    assign debug_sata = {link_established, phy_ready, debug_phy[29:16],debug_link[15:0]}; // 
 //    assign debug_sata = debug_link[31:0]; // 
 ///    assign debug_sata = debug_phy;
@@ -248,6 +253,24 @@ module  ahci_sata_layers #(
     assign serr_EM = phy_ready && (0);   // RWC: Communication between the device and host was lost but re-established
     assign serr_EI = phy_ready && (0);   // RWC: Recovered Data integrity Error
     
+    reg [1:0] debug_last_d2h_type_in;
+    always @ (posedge clk) begin
+        if (d2h_fifo_wr) debug_last_d2h_type_in<= d2h_type_in;
+    end
+    assign debug_phy = {h2d_type_out[1:0],h2d_type[1:0],
+                        ll_h2d_last,d2h_valid,  d2h_type[1:0],
+                        debug_last_d2h_type_in, d2h_type_in[1:0],
+                        debug_phy0[19:0]};
+    
+/*
+// Data/type FIFO, device -> host
+    output      [31:0] d2h_data,         // FIFO input  data
+    output      [ 1:0] d2h_mask,     // set to 2'b11
+    output      [ 1:0] d2h_type,    // 0 - data, 1 - FIS head, 2 - R_OK, 3 - R_ERR (last two - after data, so ignore data with R_OK/R_ERR)
+    output             d2h_valid,  // Data available from the transport layer in FIFO                
+    output             d2h_many,    // Multiple DWORDs available from the transport layer in FIFO           
+    input              d2h_ready,   // This module or DMA consumes DWORD
+*/    
 //        .comreset_send   (comreset_send),     // input
 //        .cominit_got     (cominit_got),       // output wire 
 //        .comwake_got     (serr_DW),            // output wire 
@@ -338,7 +361,9 @@ module  ahci_sata_layers #(
         .DATASCOPE_START_BIT (DATASCOPE_START_BIT),
         .DATASCOPE_POST_MEAS (DATASCOPE_POST_MEAS),
 `endif    
-        .DATA_BYTE_WIDTH(4)
+        .DATA_BYTE_WIDTH     (DATA_BYTE_WIDTH),
+        .ELASTIC_DEPTH       (ELASTIC_DEPTH),
+        .ELASTIC_OFFSET      (ELASTIC_OFFSET)
     ) phy (
         .extrst              (exrst),             // input wire 
         .clk                 (clk),               // output wire 
@@ -366,15 +391,16 @@ module  ahci_sata_layers #(
         .rxelsempty          (rxelsempty),        // output wire 
 
         .cplllock_debug      (),
-        .usrpll_locked_debug(),
+        .usrpll_locked_debug (),
         .re_aligned          (serr_DS),           // output reg 
+        .xclk                (xclk),             // output receive clock, just to measure frequency
 
 `ifdef USE_DATASCOPE
         .datascope_clk     (datascope_clk),     // output
         .datascope_waddr   (datascope_waddr),   // output[9:0] 
         .datascope_we      (datascope_we),      // output
         .datascope_di      (datascope_di),      // output[31:0] 
-        .datascope_trig    (ll_frame_ackn),     // input datascope external trigger
+        .datascope_trig    (ll_incom_invalidate), // ll_frame_ackn),     // input datascope external trigger
 `endif        
 
 `ifdef USE_DRP
@@ -387,7 +413,7 @@ module  ahci_sata_layers #(
         .drp_rdy           (drp_rdy),           // output
         .drp_do            (drp_do),            // output[15:0] 
 `endif 
-        .debug_sata      (debug_phy)  
+        .debug_sata      (debug_phy0)  
         ,.debug_detected_alignp(debug_detected_alignp)
     );
 
@@ -459,5 +485,15 @@ module  ahci_sata_layers #(
         .data_in  ({d2h_type_in, ll_d2h_mask_out, ll_d2h_data_out}) // input[35:0] 
     );
 
+    freq_meter #(
+        .WIDTH    (FREQ_METER_WIDTH),
+        .PRESCALE (1)
+    ) freq_meter_i (
+        .rst   (rst),        // input
+        .clk   (clk),        // input
+        .xclk  (xclk), // hclk), //xclk),       // input
+        .dout  (xclk_period) // output[11:0] reg 
+    );
+
 endmodule
 

ahci/ahci_top.v

@@ -27,7 +27,9 @@ module  ahci_top#(
     parameter READ_CT_LATENCY =       2, // 0 if  ct_rdata is available with reg_re/reg_addr, 2 with re/regen
     parameter ADDRESS_BITS =         10, // number of memory address bits - now fixed. Low half - RO/RW/RWC,RW1 (2-cycle write), 2-nd just RW (single-cycle)
     parameter HBA_RESET_BITS =        9, // duration of HBA reset in aclk periods (9: ~10usec)
-    parameter RESET_TO_FIRST_ACCESS = 1 // keep port reset until first R/W any register by software
+    parameter RESET_TO_FIRST_ACCESS = 1, // keep port reset until first R/W any register by software
+    parameter FREQ_METER_WIDTH =     12
+    
 )(
     input             aclk,    // clock - should be buffered
     input             arst,    // @aclk sync reset, active high
@@ -200,7 +202,7 @@ module  ahci_top#(
     input                     drp_rdy,
     input              [15:0] drp_do, 
 `endif    
-    
+    input  [FREQ_METER_WIDTH - 1:0] xclk_period,      // relative (to 2*clk) xclk period
     input       [31:0] debug_in_phy,
     input       [31:0] debug_in_link
     
@@ -379,7 +381,7 @@ module  ahci_top#(
     wire                    fsnd_clearCmdToIssue; // From CFIS:SUCCESS 
     // State variables fsm <- ahc_fis_transmit 
     wire                    fsnd_pCmdToIssue; // AHCI port variable
-    wire             [ 2:0] fsnd_dx_err;       // bit 0 - syncesc_recv, 1 - xmit_err  2 - X-RDY/X_RDY collision (valid @ xmit_err and later, reset by new command)
+    wire             [ 2:0] fsnd_dx_err;       // bit 0 - syncesc_recv, 1 - R_ERR (was xmit_err)  2 - X-RDY/X_RDY collision (valid @ xmit_err and later, reset by new command)
     wire                    fsnd_ch_c;        // Clear busy upon R_OK for this FIS
     wire                    fsnd_ch_b;        // Built-in self test command
     wire                    fsnd_ch_r;        // reset - may need to send SYNC escape before this command
@@ -649,7 +651,7 @@ module  ahci_top#(
 ///        .xmit_busy       (fsnd_busy),          // input
         .clearCmdToIssue          (fsnd_clearCmdToIssue),// output // From CFIS:SUCCESS 
         .pCmdToIssue              (fsnd_pCmdToIssue),   // input
-        .dx_err                   (fsnd_dx_err),        // input[1:0] 
+        .dx_err                   (fsnd_dx_err),        // input[2:0] 
 ///        .ch_prdtl        (prdtl),              // input[15:0] 
         .ch_c                     (fsnd_ch_c),          // input
         .ch_b                     (fsnd_ch_b),          // input
@@ -723,10 +725,18 @@ module  ahci_top#(
         .was_hba_rst      (was_hba_rst),     // output 
         .was_port_rst     (was_port_rst),    // output 
         .debug_in0        (debug_dma),       // input[31:0]
-        .debug_in1        (debug_dma1),      // debug_in_link),   // input[31:0]
+//        .debug_in1        ({xclk_period[7:0], // lower 8 bits of 12-bit value. Same frequency would be 0x800 (msb opposite to 3 next bits)
+//                            debug_dma1[23:0]}),      // debug_in_link),   // input[31:0]
+        .debug_in1        ({2'b0, 
+                            debug_in_link[13:8],
+                            debug_dma1[23:0]}),      // debug_in_link),   // input[31:0]
         .debug_in2        (debug_in_phy),    // input[31:0]     // debug from phy/link
 //        .debug_in3        ({22'b0, last_jump_addr[9:0]}) // input[31:0]// Last jump address in the AHDCI sequencer
-        .debug_in3        ({3'b0, debug_in_link[4:0], 14'b0,last_jump_addr[9:0]}) // input[31:0]// Last jump address in the AHDCI sequencer
+        .debug_in3        ({3'b0, debug_in_link[4:0],
+                            frcv_busy,frcv_ok, // 2'b0,
+                             datascope_waddr[9:0],
+                            frcv_err,frcv_ferr, // 2'b0,
+                             last_jump_addr[9:0]}) // input[31:0]// Last jump address in the AHDCI sequencer
         
 `ifdef USE_DRP
        ,.drp_en           (drp_en),          // output reg 
@@ -1083,8 +1093,10 @@ wire [9:0] xmit_dbg_01;
 //    assign datascope_we = (datascope_run[0] && h2d_valid && h2d_ready) || (datascope_run == 2);
 //    assign datascope_di = datascope_run[0]? {h2d_data[31:0]} : {16'hffff,{16-ADDRESS_BITS{1'b0}},datascope_waddr_r};
 
-    assign datascope_we = (datascope_run[0] && h2d_valid && h2d_ready) || (datascope_run == 2) || d2h_ready;
-    assign datascope_di = d2h_ready? {d2h_type, d2h_data[29:0]}:(datascope_run[0]? {h2d_data[31:0]} : {16'hffff,{16-ADDRESS_BITS{1'b0}},datascope_waddr_r});
+//    assign datascope_we = (datascope_run[0] && h2d_valid && h2d_ready) || (datascope_run == 2) || d2h_ready;
+//    assign datascope_di = d2h_ready? {d2h_type, d2h_data[29:0]}:(datascope_run[0]? {h2d_data[31:0]} : {16'hffff,{16-ADDRESS_BITS{1'b0}},datascope_waddr_r});
+    assign datascope_we = (datascope_run[0] && h2d_valid && h2d_ready) || fsnd_done || d2h_ready;
+    assign datascope_di = d2h_ready? {d2h_type, d2h_data[29:0]}:(datascope_run[0]? {h2d_data[31:0]} : {13'hffff,fsnd_dx_err[2:0],{16-ADDRESS_BITS{1'b0}},datascope_waddr_r});
 ///    assign datascope_we = |datascope_run;
 /*
     assign datascope_di = datascope_run[0]? {h2d_type,            // 2 bits

ahci/freq_meter.v

+/*******************************************************************************
+ * Module: freq_meter
+ * Date:2016-02-13  
+ * Author: andrey     
+ * Description: Measure device clock frequency to set the local clock
+ *
+ * Copyright (c) 2016 Elphel, Inc .
+ * freq_meter.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  freq_meter.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  freq_meter#(
+    parameter WIDTH =    12, // width of the result
+    parameter PRESCALE = 1 // 0 same frequency, +1 - xclk is tvice faster, -1 - twice slower
+)(
+    input                     rst,
+    input                     clk,
+    input                    xclk,
+    output reg [WIDTH - 1:0] dout
+);
+    localparam TIMER_WIDTH = WIDTH - PRESCALE;
+    reg [TIMER_WIDTH - 1 :0] timer;
+    reg       [WIDTH - 1 :0] counter;
+    
+    wire                     restart;
+    reg                [3:0] run_xclk;
+    
+    always @ (posedge clk) begin
+        if      (rst || restart)          timer <= 0;
+        else if (!timer[TIMER_WIDTH - 1]) timer <= timer + 1;
+        
+        if (restart) dout <= counter; // it is stopped before copying
+        
+    end
+    always @ (posedge xclk) begin
+        run_xclk <= {run_xclk[2:0], ~timer[TIMER_WIDTH - 1] & ~rst};
+        
+        if      (run_xclk[2]) counter <= counter + 1;
+        else if (run_xclk[1]) counter <= 0;
+        
+    end
+    
+    pulse_cross_clock #(
+        .EXTRA_DLY(0)
+    ) xclk2clk_i (
+        .rst       (rst),                         // input
+        .src_clk   (xclk),                        // input
+        .dst_clk   (clk),                         // input
+        .in_pulse  (!run_xclk[2] && run_xclk[3]), // input
+        .out_pulse (restart),                     // output
+        .busy      ()                             // output
+    );
+    
+    
+endmodule
+

ahci/sata_ahci_top.v

@@ -46,7 +46,12 @@
 `endif
     
     parameter HBA_RESET_BITS =        9, // duration of HBA reset in aclk periods (9: ~10usec)
-    parameter RESET_TO_FIRST_ACCESS = 1 // keep port reset until first R/W any register by software
+    parameter RESET_TO_FIRST_ACCESS = 1, // keep port reset until first R/W any register by software
+    parameter BITS_TO_START_XMIT =    6,   // wait H2D FIFO to have 1 << BITS_TO_START_XMIT to start FIS transmission (or all FIS fits)
+    parameter DATA_BYTE_WIDTH =       4,
+    parameter ELASTIC_DEPTH =         4, // 4, //5, With 4/7 got infrequent overflows!
+    parameter ELASTIC_OFFSET =        7, //  5 //10
+    parameter FREQ_METER_WIDTH =     16
  )(
     output  wire                sata_clk,
     output  wire                sata_rst,
@@ -228,6 +233,8 @@
     
     reg          [2:0] nhrst_r;
     wire               hrst = !nhrst_r[2];
+    
+    wire [FREQ_METER_WIDTH-1:0] xclk_period;
 `ifdef USE_DATASCOPE
 // Datascope interface (write to memory that can be software-read)
     wire                     datascope_clk;
@@ -261,7 +268,8 @@
 //        .READ_CT_LATENCY       (READ_CT_LATENCY),
         .ADDRESS_BITS          (ADDRESS_BITS),
         .HBA_RESET_BITS        (HBA_RESET_BITS),
-        .RESET_TO_FIRST_ACCESS (RESET_TO_FIRST_ACCESS)
+        .RESET_TO_FIRST_ACCESS (RESET_TO_FIRST_ACCESS),
+        .FREQ_METER_WIDTH      (FREQ_METER_WIDTH)
     ) ahci_top_i (
         .aclk              (ACLK),              // input
         .arst              (arst),              // input
@@ -404,6 +412,7 @@
         .drp_rdy          (drp_rdy),            // input
         .drp_do           (drp_do),             // input[15:0] 
 `endif   
+        .xclk_period       (xclk_period),       // input[11:0] 
         .debug_in_phy      (debug_phy),         // input[31:0]
         .debug_in_link     (debug_link)         // input[31:0]
     );
@@ -414,8 +423,11 @@
         .DATASCOPE_START_BIT (DATASCOPE_START_BIT), // bit of DRP "other_control" to start recording after 0->1 (needs DRP)
         .DATASCOPE_POST_MEAS (DATASCOPE_POST_MEAS), // number of measurements to perform after event
 `endif    
-        .BITS_TO_START_XMIT (6),
-        .DATA_BYTE_WIDTH(4)
+        .BITS_TO_START_XMIT  (BITS_TO_START_XMIT),
+        .DATA_BYTE_WIDTH     (DATA_BYTE_WIDTH),
+        .ELASTIC_DEPTH       (ELASTIC_DEPTH),
+        .ELASTIC_OFFSET      (ELASTIC_OFFSET),
+        .FREQ_METER_WIDTH    (FREQ_METER_WIDTH)
     ) ahci_sata_layers_i (
         .exrst             (exrst),             // input
         .reliable_clk      (reliable_clk),      // input
@@ -485,8 +497,10 @@
         .drp_rdy           (drp_rdy),           // output
         .drp_do            (drp_do),            // output[15:0] 
 `endif 
+        .xclk_period       (xclk_period),       // output[11:0] 
         .debug_phy         (debug_phy),         // output[31:0]
         .debug_link        (debug_link)         // output[31:0]
+       ,.hclk(hclk)
     );
 
 

generated/action_decoder.v

 /*******************************************************************************
  * Module: action_decoder
- * Date:2016-02-07  
+ * Date:2016-02-13  
  * Author: auto-generated file, see ahci_fsm_sequence.py
  * Description: Decode sequencer code to 1-hot actions
  *******************************************************************************/

generated/condition_mux.v

 /*******************************************************************************
  * Module: condition_mux
- * Date:2016-02-07  
+ * Date:2016-02-13  
  * Author: auto-generated file, see ahci_fsm_sequence.py
  * Description: Select condition
  *******************************************************************************/

helpers/ahci_fsm_sequence.py

@@ -240,8 +240,11 @@ sequence = [{LBL:'POR',      ADDR: 0x0, ACT: NOP},
             {IF: 'X_RDY_COLLISION',     GOTO:'P:Idle'},              # 2. x_rdy_collision_pend
             {IF: 'SYNCESC_ERR',         GOTO:'ERR:SyncEscapeRecv'},  # 4. dx_err[0] (reset by new command)
             
-            {IF: 'FIS_OK',              GOTO:'CFIS:Success'},        # 5. fis_ok
-            {                           GOTO:'ERR:Non-Fatal'},       # 6
+#            {IF: 'FIS_OK',              GOTO:'CFIS:Success'},       # 5. fis_ok - wrong, it was for received FISes
+#            {                           GOTO:'ERR:Non-Fatal'},      # 6
+            {IF: 'TX_ERR',              GOTO:'ERR:Non-Fatal'},       # dx_err[1] - R_ERR received - non-fatal, retransmit
+            {                           GOTO:'CFIS:Success'},        # No errors, R_OK received            
+            
                         
             {LBL:'CFIS:Success',        ACT: 'CLEAR_CMD_TO_ISSUE'},  # clearCmdToIssue
             {IF: 'CTBA_B',              GOTO:'BIST:TestOngoing'},    # 1. ch_b

host/elastic1632.v

@@ -58,27 +58,34 @@ reg                   msb_in_r;      // input contains MSB
 reg                   inc_waddr;
 reg    [DEPTH_LOG2:0] waddr;
 wire [DEPTH_LOG2-1:0] waddr_minus = waddr[DEPTH_LOG2-1:0] - 1;
-//reg    [DEPTH_LOG2:0] raddr;
 wire   [DEPTH_LOG2:0] raddr_w;
 reg    [DEPTH_LOG2:0] raddr_r;
 reg            [44:0] fifo_ram    [0: FIFO_DEPTH -1];
 reg             [0:0] prealign_ram[0: FIFO_DEPTH -1];
 reg  [FIFO_DEPTH-1:0] fill;
 wire [FIFO_DEPTH-1:0] fill_out;
+wire [FIFO_DEPTH-1:0] fill_out_more; // "pessimistic"
+wire [FIFO_DEPTH-1:0] fill_out_less; // "optimistic"
 wire [FIFO_DEPTH-1:0] fill_1;
 reg             [2:0] aligned_rclk;
-reg             [1:0] dav_rclk;
-wire                  skip_rclk;
-wire                  add_rclk;
-//wire           [44:0] rdata = fifo_ram[raddr[DEPTH_LOG2-1:0]];
+reg             [1:0] dav_rclk;      // FIFO has more than level
+reg             [1:0] dav_rclk_more; // FIFO has more than (level + 1)
+reg             [1:0] dav_rclk_less; // FIFO has more than (level - 1)
+wire                  skip_rclk;  // skip 1 align primitive
+wire                  skip_rclk2; // skip 2 align primitives
+//wire                  add_rclk;   // insert 1 align primitive (to add2 - do this twice)
+//wire                  add_rclk2;  // skip 2 ALIGNp (just twice using add_rclk || add_rclk2_r
+reg             [1:0] add_rclk_r;                   
 reg            [44:0] rdata_r;
-//wire                  align_out = rdata[44];
 wire                  align_out = rdata_r[44];
-//wire                  pre_align_out = prealign_ram[raddr[DEPTH_LOG2-1:0]];
 reg                   pre_align_out_r;
-reg                   align_out_r;
+// reg                   align_out_r;
 reg             [2:0] correct_r;
-wire                  correct = align_out && (!align_out_r || (pre_align_out_r && !correct_r[2]));
+//wire                  correct = align_out && (!align_out_r || (pre_align_out_r && !correct_r[2]));
+wire                  correct_stream = align_out && pre_align_out_r && !correct_r[2]; // correct during continuous align steram - by 1 only
+wire                  correct_first = pre_align_out_r && !align_out; // next will be ALIGNp, may skip both
+
+wire                  correct = correct_stream || correct_first;
 
 reg             [1:0] full_0; // full at waddr = waddr
 reg             [1:0] full_1; // full at waddr = raddr+1
@@ -89,18 +96,27 @@ wire is_alignp_w = ({data_in,       data_in_r} ==       ALIGN_PRIM) &&
                    ({charisk_in,    charisk_in_r} ==    4'h1) &&
                    ({notintable_in, notintable_in_r} == 0) &&
                    ({disperror_in,  disperror_in_r} ==  0);
+`ifdef SIMULATION
+    wire  [DEPTH_LOG2:0] dbg_diff = waddr-raddr_r; // SuppressThisWarning VEditor Not used, just for viewing in simulator
+    wire                 dbg_dav1 = dav_rclk[1];   // SuppressThisWarning VEditor Not used, just for viewing in simulator
+    wire                 dbg_full0 = full_0[1];    // SuppressThisWarning VEditor Not used, just for viewing in simulator
+    wire                 dbg_full1 = full_1[1];    // SuppressThisWarning VEditor Not used, just for viewing in simulator
+    reg          [31:0]  dbg_di;                   // SuppressThisWarning VEditor Not used, just for viewing in simulator
+    
+    always @(posedge wclk) begin
+        if (msb_in_r) dbg_di<= {data_in,data_in_r};
+    end
+`endif
 
-wire  [DEPTH_LOG2:0] dbg_diff = waddr-raddr_r;
-wire                 dbg_dav1 = dav_rclk[1];
-wire                 dbg_full0 = full_0[1];
-wire                 dbg_full1 = full_1[1];
 
 genvar ii;
 generate
     for (ii = 0; ii < FIFO_DEPTH; ii = ii + 1)
     begin: gen_fill_out
-        assign fill_out[ii] =            fill[(ii + CORR_OFFSET) & (FIFO_DEPTH-1)] ^ ((ii + CORR_OFFSET)>=FIFO_DEPTH);
-        assign fill_1[ii] =              fill[(ii + 1) & (FIFO_DEPTH-1)] ^ ((ii + 1)>=FIFO_DEPTH);
+        assign fill_out[ii] =            fill[(ii + CORR_OFFSET    ) & (FIFO_DEPTH - 1)] ^ ((ii + CORR_OFFSET    ) >= FIFO_DEPTH);
+        assign fill_out_more[ii] =       fill[(ii + CORR_OFFSET + 1) & (FIFO_DEPTH - 1)] ^ ((ii + CORR_OFFSET + 1) >= FIFO_DEPTH);
+        assign fill_out_less[ii] =       fill[(ii + CORR_OFFSET - 1) & (FIFO_DEPTH - 1)] ^ ((ii + CORR_OFFSET - 1) >= FIFO_DEPTH);
+        assign fill_1[ii] =              fill[(ii + 1) & (FIFO_DEPTH - 1)] ^ ((ii + 1) >= FIFO_DEPTH);
     end
 endgenerate
                    
@@ -133,16 +149,14 @@ always @(posedge wclk) begin
     if (!aligned32_in_r)  fill <= 0;
     else if (msb_in_r)    fill <={fill[FIFO_DEPTH-2:0],~waddr[DEPTH_LOG2]};
     
-    
 end
 
 // FIFO read clock domain - system synchronous, 75MHz for SATA2
     localparam [DEPTH_LOG2:0] SIZED0 = 0;
     localparam [DEPTH_LOG2:0] SIZED1 = 1;
     localparam [DEPTH_LOG2:0] SIZED2 = 2;
-//    assign raddr_w = aligned_rclk[1]? ( raddr_r + (add_rclk? 0 : (skip_rclk ? 2 : 1))) : 0;
-    assign raddr_w = aligned_rclk[1]? ( raddr_r + (add_rclk? SIZED0 : (skip_rclk ? SIZED2 : SIZED1))) : SIZED0;
-
+    localparam [DEPTH_LOG2:0] SIZED3 = 3;
+    assign raddr_w = aligned_rclk[1]? ( raddr_r + (add_rclk_r[0]? SIZED0 : (skip_rclk ? (skip_rclk2 ? SIZED3 : SIZED2) : SIZED1))) : SIZED0;
 
 always @(posedge rclk) begin
 
@@ -156,35 +170,46 @@ always @(posedge rclk) begin
     else                 aligned_rclk <= {aligned_rclk[1:0],fill[OFFSET-2] | aligned_rclk[0]};
 
     if (!aligned32_in_r) dav_rclk <= 0;
-//    else                 dav_rclk <= {dav_rclk[0],fill_out[raddr[DEPTH_LOG2-1:0]] ^ raddr[DEPTH_LOG2]};
     else                 dav_rclk <= {dav_rclk[0],fill_out[raddr_r[DEPTH_LOG2-1:0]] ^ raddr_r[DEPTH_LOG2]};
 
+    if (!aligned32_in_r) dav_rclk_more <= 0;
+    else                 dav_rclk_more <= {dav_rclk_more[0],fill_out_more[raddr_r[DEPTH_LOG2-1:0]] ^ raddr_r[DEPTH_LOG2]};
+
+    if (!aligned32_in_r) dav_rclk_less <= 0;
+    else                 dav_rclk_less <= {dav_rclk_less[0],fill_out_less[raddr_r[DEPTH_LOG2-1:0]] ^ raddr_r[DEPTH_LOG2]};
+
+    
     if (!aligned32_in_r) full_0 <= 1;
-//    else                 full_0 <= {full_0[0], fill[raddr[DEPTH_LOG2-1:0]] ^ raddr[DEPTH_LOG2]};
     else                 full_0 <= {full_0[0], fill[raddr_r[DEPTH_LOG2-1:0]] ^ raddr_r[DEPTH_LOG2]};
 
     if (!aligned32_in_r) full_1 <= 1;
-//    else                 full_1 <= {full_1[0], fill_1[raddr[DEPTH_LOG2-1:0]] ^ raddr[DEPTH_LOG2]};
     else                 full_1 <= {full_1[0], fill_1[raddr_r[DEPTH_LOG2-1:0]] ^ raddr_r[DEPTH_LOG2]};
     
-
-//    if (!aligned_rclk[1]) raddr <=0;
-//    else if (!add_rclk)   raddr <= raddr + (skip_rclk ? 2 : 1);
-
     disperror_out <=  rdata_r[43:40];
     notintable_out <= rdata_r[39:36];
     charisk_out <=    rdata_r[35:32];
     data_out <=       rdata_r[31: 0];
     
-    align_out_r <= align_out;
+//    align_out_r <= align_out;
 
     if (correct || !aligned_rclk) correct_r <= ~0;
     else correct_r <= correct_r << 1;
 
+//    add_rclk2_r <=add_rclk2;
+    if      (correct_first)  add_rclk_r <= {~dav_rclk_less[1], ~dav_rclk[1]};
+    else if (correct_stream) add_rclk_r <= {1'b0,              ~dav_rclk[1]};
+    else                     add_rclk_r <= add_rclk_r >> 1; 
+    
 end
 
+//assign skip_rclk = correct &&  dav_rclk[1];
+//assign add_rclk =  correct && !dav_rclk[1];
 assign skip_rclk =  correct &&  dav_rclk[1];
-assign add_rclk =  correct && !dav_rclk[1];
+assign skip_rclk2 = correct_first &&  dav_rclk_more[1];
+
+//assign add_rclk =   correct && !dav_rclk[1];
+//assign add_rclk2 =  correct_first && !dav_rclk_less[1];
+
 assign isaligned_out = aligned_rclk[2];
 assign full =  aligned_rclk &&  full_1[1] && !full_0[1];
 assign empty = aligned_rclk && !full_1[1] &&  full_0[1];

host/gtx_8x10enc.v

@@ -139,6 +139,7 @@ always @ (posedge clk)
     else begin
         // got xxxx or 0000, both cases tell us addresses were bad
         $display("Error in %m: bad incoming data: 1) K = %h, Data = %h 2) K = %h, Data = %h", addr0_rr[8], addr0_rr[7:0], addr1_rr[8], addr1_rr[7:0]);
+        repeat (10) @(posedge clk);
         $finish;
     end
 `endif // CHECKERS_ENABLED

host/gtx_wrap.v

@@ -51,7 +51,7 @@ module gtx_wrap #(
     parameter RXDFELPMRESET_TIME  = 7'hf,
     parameter RXISCANRESET_TIME   = 5'h1,
     
-    parameter ELASTIC_DEPTH = 4, //5,
+    parameter ELASTIC_DEPTH =       4, //5, With 4/7 got infrequent overflows!
     parameter ELASTIC_OFFSET =      7 //  5 //10
 )
 (
@@ -104,7 +104,10 @@ module gtx_wrap #(
     output  wire    dbg_rxcdrlock,
     output  wire    dbg_rxdlysresetdone,
     
-    output wire [1:0] txbufstatus
+    output wire [1:0] txbufstatus,
+    
+    output          xclk   //  just to measure frequency to set the local clock
+    
 `ifdef USE_DATASCOPE
 // Datascope interface (write to memory that can be software-read)
    ,output                    datascope_clk,
@@ -385,7 +388,7 @@ gtx_8x10enc gtx_8x10enc(
  * RX PCS part: comma detect + align module, 10/8 decoder, elastic buffer, interface resynchronisation
  * all modules before elastic buffer shall work on a restored clock - xclk
  */
-wire    xclk;
+// wire    xclk; make it output to measure frequency
 // assuming GTX interface width = 20 bits
 // comma aligner
 wire    [19:0]  rxdata_comma_out;

host/sata_phy.v

@@ -39,7 +39,9 @@ module sata_phy #(
     parameter DATASCOPE_START_BIT =  14, // bit of DRP "other_control" to start recording after 0->1 (needs DRP)
     parameter DATASCOPE_POST_MEAS =  16, // number of measurements to perform after event
 `endif        
-    parameter   DATA_BYTE_WIDTH = 4
+    parameter   DATA_BYTE_WIDTH =     4,
+    parameter ELASTIC_DEPTH =         4, //5, With 4/7 got infrequent overflows!
+    parameter ELASTIC_OFFSET =        7 //  5 //10
 )
 (
     // initial reset, resets PLL. After pll is locked, an internal sata reset is generated.
@@ -88,6 +90,7 @@ module sata_phy #(
     output                                      cplllock_debug,
     output                                      usrpll_locked_debug,
     output                                      re_aligned,      // re-aligned after alignment loss
+    output                                      xclk,            //  just to measure frequency to set the local clock
     
 `ifdef USE_DATASCOPE
 // Datascope interface (write to memory that can be software-read)
@@ -488,7 +491,10 @@ gtx_wrap #(
     .RXCDRPHRESET_TIME      (RXCDRPHRESET_TIME),
     .RXCDRFREQRESET_TIME    (RXCDRFREQRESET_TIME),
     .RXDFELPMRESET_TIME     (RXDFELPMRESET_TIME),
-    .RXISCANRESET_TIME      (RXISCANRESET_TIME)
+    .RXISCANRESET_TIME      (RXISCANRESET_TIME),
+    .ELASTIC_DEPTH          (ELASTIC_DEPTH), // with 4/7 infrequent full !
+    .ELASTIC_OFFSET         (ELASTIC_OFFSET)
+    
 )
 gtx_wrap
 (
@@ -537,7 +543,8 @@ gtx_wrap
     .dbg_rx_clocks_aligned(dbg_rx_clocks_aligned),
     .dbg_rxcdrlock        (dbg_rxcdrlock)    ,
     .dbg_rxdlysresetdone(dbg_rxdlysresetdone),
-    .txbufstatus        (txbufstatus[1:0])
+    .txbufstatus        (txbufstatus[1:0]),
+    .xclk               (xclk)             // output receive clock, just to measure frequency
 `ifdef USE_DATASCOPE
        ,.datascope_clk     (datascope_clk),     // output
         .datascope_waddr   (datascope_waddr),   // output[9:0] 
@@ -671,9 +678,9 @@ assign debug_sata[23:20] = debug_cntr4;
 //assign debug_sata = {8'b0, dbg_clk_align_cntr, 1'b0, dbg_rxdlysresetdone, rxelecidle, dbg_rxcdrlock, rxelsfull, rxelsempty, dbg_rxphaligndone, dbg_rx_clocks_aligned};
 `ifdef USE_DATASCOPE
     assign debug_sata = {txbufstatus[1:0], rxelecidle, dbg_rxcdrlock, rxelsfull, rxelsempty, dbg_rxphaligndone, dbg_rx_clocks_aligned,
-                         error_count,
+                         error_count[11:0],
                          2'b0,
-                         datascope_waddr};
+                         datascope_waddr[9:0]};
 `else
     assign debug_sata = {8'b0, dbg_clk_align_cntr, txbufstatus[1:0], rxelecidle, dbg_rxcdrlock, rxelsfull, rxelsempty, dbg_rxphaligndone, dbg_rx_clocks_aligned};
 `endif

includes/ahxi_fsm_code.vh

@@ -4,8 +4,8 @@
 , .INIT_03 (256'h845284BE44374C682C4214190012003900880018000A02080022001901020090)
 , .INIT_04 (256'h00190110003901100019144601020030020202040039B07D707A041000398C6B)
 , .INIT_05 (256'h64540C2504580000004E24FB250200C0004C24FB250200C0005C000000390000)
-, .INIT_06 (256'hA47150F8903900A00104006B0202005000E2A89368F018E918CB98A758D73882)
-, .INIT_07 (256'h0060003900000039B07D00000050004400220039B07D707A307730F001080102)
+, .INIT_06 (256'hD10250F8903900A00104006B0202005000E2A89368F018E918CB98A758D73882)
+, .INIT_07 (256'h0060003900000039B07D00000050004400220039B07D707A307730F001080071)
 , .INIT_08 (256'h00050091C88F002200240091288B28FE000C0110008624FB25020240009CD0FB)
 , .INIT_09 (256'h48A528A128FE00140039487F0CAD28FE0110009724FB25020140005004020091)
 , .INIT_0A (256'h8839089C040800AD011000AB24FB250200C000500081005048A5002200240039)

py393sata/x393sata.py

@@ -534,11 +534,15 @@ class x393sata(object):
                 break
             sleep(0.1)
         else:
-            print ("Failed to get interrupt")    
+            print ("\n ====================== Failed to get interrupt ============================")    
             self.reg_status()
             print("_=mem.mem_dump (0x%x, 0x4,4)"%(MAXI1_ADDR + DBG_OFFS))
             self.x393_mem.mem_dump (MAXI1_ADDR + DBG_OFFS, 0x4,4)        
+            print("Datascope (debug) data:")    
+            print("_=mem.mem_dump (0x%x, 0x20,4)"%(DATASCOPE_ADDR))
+            self.x393_mem.mem_dump (DATASCOPE_ADDR, 0xa0,4)
             raise Exception("Failed to get interrupt")
+            
         print("Datascope (debug) data:")    
         print("_=mem.mem_dump (0x%x, 0x20,4)"%(DATASCOPE_ADDR))
         self.x393_mem.mem_dump (DATASCOPE_ADDR, 0x20,4)
@@ -616,14 +620,28 @@ class x393sata(object):
                 self.parse_register(group_range = ['HBA_PORT__PxIS'],
                                     skip0 =       True,
                                     dword =       None)
+                if istat != 1: #DHRS interrupt (for PIO - 2)
+                    print ("\n ======================Got wrong interrupt ============================")    
+                    self.reg_status()
+                    print("_=mem.mem_dump (0x%x, 0x4,4)"%(MAXI1_ADDR + DBG_OFFS))
+                    self.x393_mem.mem_dump (MAXI1_ADDR + DBG_OFFS, 0x4,4)        
+                    print("Datascope (debug) data:")    
+                    print("_=mem.mem_dump (0x%x, 0x20,4)"%(DATASCOPE_ADDR))
+                    self.x393_mem.mem_dump (DATASCOPE_ADDR, 0xa0,4)
+                    raise Exception("Failed to get interrupt")
+                    
                 break
             sleep(0.1)
         else:
-            print ("Failed to get interrupt")    
+            print ("\n ====================== Failed to get interrupt ============================")    
             self.reg_status()
             print("_=mem.mem_dump (0x%x, 0x4,4)"%(MAXI1_ADDR + DBG_OFFS))
             self.x393_mem.mem_dump (MAXI1_ADDR + DBG_OFFS, 0x4,4)        
+            print("Datascope (debug) data:")    
+            print("_=mem.mem_dump (0x%x, 0x20,4)"%(DATASCOPE_ADDR))
+            self.x393_mem.mem_dump (DATASCOPE_ADDR, 0xa0,4)
             raise Exception("Failed to get interrupt")
+            
         print("Datascope (debug) data:")    
         print("_=mem.mem_dump (0x%x, 0x20,4)"%(DATASCOPE_ADDR))
         self.x393_mem.mem_dump (DATASCOPE_ADDR, 0xa0,4)
@@ -705,10 +723,13 @@ class x393sata(object):
                 break
             sleep(0.1)
         else:
-            print ("Failed to get interrupt")    
+            print ("\n ====================== Failed to get interrupt ============================")    
             self.reg_status()
             print("_=mem.mem_dump (0x%x, 0x4,4)"%(MAXI1_ADDR + DBG_OFFS))
             self.x393_mem.mem_dump (MAXI1_ADDR + DBG_OFFS, 0x4,4)        
+            print("Datascope (debug) data:")    
+            print("_=mem.mem_dump (0x%x, 0x20,4)"%(DATASCOPE_ADDR))
+            self.x393_mem.mem_dump (DATASCOPE_ADDR, 0xa0,4)
             raise Exception("Failed to get interrupt")
             
         print("Datascope (debug) data:")    
@@ -1062,6 +1083,15 @@ sata.reg_status(),sata.reset_ie(),sata.err_count()
 '0x3'
 
 
+for block in range (38,255):
+    print("\n======== Reading block %d ==============="%block)
+    sata.arm_logger()
+    sata.dd_read_dma(block, 1)
+    _=mem.mem_dump (0x80000ff0, 4,4)
+    sata.reg_status(),sata.reset_ie(),sata.err_count()
+
+
+
 
 for block in range (1,255):
     sata.dd_read_dma(block, 1)
@@ -1075,6 +1105,12 @@ for block in range (1,255):
     _=mem.mem_dump (0x80001000, 0x100,4)
     sata.reg_status(),sata.reset_ie(),sata.err_count()
 
+for block in range (45,255):
+    print("\n======== Reading block %d ==============="%block)
+    sata.arm_logger()
+    sata.dd_read_dma(block, 1)
+    _=mem.mem_dump (0x80000ff0, 4,4)
+    sata.reg_status(),sata.reset_ie(),sata.err_count()
 
 
 #sata.drp (0x20b,0x81), sata.drp (0x20b,0x4081)