Commit fb82aa54 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

eliminated all phy errors, working on remaining in ll

parent 78da3183

.project

+17 −17
Original line number Original line Diff line number Diff line
@@ -52,87 +52,87 @@ 
		<link>

		<link>

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			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160213012011614.dcp</location>

			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160214170151284.dcp</location>

		</link>

		</link>

	</linkedResources>

	</linkedResources>

</projectDescription>
 
</projectDescription>

ahci/ahci_fis_receive.v

+3 −3
Original line number Original line Diff line number Diff line
@@ -182,10 +182,10 @@ localparam DATA_TYPE_ERR = 3; 
    wire                reg_we_w;

    wire                reg_we_w;





    reg           [3:0] store_sig;

    reg           [3:0] store_sig;

    reg           [5:0] reg_ds;

    reg           [5:0] reg_ds;     //Unused?

    reg           [4:0] reg_ps;

    reg           [4:0] reg_ps;

    reg                 reg_d2h;    

    reg                 reg_d2h;    //unused?

    reg           [1:0] reg_sdb;    

    reg           [1:0] reg_sdb;    //unused?

    reg          [31:2] xfer_cntr_r;

    reg          [31:2] xfer_cntr_r;

    reg          [31:2] prdbc_r;

    reg          [31:2] prdbc_r;

ahci/ahci_fis_transmit.v

+1 −1
Original line number Original line Diff line number Diff line
@@ -53,7 +53,7 @@ module ahci_fis_transmit #( 
    input                         xmit_err,     // 

    input                         xmit_err,     // 

    input                         syncesc_recv, // These two inputs interrupt transmit

    input                         syncesc_recv, // These two inputs interrupt transmit

    input                         xrdy_collision, 

    input                         xrdy_collision, 

    output                 [ 2:0] dx_err,       // bit 0 - syncesc_recv, 1 - xmit_err, 2 - collision  (valid @ xmit_err and later, reset by new command)

    output                 [ 2:0] dx_err,       // bit 0 - syncesc_recv, 1 - R_ERR (was xmit_err), 2 - collision  (valid @ xmit_err and later, reset by new command)

    

    

    output                 [15:0] ch_prdtl,    // Physical region descriptor table length (in entries, 0 is 0)

    output                 [15:0] ch_prdtl,    // Physical region descriptor table length (in entries, 0 is 0)

    output                        ch_c,        // Clear busy upon R_OK for this FIS

    output                        ch_c,        // Clear busy upon R_OK for this FIS

ahci/ahci_fsm.v

+1 −1
Original line number Original line Diff line number Diff line
@@ -225,7 +225,7 @@ module ahci_fsm 
//    output                        dmaCntrZero, // DMA counter is zero - would be a duplicate to the one in receive module and dwords_sent output

//    output                        dmaCntrZero, // DMA counter is zero - would be a duplicate to the one in receive module and dwords_sent output

//    input                         syncesc_recv, // These two inputs interrupt transmit

//    input                         syncesc_recv, // These two inputs interrupt transmit

//    input                         xmit_err,     // 

//    input                         xmit_err,     // 

    input                  [ 2:0] dx_err,       // bit 0 - syncesc_recv, 1 - xmit_err, 2 - X_RDY/X_RDY collision (valid @ xmit_err and later, reset by new command)

    input                  [ 2:0] dx_err,       // bit 0 - syncesc_recv, 1 - R_ERR (was xmit_err), 2 - X_RDY/X_RDY collision (valid @ xmit_err and later, reset by new command)

    

    

///    input                  [15:0] ch_prdtl,    // Physical region descriptor table length (in entries, 0 is 0)

///    input                  [15:0] ch_prdtl,    // Physical region descriptor table length (in entries, 0 is 0)

    input                         ch_c,        // Clear busy upon R_OK for this FIS

    input                         ch_c,        // Clear busy upon R_OK for this FIS

ahci/ahci_sata_layers.v

+73 −37
Original line number Original line Diff line number Diff line
@@ -27,7 +27,11 @@ module ahci_sata_layers #( 
    parameter DATASCOPE_POST_MEAS =  16, // number of measurements to perform after event

    parameter DATASCOPE_POST_MEAS =  16, // number of measurements to perform after event

`endif        

`endif        

    parameter BITS_TO_START_XMIT =    6,   // wait H2D FIFO to have 1 << BITS_TO_START_XMIT to start FIS transmission (or all FIS fits)

    parameter BITS_TO_START_XMIT =    6,   // wait H2D FIFO to have 1 << BITS_TO_START_XMIT to start FIS transmission (or all FIS fits)

    parameter  DATA_BYTE_WIDTH =      4

    parameter DATA_BYTE_WIDTH =       4,

    parameter ELASTIC_DEPTH =         4, //5, With 4/7 got infrequent overflows!

    parameter ELASTIC_OFFSET =        7, //  5 //10

    parameter FREQ_METER_WIDTH =     12

    

)(

)(

    input              exrst,   // master reset that resets PLL and GTX

    input              exrst,   // master reset that resets PLL and GTX

    input              reliable_clk, // use aclk that runs independently of the GTX

    input              reliable_clk, // use aclk that runs independently of the GTX
@@ -114,9 +118,10 @@ module ahci_sata_layers #( 
    output              drp_rdy,

    output              drp_rdy,

    output       [15:0] drp_do ,

    output       [15:0] drp_do ,

`endif    

`endif    

    

    output  [FREQ_METER_WIDTH - 1:0] xclk_period,      // relative (to 2*clk) xclk period

    output       [31:0] debug_phy,

    output       [31:0] debug_phy,

    output       [31:0] debug_link

    output       [31:0] debug_link,

    input               hclk // just for testing

    

    

    

    

);

);
@@ -202,11 +207,11 @@ module ahci_sata_layers #( 




    wire                           rxelsfull; 

    wire                           rxelsfull; 

    wire                           rxelsempty; 

    wire                           rxelsempty; 



    wire                           xclk;             // output receive clock, just to measure frequency

//    wire  [FREQ_METER_WIDTH - 1:0] xclk_period;      // relative (to 2*clk) xclk period

    

    

    wire debug_detected_alignp; // oob detects ALIGNp, but not the link layer

    wire debug_detected_alignp; // oob detects ALIGNp, but not the link layer

    

    wire                    [31:0] debug_phy0;

    

//    assign debug_sata = {link_established, phy_ready, debug_phy[29:16],debug_link[15:0]}; // 

//    assign debug_sata = {link_established, phy_ready, debug_phy[29:16],debug_link[15:0]}; // 

//    assign debug_sata = debug_link[31:0]; // 

//    assign debug_sata = debug_link[31:0]; // 

///    assign debug_sata = debug_phy;

///    assign debug_sata = debug_phy;
@@ -248,6 +253,24 @@ module ahci_sata_layers #( 
    assign serr_EM = phy_ready && (0);   // RWC: Communication between the device and host was lost but re-established

    assign serr_EM = phy_ready && (0);   // RWC: Communication between the device and host was lost but re-established

    assign serr_EI = phy_ready && (0);   // RWC: Recovered Data integrity Error

    assign serr_EI = phy_ready && (0);   // RWC: Recovered Data integrity Error

    

    

    reg [1:0] debug_last_d2h_type_in;

    always @ (posedge clk) begin

        if (d2h_fifo_wr) debug_last_d2h_type_in<= d2h_type_in;

    end

    assign debug_phy = {h2d_type_out[1:0],h2d_type[1:0],

                        ll_h2d_last,d2h_valid,  d2h_type[1:0],

                        debug_last_d2h_type_in, d2h_type_in[1:0],

                        debug_phy0[19:0]};

    

/*

// Data/type FIFO, device -> host

    output      [31:0] d2h_data,         // FIFO input  data

    output      [ 1:0] d2h_mask,     // set to 2'b11

    output      [ 1:0] d2h_type,    // 0 - data, 1 - FIS head, 2 - R_OK, 3 - R_ERR (last two - after data, so ignore data with R_OK/R_ERR)

    output             d2h_valid,  // Data available from the transport layer in FIFO                

    output             d2h_many,    // Multiple DWORDs available from the transport layer in FIFO           

    input              d2h_ready,   // This module or DMA consumes DWORD

*/    

//        .comreset_send   (comreset_send),     // input

//        .comreset_send   (comreset_send),     // input

//        .cominit_got     (cominit_got),       // output wire 

//        .cominit_got     (cominit_got),       // output wire 

//        .comwake_got     (serr_DW),            // output wire 

//        .comwake_got     (serr_DW),            // output wire
@@ -338,7 +361,9 @@ module ahci_sata_layers #( 
        .DATASCOPE_START_BIT (DATASCOPE_START_BIT),

        .DATASCOPE_START_BIT (DATASCOPE_START_BIT),

        .DATASCOPE_POST_MEAS (DATASCOPE_POST_MEAS),

        .DATASCOPE_POST_MEAS (DATASCOPE_POST_MEAS),

`endif    

`endif    

        .DATA_BYTE_WIDTH(4)

        .DATA_BYTE_WIDTH     (DATA_BYTE_WIDTH),

        .ELASTIC_DEPTH       (ELASTIC_DEPTH),

        .ELASTIC_OFFSET      (ELASTIC_OFFSET)

    ) phy (

    ) phy (

        .extrst              (exrst),             // input wire 

        .extrst              (exrst),             // input wire 

        .clk                 (clk),               // output wire 

        .clk                 (clk),               // output wire
@@ -368,13 +393,14 @@ module ahci_sata_layers #( 
        .cplllock_debug      (),

        .cplllock_debug      (),

        .usrpll_locked_debug (),

        .usrpll_locked_debug (),

        .re_aligned          (serr_DS),           // output reg 

        .re_aligned          (serr_DS),           // output reg 

        .xclk                (xclk),             // output receive clock, just to measure frequency





`ifdef USE_DATASCOPE

`ifdef USE_DATASCOPE

        .datascope_clk     (datascope_clk),     // output

        .datascope_clk     (datascope_clk),     // output

        .datascope_waddr   (datascope_waddr),   // output[9:0] 

        .datascope_waddr   (datascope_waddr),   // output[9:0] 

        .datascope_we      (datascope_we),      // output

        .datascope_we      (datascope_we),      // output

        .datascope_di      (datascope_di),      // output[31:0] 

        .datascope_di      (datascope_di),      // output[31:0] 

        .datascope_trig    (ll_frame_ackn),     // input datascope external trigger

        .datascope_trig    (ll_incom_invalidate), // ll_frame_ackn),     // input datascope external trigger

`endif        

`endif        





`ifdef USE_DRP

`ifdef USE_DRP
@@ -387,7 +413,7 @@ module ahci_sata_layers #( 
        .drp_rdy           (drp_rdy),           // output

        .drp_rdy           (drp_rdy),           // output

        .drp_do            (drp_do),            // output[15:0] 

        .drp_do            (drp_do),            // output[15:0] 

`endif 

`endif 

        .debug_sata      (debug_phy)  

        .debug_sata      (debug_phy0)  

        ,.debug_detected_alignp(debug_detected_alignp)

        ,.debug_detected_alignp(debug_detected_alignp)

    );

    );
@@ -459,5 +485,15 @@ module ahci_sata_layers #( 
        .data_in  ({d2h_type_in, ll_d2h_mask_out, ll_d2h_data_out}) // input[35:0] 

        .data_in  ({d2h_type_in, ll_d2h_mask_out, ll_d2h_data_out}) // input[35:0] 

    );

    );





    freq_meter #(

        .WIDTH    (FREQ_METER_WIDTH),

        .PRESCALE (1)

    ) freq_meter_i (

        .rst   (rst),        // input

        .clk   (clk),        // input

        .xclk  (xclk), // hclk), //xclk),       // input

        .dout  (xclk_period) // output[11:0] reg 

    );



endmodule

endmodule