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    reg          [1:0] d2h_type_in;

    reg          [1:0] d2h_type_in;

    reg                fis_over_r;  // push 1 more DWORD (ignore) + type (ERR/OK) when received FIS is done/error         

    reg                fis_over_r;  // push 1 more DWORD (ignore) + type (ERR/OK) when received FIS is done/error         

    wire ll_frame_req_w;       // pre ll_frame_req

//    wire ll_frame_req_w;       // pre ll_frame_req

    reg  ll_frame_req;         // -> link // request for a new frame transition

    reg  ll_frame_req;         // -> link // request for a new frame transition

    wire ll_frame_busy;        // link -> // a little bit of overkill with the cound of response signals, think of throwing out 1 of them // LL tells back if it cant handle the request for now

    wire ll_frame_ackn;        // acknowledge for ll_frame_req

//    wire ll_frame_busy;        // link -> // a little bit of overkill with the cound of response signals, think of throwing out 1 of them // LL tells back if it cant handle the request for now

//    wire ll_frame_ack;         // link -> // LL tells if the request is transmitting not used

//    wire ll_frame_ack;         // link -> // LL tells if the request is transmitting not used

//    wire ll_frame_rej;         // link -> // or if it was cancelled because of simultanious incoming transmission

//    wire ll_frame_rej;         // link -> // or if it was cancelled because of simultanious incoming transmission

//    wire ll_frame_done_good;   // link -> // TL tell if the outcoming transaction is done and how it was done

//    wire ll_frame_done_good;   // link -> // TL tell if the outcoming transaction is done and how it was done

    assign h2d_ready = !h2d_fill[FIFO_ADDR_WIDTH] && !(&h2d_fill[FIFO_ADDR_WIDTH:3]);

    assign h2d_ready = !h2d_fill[FIFO_ADDR_WIDTH] && !(&h2d_fill[FIFO_ADDR_WIDTH:3]);

    assign ll_d2h_almost_full   = d2h_fill[FIFO_ADDR_WIDTH] || &d2h_fill[FIFO_ADDR_WIDTH-1:6]; // 63 dwords (maybe use :5?) - time to tell device to stop 

    assign ll_d2h_almost_full   = d2h_fill[FIFO_ADDR_WIDTH] || &d2h_fill[FIFO_ADDR_WIDTH-1:6]; // 63 dwords (maybe use :5?) - time to tell device to stop 

    assign ll_frame_req_w = !ll_frame_busy && h2d_pending && (((h2d_type == H2D_TYPE_FIS_LAST) && h2d_fifo_wr ) || (|h2d_fill[FIFO_ADDR_WIDTH : BITS_TO_START_XMIT]));

//    assign ll_frame_req_w = !ll_frame_busy && h2d_pending && (((h2d_type == H2D_TYPE_FIS_LAST) && h2d_fifo_wr ) || (|h2d_fill[FIFO_ADDR_WIDTH : BITS_TO_START_XMIT]));

// Separating different types of errors, sync_escape from other problems. TODO: route individual errors to set SERR bits

// Separating different types of errors, sync_escape from other problems. TODO: route individual errors to set SERR bits

//assign  incom_invalidate = state_rcvr_eof & crc_bad & ~alignes_pair | state_rcvr_data   & dword_val &  rcvd_dword[CODE_WTRMP];

//assign  incom_invalidate = state_rcvr_eof & crc_bad & ~alignes_pair | state_rcvr_data   & dword_val &  rcvd_dword[CODE_WTRMP];

    assign phy_speed = phy_ready ? PHY_SPEED:0;

    assign phy_speed = phy_ready ? PHY_SPEED:0;

    assign serr_DT = phy_ready && (0);   // RWC: Transport state transition error

    assign serr_DT = phy_ready && (0);   // RWC: Transport state transition error

    assign serr_DS = phy_ready && (0);   // RWC: Link sequence error

    assign serr_DS = phy_ready && (0);   // RWC: Link sequence error

    assign serr_DC = phy_ready && (0);   // RWC: CRC error in Link layer

    assign serr_DC = phy_ready && (0);   // RWC: CRC error in Link layer

    assign serr_DB = phy_ready && (0);   // RWC: 10B to 8B decode error

//    assign serr_DB = phy_ready && (0);   // RWC: 10B to 8B decode error

    assign serr_DI = phy_ready && (0);   // RWC: PHY Internal Error

    assign serr_DI = phy_ready && (0);   // RWC: PHY Internal Error

    assign serr_EP = phy_ready && (0);   // RWC: Protocol Error - a violation of SATA protocol detected

    assign serr_EP = phy_ready && (0);   // RWC: Protocol Error - a violation of SATA protocol detected

    assign serr_EC = phy_ready && (0);   // RWC: Persistent Communication or Data Integrity Error

    assign serr_EC = phy_ready && (0);   // RWC: Persistent Communication or Data Integrity Error

        .data_last_out    (),                      // ll_d2h_last),        // output wire not used

        .data_last_out    (),                      // ll_d2h_last),        // output wire not used

        .frame_req        (ll_frame_req),          // input wire  // request for a new frame transmission

        .frame_req        (ll_frame_req),          // input wire  // request for a new frame transmission

        .frame_busy       (ll_frame_busy),         // output wire // a little bit of overkill with the cound of response signals, think of throwing out 1 of them // LL tells back if it cant handle the request for now

        .frame_busy       (), // ll_frame_busy),   // output wire // a little bit of overkill with the cound of response signals, think of throwing out 1 of them // LL tells back if it cant handle the request for now

        .frame_ack        (),                      // ll_frame_ack), // output wire // LL tells if the request is transmitting

        .frame_ack        (ll_frame_ackn),         // ll_frame_ack), // output wire // LL tells if the request is transmitting

        .frame_rej        (x_rdy_collision),       // output wire // or if it was cancelled because of simultanious incoming transmission

        .frame_rej        (x_rdy_collision),       // output wire // or if it was cancelled because of simultanious incoming transmission

        .frame_done_good  (xmit_ok),               // output wire // TL tell if the outcoming transaction is done and how it was done

        .frame_done_good  (xmit_ok),               // output wire // TL tell if the outcoming transaction is done and how it was done

        .frame_done_bad   (xmit_err),              // output wire 

        .frame_done_bad   (xmit_err),              // output wire 

        else if ((h2d_type == H2D_TYPE_FIS_HEAD) && h2d_fifo_wr) h2d_pending <= 1;

        else if ((h2d_type == H2D_TYPE_FIS_HEAD) && h2d_fifo_wr) h2d_pending <= 1;

        if (rst)                                                        ll_frame_req <= 0;

        if (rst)                                                        ll_frame_req <= 0;

        else     ll_frame_req <= ll_frame_req_w;

//        else     ll_frame_req <= ll_frame_req_w;

        else if (h2d_pending &&

                  (((h2d_type == H2D_TYPE_FIS_LAST) && h2d_fifo_wr ) ||

                   (|h2d_fill[FIFO_ADDR_WIDTH : BITS_TO_START_XMIT])))  ll_frame_req <= 1;

        else if (ll_frame_ackn)                                         ll_frame_req <= 0;          

    end

    end

//`include "crc.v"

//`include "crc.v"

module link #(

module link #(

    // 4 = dword. 4-bytes aligned data transfers TODO 2 = word - easy, 8 = qword - difficult

    // 4 = dword. 4-bytes aligned data transfers TODO 2 = word - easy, 8 = qword - difficult

    parameter DATA_BYTE_WIDTH = 4

    parameter DATA_BYTE_WIDTH = 4,

    parameter ALIGNES_PERIOD =  252 // period of sending ALIGNp pairs

)

)

(

(

    // TODO insert watchdogs

    // TODO insert watchdogs

    reg [639:0] HOST_LINK_TITLE; // to show human-readable state in the GTKWave

    reg [639:0] HOST_LINK_TITLE; // to show human-readable state in the GTKWave

    reg  [31:0] HOST_LINK_DATA;

    reg  [31:0] HOST_LINK_DATA;

`endif

`endif

// latching data-primitives stream from phy

// latching data-primitives stream from phy

reg     [DATA_BYTE_WIDTH*8 - 1:0] phy_data_in_r;

reg     [DATA_BYTE_WIDTH*8 - 1:0] phy_data_in_r;

reg     [DATA_BYTE_WIDTH   - 1:0] phy_isk_in_r; // charisk

reg     [DATA_BYTE_WIDTH   - 1:0] phy_isk_in_r; // charisk

reg                      data_txing; // if there are still some data to transmit and the transaction wasn't cancelled

reg                      data_txing; // if there are still some data to transmit and the transaction wasn't cancelled

always @ (posedge clk)

always @ (posedge clk) begin

    data_txing <= rst | (data_last_in & data_strobe_out | dword_val & rcvd_dword[CODE_DMATP]) ? 1'b0 : frame_req ? 1'b1 : data_txing;

///    data_txing <= rst | (data_last_in & data_strobe_out | dword_val & rcvd_dword[CODE_DMATP]) ? 1'b0 : frame_req ? 1'b1 : data_txing;

    if (rst ||

         (data_last_in && data_strobe_out)  ||

         (dword_val && rcvd_dword[CODE_DMATP])) data_txing <= 0;

    else if (frame_req)                         data_txing <= 1;    

end    

// fsm

// fsm

// states and transitions are taken from the doc, "Link Layer State Machine" chapter

// states and transitions are taken from the doc, "Link Layer State Machine" chapter

// power mode states are not implemented. TODO insert them as an additional branch of fsm

// power mode states are not implemented. TODO insert them as an additional branch of fsm

                  & ~state_rcvr_goodend

                  & ~state_rcvr_goodend

                  & ~state_rcvr_badend;

                  & ~state_rcvr_badend;

// got an escaping primitive = request to cancel the transmission

// got an escaping primitive = request to cancel the transmission

wire    got_escape;

assign  got_escape = dword_val & rcvd_dword[CODE_SYNCP];

// escaping is done

assign  sync_escape_ack = state_sync_esc;

wire    alignes_pair;   // pauses every state go give a chance to insert 2 align primitives on a line at least every 256 dwords due to spec

wire    alignes_pair;   // pauses every state go give a chance to insert 2 align primitives on a line at least every 256 dwords due to spec

wire    alignes_pair_0; // time for 1st align primitive

//wire    alignes_pair_0; // time for 1st align primitive

wire    alignes_pair_1; // time for 2nd align primitive

//wire    alignes_pair_1; // time for 2nd align primitive

reg     [8:0] alignes_timer;

reg     [8:0] alignes_timer;

assign  alignes_pair_0 = alignes_timer == 9'd252;

///assign  alignes_pair_0 = alignes_timer == 9'd252;

assign  alignes_pair_1 = alignes_timer == 9'd253;

///assign  alignes_pair_1 = alignes_timer == 9'd253;

assign  alignes_pair   = alignes_pair_0 | alignes_pair_1;

///assign  alignes_pair_0 = alignes_timer == 9'd254;

always @ (posedge clk)

///assign  alignes_pair_1 = alignes_timer == 9'd255;

    alignes_timer <= rst | alignes_pair_1 | state_reset ? 9'h0 : alignes_timer + 1'b1;

///always @ (posedge clk)

///    alignes_timer <= rst | alignes_pair_1 | state_reset ? 9'h0 : alignes_timer + 1'b1;

wire    got_escape;

assign  got_escape = dword_val & rcvd_dword[CODE_SYNCP];

// escaping is done

//select_prim[CODE_ALIGNP]

assign  sync_escape_ack = state_sync_esc;

//ALIGNES_PERIOD

reg    alignes_pair_0; // time for 1st align primitive

reg    alignes_pair_1; // time for 2nd align primitive

always @ (posedge clk) begin

    if (rst || select_prim[CODE_ALIGNP]) alignes_timer <= ALIGNES_PERIOD;

    else                                 alignes_timer <= alignes_timer -1;

    alignes_pair_0 <= alignes_timer == 0;

    alignes_pair_1 <= alignes_pair_0;

end

assign  alignes_pair   = alignes_pair_0 | alignes_pair_1;

// Whole transitions table, literally from doc pages 311-328

// Whole transitions table, literally from doc pages 311-328

//    else        rst_r <= ~|rst_timer ? 1'b0 : sata_reset_done ? 1'b0 : 1'b1;

//    else        rst_r <= ~|rst_timer ? 1'b0 : sata_reset_done ? 1'b0 : 1'b1;

///assign  sata_reset_done = rst_timer == RST_TIMER_LIMIT;

///assign  sata_reset_done = rst_timer == RST_TIMER_LIMIT;

*/

*/

always @ (posedge clk or  sata_areset) begin

always @ (posedge clk or  posedge sata_areset) begin

    if      (sata_areset)  sata_reset_done_r <= 0;

    if      (sata_areset)  sata_reset_done_r <= 0;

    else                   sata_reset_done_r <= {sata_reset_done_r[1:0], 1'b1};

    else                   sata_reset_done_r <= {sata_reset_done_r[1:0], 1'b1};

end

end