Fixed most of vdt warnings

.editor_defines

+`define SIMULATION 1
+`define CHECKERS_ENABLED 1
+`define OPEN_SOURCE_ONLY 1
+`define PRELOAD_BRAMS
\ No newline at end of file

.settings/com.elphel.vdt.iverilog.prefs

@@ -3,7 +3,6 @@ eclipse.preferences.version=1
 iverilog_101_TopModulesOther=glbl<-@\#\#@->
 iverilog_103_ExtraFiles=x393/glbl.v<-@\#\#@->
 iverilog_104_IncludeDir=${verilog_project_loc}/x393<-@\#\#@->${verilog_project_loc}/x393/includes<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->${verilog_project_loc}/tb<-@\#\#@->
-iverilog_122_IVerilogOther=-D OPEN_SOURCE_ONLY
 iverilog_77_Param_Exe=/usr/local/bin/iverilog
 iverilog_78_VVP_Exe=/usr/local/bin/vvp
 iverilog_79_GtkWave_Exe=/usr/local/bin/gtkwave

device/oob_dev.v

@@ -121,6 +121,8 @@ end
 
 reg [9:0] txelecidle_cnt;
 
+wire    aligndet;
+wire    syncdet;
 assign  aligndet = ~|(rxdata ^ {8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100}) & ~|(rxcharisk ^ 4'h1); // {D27.3, D10.2, D10.2, K28.5}
 assign  syncdet  = ~|(rxdata ^ {8'b10110101, 8'b10110101, 8'b10010101, 8'b01111100}) & ~|(rxcharisk ^ 4'h1); // {D21.5, D21.5, D21.4, K28.3}
 

device/sata_phy_dev.v

@@ -52,9 +52,6 @@ module sata_phy_dev #(
     input   wire    [3:0]   ll_charisk_in
 );
 
-parameter  CHIPSCOPE            = "FALSE";
-
-wire            txcomfinish;
 wire    [31:0]  txdata;
 wire    [31:0]  txdata_oob;
 wire    [3:0]   txcharisk;
@@ -92,7 +89,7 @@ assign  txdata          = phy_ready ? ll_data_in : txdata_oob;
 assign  txcharisk       = phy_ready ? ll_charisk_in : txcharisk_oob;
 assign  ll_err_out      = 4'h0;
 assign  ll_charisk_out  = rxcharisk[3:0];
-assign  ll_data_out     = rxdata;
+assign  ll_data_out     = rxdata[31:0];
 
 
 oob_dev oob_dev(
@@ -164,7 +161,7 @@ localparam  RXEYERESET_TIME     = 7'h0 + RXPMARESET_TIME + RXCDRPHRESET_TIME + R
 reg     [6:0]   rxeyereset_cnt;
 assign  rxeyereset_done = rxeyereset_cnt == RXEYERESET_TIME;
 always @ (posedge gtrefclk)
-    rxeyereset_cnt  <= rxreset ? 3'h0 : rxeyereset_done ? rxeyereset_cnt : rxeyereset_cnt + 1'b1;
+    rxeyereset_cnt  <= rxreset ? 7'h0 : rxeyereset_done ? rxeyereset_cnt : rxeyereset_cnt + 1'b1;
 
 /*
  * Resets
@@ -503,12 +500,12 @@ gtx_wrapper(
     .CPLLREFCLKLOST                 (),
     .CPLLREFCLKSEL                  (3'b001),
     .CPLLRESET                      (cpllreset),
-    .GTRSVD                         (1'b0),
-    .PCSRSVDIN                      (1'b0),
-    .PCSRSVDIN2                     (1'b0),
-    .PMARSVDIN                      (1'b0),
-    .PMARSVDIN2                     (1'b0),
-    .TSTIN                          (1'b1),
+    .GTRSVD                         (16'b0),
+    .PCSRSVDIN                      (16'b0),
+    .PCSRSVDIN2                     (5'b0),
+    .PMARSVDIN                      (5'b0),
+    .PMARSVDIN2                     (5'b0),
+    .TSTIN                          (20'b1),
     .TSTOUT                         (),
     .CLKRSVD                        (4'b0000),
     .GTGREFCLK                      (1'b0),
@@ -714,7 +711,7 @@ gtx_wrapper(
     .TXPCSRESET                     (txpcsreset),
     .TXPMARESET                     (1'b0),
     .TXRESETDONE                    (txresetdone),
-    .TXCOMFINISH                    (txcomfinish),
+    .TXCOMFINISH                    (),
     .TXCOMINIT                      (txcominit),
     .TXCOMSAS                       (1'b0),
     .TXCOMWAKE                      (txcomwake),
@@ -740,6 +737,8 @@ assign  rxchariscomma   = twobytes_shift ? {rxchariscomma_gtx[7:4], rxchariscomm
 assign  rxdisperr       = twobytes_shift ? {rxdisperr_gtx[7:4]    , rxdisperr_gtx[1:0]    , rxdisperr_gtx[3:2]    } : rxdisperr_gtx;
 assign  rxnotintable    = twobytes_shift ? {rxnotintable_gtx[7:4] , rxnotintable_gtx[1:0] , rxnotintable_gtx[3:2] } : rxnotintable_gtx;
 
+assign  ll_err_out      = rxdisperr[3:0] | rxnotintable[3:0];
+
 /*
  * Interfaces
  */

dma/axi_regs.v

@@ -20,10 +20,7 @@
  *******************************************************************************/
 //`include "axibram_read.v"
 //`include "axibram_write.v"
-module axi_regs #(
-    parameter REGISTERS_CNT = 20
-)
-(
+module axi_regs(
     input   wire                ACLK,              // AXI PS Master GP1 Clock , input
     input   wire                ARESETN,           // AXI PS Master GP1 Reset, output
 // AXI PS Master GP1: Read Address    
@@ -31,13 +28,9 @@ module axi_regs #(
     input   wire                ARVALID,           // AXI PS Master GP1 ARVALID, output
     output  wire                ARREADY,           // AXI PS Master GP1 ARREADY, input
     input   wire    [11:0]      ARID,              // AXI PS Master GP1 ARID[11:0], output
-    input   wire    [1:0]       ARLOCK,            // AXI PS Master GP1 ARLOCK[1:0], output
-    input   wire    [3:0]       ARCACHE,           // AXI PS Master GP1 ARCACHE[3:0], output
-    input   wire    [2:0]       ARPROT,            // AXI PS Master GP1 ARPROT[2:0], output
     input   wire    [3:0]       ARLEN,             // AXI PS Master GP1 ARLEN[3:0], output
     input   wire    [1:0]       ARSIZE,            // AXI PS Master GP1 ARSIZE[1:0], output
     input   wire    [1:0]       ARBURST,           // AXI PS Master GP1 ARBURST[1:0], output
-    input   wire    [3:0]       ARQOS,             // AXI PS Master GP1 ARQOS[3:0], output
 // AXI PS Master GP1: Read Data
     output  wire    [31:0]      RDATA,             // AXI PS Master GP1 RDATA[31:0], input
     output  wire                RVALID,            // AXI PS Master GP1 RVALID, input
@@ -50,13 +43,9 @@ module axi_regs #(
     input   wire                AWVALID,           // AXI PS Master GP1 AWVALID, output
     output  wire                AWREADY,           // AXI PS Master GP1 AWREADY, input
     input   wire    [11:0]      AWID,              // AXI PS Master GP1 AWID[11:0], output
-    input   wire    [1:0]       AWLOCK,            // AXI PS Master GP1 AWLOCK[1:0], output
-    input   wire    [3:0]       AWCACHE,           // AXI PS Master GP1 AWCACHE[3:0], output
-    input   wire    [2:0]       AWPROT,            // AXI PS Master GP1 AWPROT[2:0], output
     input   wire    [3:0]       AWLEN,             // AXI PS Master GP1 AWLEN[3:0], outpu:t
     input   wire    [1:0]       AWSIZE,            // AXI PS Master GP1 AWSIZE[1:0], output
     input   wire    [1:0]       AWBURST,           // AXI PS Master GP1 AWBURST[1:0], output
-    input   wire    [3:0]       AWQOS,             // AXI PS Master GP1 AWQOS[3:0], output
 // AXI PS Master GP1: Write Data
     input   wire    [31:0]      WDATA,             // AXI PS Master GP1 WDATA[31:0], output
     input   wire                WVALID,            // AXI PS Master GP1 WVALID, output

dma/dma_adapter.v

@@ -96,7 +96,7 @@ assign  rd_start = set_busy & ~cmd_type;
 always @ (posedge clk)
 begin
     cmd_type_r  <= rst ? 1'b0 : set_busy ? cmd_type : cmd_type_r;
-    cmd_addr_r  <= rst ? 1'b0 : set_busy ? cmd_addr : cmd_addr_r;
+    cmd_addr_r  <= rst ? 25'b0 : set_busy ? cmd_addr[31:7] : cmd_addr_r[31:7];
     cmd_busy_r  <= (cmd_busy_r | set_busy) & ~rst & ~clr_busy;
 end
 
@@ -126,18 +126,21 @@ reg     [3:0]   rdwr_state;
 localparam READ_IDLE        = 0;
 localparam READ_WAIT_ADDR   = 3;
 localparam READ_DATA        = 4;
-reg             rd_reset_page;
+wire            rd_reset_page;
 reg             rd_next_page;
-reg             rd_data;
+wire    [63:0]  rd_data;
 reg     [6:0]   rd_data_count;
 reg             rd_en;
 
 wire            rd_stop;
-wire            rd_cnt_to_pull;
+wire    [6:0]   rd_cnt_to_pull;
 
 assign  rd_cnt_to_pull = 7'hf;
 assign  rd_stop = rd_ack_in & rd_data_count == rd_cnt_to_pull;
 
+assign  rd_reset_page = 1'b0;
+assign  rd_data     = buf_rdata;
+assign  rd_val_out  = rd_en;
 assign  rd_data_out = rd_data;
 
 always @ (posedge clk)
@@ -296,7 +299,7 @@ localparam MEMBR_SIZE   = 5;
 localparam MEMBR_LOADDR = 6;
 localparam MEMBR_CTRL   = 7;
 
-reg     [32:0]  membr_data;
+reg     [31:0]  membr_data;
 reg     [15:0]  membr_addr;
 reg             membr_start;
 reg             membr_done;
@@ -374,7 +377,7 @@ always @ (posedge clk)
             end
             MEMBR_LOADDR:
             begin
-                membr_data  <= cmd_addr_r;
+                membr_data  <= {7'h0, cmd_addr_r[31:7]};
                 membr_addr  <= 16'h202;
                 membr_start <= membr_inprocess ? 1'b0 : 1'b1;
                 membr_setup <= membr_inprocess | membr_setup ? 1'b0 : 1'b1;

dma/dma_control.v

@@ -96,7 +96,7 @@ always @ (posedge sclk)
 
 // drive iface signals
 assign  host_new_cmd        = host_issued_set;
-assign  host_cmd_type       = dma_type;
+assign  host_cmd_type       = {1'b0, dma_type};
 assign  host_sector_count   = sector_cnt;
 assign  host_sector_addr    = lba;
 
@@ -134,6 +134,7 @@ begin
     state_wait_done <= (state_wait_done | set_wait_done) & ~clr_wait_done & ~rst;
 end
 
+assign  adp_val_sclk = set_wait_busy;
 // conrol signals resync
 reg             adp_val_r;
 reg             adp_val_rr;
@@ -143,7 +144,7 @@ begin
     adp_val_rr  <= adp_val_r;
 end
 
-assign  adp_addr = current_addr;
+assign  adp_addr = current_addr[31:7];
 assign  adp_type = current_type;
 assign  adp_val  = adp_val_rr;
 
@@ -208,9 +209,9 @@ assign  last_data = (sector_cnt == quarter_sector_cnt[33:2] + 1'b1) & (&quarter_
 // calculate outgoing address
 // increment every transaction to adapter
 always @ (posedge sclk)
-    current_addr <= ~set_wait_busy ? current_addr :
-                        state_idle ? mem_address :           // new dma request
-                                     current_addr + 1'b1; // same dma request, next 128 bytes
+    current_addr <= ~set_wait_busy ? current_addr[31:7] :
+                        state_idle ? mem_address[31:7] :           // new dma request
+                                     current_addr[31:7] + 1'b1; // same dma request, next 128 bytes
 
 always @ (posedge sclk)
     current_type <= ~set_wait_busy ? current_type :
@@ -262,13 +263,13 @@ end
 // write address -> sclk (rd) domain to compare 
 always @ (posedge sclk)
 begin
-    from_wr_addr_gr_r   <= rst ?  9'h0 : from_wr_addr;
+    from_wr_addr_gr_r   <= rst ?  9'h0 : from_wr_addr_gr;
     from_wr_addr_gr_rr  <= rst ?  9'h0 : from_wr_addr_gr_r;
 end
 // read address -> hclk (wr) domain to compare 
 always @ (posedge hclk)
 begin
-    from_rd_addr_gr_r   <= rst ? 10'h0 : from_rd_addr;
+    from_rd_addr_gr_r   <= rst ? 10'h0 : from_rd_addr_gr;
     from_rd_addr_gr_rr  <= rst ? 10'h0 : from_rd_addr_gr_r;
 end
 // translate resynced write address into ordinary (non-gray) address
@@ -367,13 +368,13 @@ end
 // write address -> hclk (rd) domain to compare 
 always @ (posedge hclk)
 begin
-    to_wr_addr_gr_r   <= rst ? 10'h0 : to_wr_addr;
+    to_wr_addr_gr_r   <= rst ? 10'h0 : to_wr_addr_gr;
     to_wr_addr_gr_rr  <= rst ? 10'h0 : to_wr_addr_gr_r;
 end
 // read address -> sclk (wr) domain to compare 
 always @ (posedge sclk)
 begin
-    to_rd_addr_gr_r   <= rst ?  9'h0 : to_rd_addr;
+    to_rd_addr_gr_r   <= rst ?  9'h0 : to_rd_addr_gr;
     to_rd_addr_gr_rr  <= rst ?  9'h0 : to_rd_addr_gr_r;
 end
 // translate resynced write address into ordinary (non-gray) address
@@ -400,8 +401,8 @@ endgenerate
 //              to_wr_addr_r - write address some hclk ticks ago
 //  => we can say if the fifo have the possibility to be empty
 //     since actual to_wr_addr could only be incremented
-assign  to_full   = {to_wr_addr, 1'b0}  == to_rd_addr_r + 1'b1;
-assign  to_empty  = {to_wr_addr_r, 1'b0} == to_rd_addr; // overflows must never be achieved
+assign  to_full   = to_wr_addr  == {to_rd_addr_r, 1'b0} + 1'b1;
+assign  to_empty  = to_wr_addr_r == {to_rd_addr, 1'b0}; // overflows must never be achieved
 // calculate bus responses in order to fifo status:
 assign  to_val    = ~to_empty;
 assign  in_val    = ~in_busy & ~to_full;

dma/dma_regs.v

@@ -18,10 +18,7 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/> .
  *******************************************************************************/
-module dma_regs #(
-    parameter REGISTERS_CNT = 20
-)
-(
+module dma_regs(
     input   wire            rst,
     input   wire            ACLK,
     input   wire            sclk,
@@ -190,27 +187,27 @@ assign sh_autoact_val   = bram_wen & (bram_waddr[7:0] == 8'hc);
 assign sh_inter_val     = bram_wen & (bram_waddr[7:0] == 8'hd);
 assign sh_dir_val       = bram_wen & (bram_waddr[7:0] == 8'he);
 assign cmd_val_out      = bram_wen & (bram_waddr[7:0] == 8'hf);
-assign sh_port          = bram_wen & (bram_waddr[7:0] == 8'h13);
+assign sh_port_val      = bram_wen & (bram_waddr[7:0] == 8'h13);
 assign sh_dma_cnt_val   = bram_wen & (bram_waddr[7:0] == 8'h14);
 assign sh_notif_val     = bram_wen & (bram_waddr[7:0] == 8'h15);
 
 assign sh_data          = wdata;
-assign sh_feature       = wdata;
-assign sh_lba_lo        = wdata;
-assign sh_lba_hi        = wdata;
-assign sh_count         = wdata;
-assign sh_command       = wdata;
-assign sh_dev           = wdata;
-assign sh_control       = wdata;
+assign sh_feature       = wdata[15:0];
+assign sh_lba_lo        = wdata[23:0];
+assign sh_lba_hi        = wdata[23:0];
+assign sh_count         = wdata[15:0];
+assign sh_command       = wdata[7:0];
+assign sh_dev           = wdata[7:0];
+assign sh_control       = wdata[7:0];
 assign sh_dma_id_lo     = wdata;
 assign sh_dma_id_hi     = wdata;
 assign sh_buf_off       = wdata;
-assign sh_tran_cnt      = wdata;
-assign sh_autoact       = wdata;
-assign sh_inter         = wdata;
-assign sh_dir           = wdata;
-assign sh_port          = wdata;
-assign sh_notif         = wdata;
+assign sh_tran_cnt      = wdata[15:0];
+assign sh_autoact       = wdata[0];
+assign sh_inter         = wdata[0];
+assign sh_dir           = wdata[0];
+assign sh_port          = wdata[3:0];
+assign sh_notif         = wdata[0];
 assign sh_dma_cnt       = wdata;
 assign cmd_out          = wdata;
 
@@ -231,27 +228,27 @@ always @ (posedge ACLK) begin
                     bram_raddr_r == 8'hf4 ? reg10 :
                     bram_raddr_r == 8'hf5 ? reg14 :
                     bram_raddr_r == 8'h00 ? sh_data_in :
-                    bram_raddr_r == 8'h01 ? sh_feature_in :
-                    bram_raddr_r == 8'h02 ? sh_lba_in[23:0] :
-                    bram_raddr_r == 8'h03 ? sh_lba_in[47:24] :
-                    bram_raddr_r == 8'h04 ? sh_count_in :
-                    bram_raddr_r == 8'h05 ? sh_command_in :
-                    bram_raddr_r == 8'h06 ? sh_dev_in :
-                    bram_raddr_r == 8'h07 ? sh_control_in :
+                    bram_raddr_r == 8'h01 ? {16'h0, sh_feature_in} :
+                    bram_raddr_r == 8'h02 ? {8'h0, sh_lba_in[23:0]} :
+                    bram_raddr_r == 8'h03 ? {8'h0, sh_lba_in[47:24]} :
+                    bram_raddr_r == 8'h04 ? {16'h0, sh_count_in} :
+                    bram_raddr_r == 8'h05 ? {24'h0, sh_command_in} :
+                    bram_raddr_r == 8'h06 ? {24'h0, sh_dev_in} :
+                    bram_raddr_r == 8'h07 ? {24'h0, sh_control_in} :
                     bram_raddr_r == 8'h08 ? sh_dma_id_in[31:0] :
                     bram_raddr_r == 8'h09 ? sh_dma_id_in[63:32] :
                     bram_raddr_r == 8'h0a ? sh_dma_off_in :
-                    bram_raddr_r == 8'h0b ? sh_tran_cnt_in : // Transfer Count
-                    bram_raddr_r == 8'h0c ? sh_autoact_in :
-                    bram_raddr_r == 8'h0d ? sh_inter_in :
-                    bram_raddr_r == 8'h0e ? sh_dir_in :
+                    bram_raddr_r == 8'h0b ? {16'h0, sh_tran_cnt_in} : // Transfer Count
+                    bram_raddr_r == 8'h0c ? {31'h0, sh_autoact_in} :
+                    bram_raddr_r == 8'h0d ? {31'h0, sh_inter_in} :
+                    bram_raddr_r == 8'h0e ? {31'h0, sh_dir_in} :
                     bram_raddr_r == 8'h0f ? cmd_in :
-                    bram_raddr_r == 8'h10 ? sh_err_in :
-                    bram_raddr_r == 8'h11 ? sh_status_in :
-                    bram_raddr_r == 8'h12 ? sh_estatus_in : // E_Status
-                    bram_raddr_r == 8'h13 ? sh_port_in :
+                    bram_raddr_r == 8'h10 ? {24'h0, sh_err_in} :
+                    bram_raddr_r == 8'h11 ? {24'h0, sh_status_in} :
+                    bram_raddr_r == 8'h12 ? {24'h0, sh_estatus_in} : // E_Status
+                    bram_raddr_r == 8'h13 ? {28'h0, sh_port_in} :
                     bram_raddr_r == 8'h14 ? sh_dma_cnt_in :
-                    bram_raddr_r == 8'h15 ? sh_notif_in :
+                    bram_raddr_r == 8'h15 ? {31'h0, sh_notif_in} :
                                             32'hd34db33f;
 end
 assign  bram_rdata = bram_rdata_r;

dma/sata_top.v

@@ -42,13 +42,9 @@
     input   wire                ARVALID,           // AXI PS Master GP1 ARVALID, output
     output  wire                ARREADY,           // AXI PS Master GP1 ARREADY, input
     input   wire    [11:0]      ARID,              // AXI PS Master GP1 ARID[11:0], output
-    input   wire    [1:0]       ARLOCK,            // AXI PS Master GP1 ARLOCK[1:0], output
-    input   wire    [3:0]       ARCACHE,           // AXI PS Master GP1 ARCACHE[3:0], output
-    input   wire    [2:0]       ARPROT,            // AXI PS Master GP1 ARPROT[2:0], output
     input   wire    [3:0]       ARLEN,             // AXI PS Master GP1 ARLEN[3:0], output
     input   wire    [1:0]       ARSIZE,            // AXI PS Master GP1 ARSIZE[1:0], output
     input   wire    [1:0]       ARBURST,           // AXI PS Master GP1 ARBURST[1:0], output
-    input   wire    [3:0]       ARQOS,             // AXI PS Master GP1 ARQOS[3:0], output
 // AXI PS Master GP1: Read Data
     output  wire    [31:0]      RDATA,             // AXI PS Master GP1 RDATA[31:0], input
     output  wire                RVALID,            // AXI PS Master GP1 RVALID, input
@@ -61,13 +57,9 @@
     input   wire                AWVALID,           // AXI PS Master GP1 AWVALID, output
     output  wire                AWREADY,           // AXI PS Master GP1 AWREADY, input
     input   wire    [11:0]      AWID,              // AXI PS Master GP1 AWID[11:0], output
-    input   wire    [1:0]       AWLOCK,            // AXI PS Master GP1 AWLOCK[1:0], output
-    input   wire    [3:0]       AWCACHE,           // AXI PS Master GP1 AWCACHE[3:0], output
-    input   wire    [2:0]       AWPROT,            // AXI PS Master GP1 AWPROT[2:0], output
     input   wire    [3:0]       AWLEN,             // AXI PS Master GP1 AWLEN[3:0], outpu:t
     input   wire    [1:0]       AWSIZE,            // AXI PS Master GP1 AWSIZE[1:0], output
     input   wire    [1:0]       AWBURST,           // AXI PS Master GP1 AWBURST[1:0], output
-    input   wire    [3:0]       AWQOS,             // AXI PS Master GP1 AWQOS[3:0], output
 // AXI PS Master GP1: Write Data
     input   wire    [31:0]      WDATA,             // AXI PS Master GP1 WDATA[31:0], output
     input   wire                WVALID,            // AXI PS Master GP1 WVALID, output
@@ -141,8 +133,8 @@
  */
     output  wire            TXN,
     output  wire            TXP,
-    output  wire            RXN,
-    output  wire            RXP,
+    input   wire            RXN,
+    input   wire            RXP,
 
     input   wire            EXTCLK_P,
     input   wire            EXTCLK_N
@@ -288,6 +280,9 @@ wire            rdata_done; // = membridge.is_last_in_page & membridge.afi_rread
 
 //assign  rst = ARESETN;
 
+// TODO
+assign hclk = ACLK;
+
 
 axi_regs axi_regs(
 // axi iface
@@ -297,13 +292,9 @@ axi_regs axi_regs(
     .ARVALID            (ARVALID),
     .ARREADY            (ARREADY),
     .ARID               (ARID),
-    .ARLOCK             (ARLOCK),
-    .ARCACHE            (ARCACHE),
-    .ARPROT             (ARPROT),
     .ARLEN              (ARLEN),
     .ARSIZE             (ARSIZE),
     .ARBURST            (ARBURST),
-    .ARQOS              (ARQOS),
     .RDATA              (RDATA),
     .RVALID             (RVALID),
     .RREADY             (RREADY),
@@ -314,13 +305,9 @@ axi_regs axi_regs(
     .AWVALID            (AWVALID),
     .AWREADY            (AWREADY),
     .AWID               (AWID),
-    .AWLOCK             (AWLOCK),
-    .AWCACHE            (AWCACHE),
-    .AWPROT             (AWPROT),
     .AWLEN              (AWLEN),
     .AWSIZE             (AWSIZE),
     .AWBURST            (AWBURST),
-    .AWQOS              (AWQOS),
     .WDATA              (WDATA),
     .WVALID             (WVALID),
     .WREADY             (WREADY),
@@ -350,7 +337,7 @@ dma_regs dma_regs(
     .ACLK           (ACLK),
     .sclk           (sclk),
 // control iface
-    .mem_address    (mem_address),
+    .mem_address    (mem_address[31:7]),
     .lba            (lba),
     .sector_cnt     (sector_cnt),
     .dma_type       (dma_type),
@@ -441,7 +428,7 @@ dma_control dma_control(
     .rst                (sata_rst),
 
     // registers iface
-    .mem_address        (mem_address),
+    .mem_address        (mem_address[31:7]),
     .lba                (lba),
     .sector_cnt         (sector_cnt),
     .dma_type           (dma_type),
@@ -450,7 +437,7 @@ dma_control dma_control(
 
     // adapter command iface
     .adp_busy           (adp_busy),
-    .adp_addr           (adp_addr),
+    .adp_addr           (adp_addr[31:7]),
     .adp_type           (adp_type),
     .adp_val            (adp_val),
 
@@ -490,7 +477,7 @@ dma_adapter dma_adapter(
 // command iface                            
     .cmd_type               (adp_type),
     .cmd_val                (adp_val),
-    .cmd_addr               (adp_addr),
+    .cmd_addr               (adp_addr[31:7]),
     .cmd_busy               (adp_busy),
 // data iface                            
     .wr_data_in             (to_data),

dma/top.v

@@ -23,10 +23,10 @@
  * to make the final integration easier - just to make an instance of 
  * what is called now 'axi_regs' and connect it
  */
-`include "system_defines.vh" 
+//`include "system_defines.vh" 
 //`include "sata_top.v"
 module top #(
-`include "includes/x393_parameters.vh"
+`include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - partially used
 )
 (
 // sata serial data iface
@@ -38,10 +38,8 @@ module top #(
     input   wire    EXTCLK_P,
     input   wire    EXTCLK_N
 );
-parameter   REGISTERS_CNT = 20;
-wire [32*REGISTERS_CNT - 1:0] outmem;
-wire clrstart;
 
+wire            axi_aclk0;
 wire            sclk;
 wire            sata_rst;
 wire            extrst;
@@ -55,13 +53,9 @@ wire    [31:0]  ARADDR;
 wire            ARVALID;
 wire            ARREADY;
 wire    [11:0]  ARID;
-wire    [1:0]   ARLOCK;
-wire    [3:0]   ARCACHE;
-wire    [2:0]   ARPROT;
 wire    [3:0]   ARLEN;
 wire    [1:0]   ARSIZE;
 wire    [1:0]   ARBURST;
-wire    [3:0]   ARQOS;
 wire    [31:0]  RDATA;
 wire            RVALID;
 wire            RREADY;
@@ -72,13 +66,9 @@ wire    [31:0]  AWADDR;
 wire            AWVALID;
 wire            AWREADY;
 wire    [11:0]  AWID;
-wire    [1:0]   AWLOCK;
-wire    [3:0]   AWCACHE;
-wire    [2:0]   AWPROT;
 wire    [3:0]   AWLEN;
 wire    [1:0]   AWSIZE;
 wire    [1:0]   AWBURST;
-wire    [3:0]   AWQOS;
 wire    [31:0]  WDATA;
 wire            WVALID;
 wire            WREADY;
@@ -137,28 +127,6 @@ wire [ 7:0] afi0_rcount;     // input[7:0]
 wire [ 2:0] afi0_racount;     // input[2:0] 
 wire        afi0_rdissuecap1en; // output
 
-// send_dma
-wire    [7:0]   cmd_ad;
-wire            cmd_stb;
-wire    [7:0]   status_ad;
-wire            status_rq;
-wire            status_start;
-wire            frame_start_chn;
-wire            next_page_chn;
-wire            cmd_wrmem;
-wire            page_ready_chn;
-wire            frame_done_chn;
-wire    [15:0]  line_unfinished_chn1;
-wire            suspend_chn1;
-wire            xfer_reset_page_rd;
-wire            buf_wpage_nxt;
-wire            buf_wr;
-wire    [63:0]  buf_wdata;
-wire            xfer_reset_page_wr;
-wire            buf_rpage_nxt;
-wire            buf_rd;
-wire    [63:0]  buf_rdata;
-
 assign comb_rst=~frst[0] | frst[1];
 always @(posedge comb_rst or posedge axi_aclk0) begin
     if (comb_rst) axi_rst_pre <= 1'b1;
@@ -191,13 +159,9 @@ sata_top sata_top(
     .ARVALID                    (ARVALID),
     .ARREADY                    (ARREADY),
     .ARID                       (ARID),
-    .ARLOCK                     (ARLOCK),
-    .ARCACHE                    (ARCACHE),
-    .ARPROT                     (ARPROT),
     .ARLEN                      (ARLEN),
     .ARSIZE                     (ARSIZE),
     .ARBURST                    (ARBURST),
-    .ARQOS                      (ARQOS),
 // AXI PS Master GP1: Read Data
     .RDATA                      (RDATA),
     .RVALID                     (RVALID),
@@ -210,13 +174,9 @@ sata_top sata_top(
     .AWVALID                    (AWVALID),
     .AWREADY                    (AWREADY),
     .AWID                       (AWID),
-    .AWLOCK                     (AWLOCK),
-    .AWCACHE                    (AWCACHE),
-    .AWPROT                     (AWPROT),
     .AWLEN                      (AWLEN),
     .AWSIZE                     (AWSIZE),
     .AWBURST                    (AWBURST),
-    .AWQOS                      (AWQOS),
 // AXI PS Master GP1: Write Data
     .WDATA                      (WDATA),
     .WVALID                     (WVALID),
@@ -615,13 +575,13 @@ PS7 ps7_i (
     .MAXIGP1ARVALID (ARVALID),          // AXI PS Master GP1 ARVALID, output
     .MAXIGP1ARREADY (ARREADY),          // AXI PS Master GP1 ARREADY, input
     .MAXIGP1ARID    (ARID),             // AXI PS Master GP1 ARID[11:0], output
-    .MAXIGP1ARLOCK  (ARLOCK),           // AXI PS Master GP1 ARLOCK[1:0], output
-    .MAXIGP1ARCACHE (ARCACHE),          // AXI PS Master GP1 ARCACHE[3:0], output
-    .MAXIGP1ARPROT  (ARPROT),           // AXI PS Master GP1 ARPROT[2:0], output
+    .MAXIGP1ARLOCK  (),           // AXI PS Master GP1 ARLOCK[1:0], output
+    .MAXIGP1ARCACHE (),          // AXI PS Master GP1 ARCACHE[3:0], output
+    .MAXIGP1ARPROT  (),           // AXI PS Master GP1 ARPROT[2:0], output
     .MAXIGP1ARLEN   (ARLEN),            // AXI PS Master GP1 ARLEN[3:0], output
     .MAXIGP1ARSIZE  (ARSIZE),           // AXI PS Master GP1 ARSIZE[1:0], output
     .MAXIGP1ARBURST (ARBURST),          // AXI PS Master GP1 ARBURST[1:0], output
-    .MAXIGP1ARQOS   (ARQOS),            // AXI PS Master GP1 ARQOS[3:0], output
+    .MAXIGP1ARQOS   (),            // AXI PS Master GP1 ARQOS[3:0], output
 // AXI PS Master GP1: Read Data
     .MAXIGP1RDATA   (RDATA),            // AXI PS Master GP1 RDATA[31:0], input
     .MAXIGP1RVALID  (RVALID),           // AXI PS Master GP1 RVALID, input
@@ -634,13 +594,13 @@ PS7 ps7_i (
     .MAXIGP1AWVALID (AWVALID),          // AXI PS Master GP1 AWVALID, output
     .MAXIGP1AWREADY (AWREADY),          // AXI PS Master GP1 AWREADY, input
     .MAXIGP1AWID    (AWID),             // AXI PS Master GP1 AWID[11:0], output
-    .MAXIGP1AWLOCK  (AWLOCK),           // AXI PS Master GP1 AWLOCK[1:0], output
-    .MAXIGP1AWCACHE (AWCACHE),          // AXI PS Master GP1 AWCACHE[3:0], output
-    .MAXIGP1AWPROT  (AWPROT),           // AXI PS Master GP1 AWPROT[2:0], output
+    .MAXIGP1AWLOCK  (),           // AXI PS Master GP1 AWLOCK[1:0], output
+    .MAXIGP1AWCACHE (),          // AXI PS Master GP1 AWCACHE[3:0], output
+    .MAXIGP1AWPROT  (),           // AXI PS Master GP1 AWPROT[2:0], output
     .MAXIGP1AWLEN   (AWLEN),            // AXI PS Master GP1 AWLEN[3:0], output
     .MAXIGP1AWSIZE  (AWSIZE),           // AXI PS Master GP1 AWSIZE[1:0], output
     .MAXIGP1AWBURST (AWBURST),          // AXI PS Master GP1 AWBURST[1:0], output
-    .MAXIGP1AWQOS   (AWQOS),            // AXI PS Master GP1 AWQOS[3:0], output
+    .MAXIGP1AWQOS   (),            // AXI PS Master GP1 AWQOS[3:0], output
 // AXI PS Master GP1: Write Data
     .MAXIGP1WDATA   (WDATA),            // AXI PS Master GP1 WDATA[31:0], output
     .MAXIGP1WVALID  (WVALID),           // AXI PS Master GP1 WVALID, output

host/command.v

@@ -185,7 +185,7 @@ begin
     sh_inter         <= rst ? 1'h0  : al_sh_inter_val_in      ? al_sh_inter_in     : tl_sh_inter_val_in      ? tl_sh_inter_in     : sh_inter;
     sh_dir           <= rst ? 1'h0  : al_sh_dir_val_in        ? al_sh_dir_in       : tl_sh_dir_val_in        ? tl_sh_dir_in       : sh_dir;
     sh_dma_id[31:0]  <= rst ? 32'h0 : al_sh_dma_id_lo_val_in  ? al_sh_dma_id_lo_in : tl_sh_dma_id_val_in ? tl_sh_dma_id_in[31:0]  : sh_dma_id[31:0];
-    sh_dma_id[63:32] <= rst ? 32'h0 : al_sh_dma_id_lo_val_in  ? al_sh_dma_id_hi_in : tl_sh_dma_id_val_in ? tl_sh_dma_id_in[63:32] : sh_dma_id[63:32];
+    sh_dma_id[63:32] <= rst ? 32'h0 : al_sh_dma_id_hi_val_in  ? al_sh_dma_id_hi_in : tl_sh_dma_id_val_in ? tl_sh_dma_id_in[63:32] : sh_dma_id[63:32];
     sh_dma_off       <= rst ? 32'h0 : al_sh_buf_off_val_in    ? al_sh_buf_off_in   : tl_sh_dma_off_val_in    ? tl_sh_dma_off_in   : sh_dma_off;
     sh_dma_cnt       <= rst ? 32'h0 : al_sh_dma_cnt_val_in    ? al_sh_dma_cnt_in   : tl_sh_dma_cnt_val_in    ? tl_sh_dma_cnt_in   : sh_dma_cnt;
     sh_tran_cnt      <= rst ? 16'h0 : al_sh_tran_cnt_val_in   ? al_sh_tran_cnt_in  : tl_sh_tran_cnt_val_in   ? tl_sh_tran_cnt_in  : sh_tran_cnt;
@@ -243,9 +243,9 @@ assign  tl_data_last_out = 1'b0;
 assign  tl_data_val_out = 1'b0;
 
 always @ (posedge clk)
-    waddr   <= rst ? 1'b0 : ~tl_data_val_in ? waddr : (raddr == waddr + 1'b1) ? waddr : waddr + 1'b1;
+    waddr   <= rst ? 10'b0 : ~tl_data_val_in ? waddr : (raddr == waddr + 1'b1) ? waddr : waddr + 1'b1;
 always @ (posedge clk)
-    raddr   <= rst ? 1'b0 : al_sh_data_strobe_in ? raddr + 1'b1 : raddr;
+    raddr   <= rst ? 10'b0 : al_sh_data_strobe_in ? raddr + 1'b1 : raddr;
 
 ram_1kx32_1kx32 rbuf(
       .rclk     (clk),      // clock for read port

host/gtx_10x8dec.v

@@ -80,6 +80,7 @@ begin
 end
 // overall expected disparity when the table values would apper - disp0_r. 
 // disp1_rr shows expected after 0st byte would be considered
+reg     correct_table_disp;
 wire    expected_disparity;
 wire    expected_disparity_interm;
 
@@ -99,7 +100,6 @@ always @ (posedge clk)
     disparity <= rst ? 1'b0 : inv_disp1 ^ inv_disp0 ? ~disparity : disparity;
 
 // to correct disparity if once an error occured
-reg     correct_table_disp;
 always @ (posedge clk)
     correct_table_disp   <= rst ? 1'b0 : disperror[1] ? ~correct_table_disp : correct_table_disp;
 

host/gtx_comma_align.v

@@ -71,7 +71,7 @@ reg     [19:0] indata_r;
 wire    [38:0] window;
 always @ (posedge clk)
     indata_r <= indata;
-assign  window = {indata, indata_r};
+assign  window = {indata[18:0], indata_r};
 
 // there is only 1 matched subwindow due to 20-bit comma's non-repetative pattern
 wire    [19:0]  subwindow [19:0];

host/gtx_elastic.v

@@ -139,8 +139,8 @@ endgenerate
 //              wr_addr_r - write address some rclk ticks ago
 //  => we can say if the fifo have the possibility to be empty
 //     since actual wr_addr could only be incremented
-assign  full   = {wr_addr, 1'b0}  == rd_addr_r + 1'b1;
-assign  empty  = {wr_addr_r, 1'b0} == rd_addr;
+assign  full   = wr_addr   == rd_addr_r + 1'b1;
+assign  empty  = wr_addr_r == rd_addr;
 
 assign  outram = ram[rd_addr];
 
@@ -262,8 +262,6 @@ wire    skip_write;
 wire    rmv1_req_wclk;
 wire    rmv2_req_wclk;
 reg     next_prim_loaded;
-always @ (wclk)
-    next_prim_loaded <= state_wait_next_p;
 
 wire    state_bypass_rmv;
 reg     state_wait1_align;
@@ -285,6 +283,9 @@ wire    clr_skip2_align;
 wire    clr_wait_next_p;
 wire    clr_send_ack;
 
+always @ (wclk)
+    next_prim_loaded <= state_wait_next_p;
+
 assign  state_bypass_rmv = ~state_wait1_align & ~state_skip1_align & ~state_wait2_align & ~state_skip2_align & ~state_wait_next_p & ~state_send_ack;
 
 assign  set_wait1_align = state_bypass_rmv & rmv1_req_wclk & ~rmv2_req_wclk;
@@ -372,13 +373,13 @@ assign  align_2nd = outram[15:0]  == 16'h7B4A
                   & outram[21:20] == 2'b00;
 // whole align primitive is the last thing we read from fifo
 reg     read_align;
+wire    pause_read;
 always @ (posedge rclk)
     read_align  <= rst ? 1'b0 : pause_read | align_1st & align_2nd;
 
 
 // just to alternate alignp's words, = 0 => 1st word, = 1 => 2nd word
 reg     align_altern;
-wire    pause_read;
 
 // also pause when offset gets ok, but only 1st word of alignp is sent - need to send 2nd word
 assign  pause_read = read_align & offset_less & fifo_stable | align_altern;

host/gtx_wrap.v

@@ -30,8 +30,7 @@ module gtx_wrap #(
     parameter RXCDRPHRESET_TIME   = 5'h1,
     parameter RXCDRFREQRESET_TIME = 5'h1,
     parameter RXDFELPMRESET_TIME  = 7'hf,
-    parameter RXISCANRESET_TIME   = 5'h1,
-    parameter RXEYERESET_TIME     = 7'h25
+    parameter RXISCANRESET_TIME   = 5'h1
 )
 (
     output  wire    cplllock,
@@ -74,7 +73,11 @@ module gtx_wrap #(
     output  wire    [DATA_BYTE_WIDTH - 1:0]     rxdisperr
 );
 
-// resets while PCS resets
+wire    rxresetdone_gtx; 
+wire    txresetdone_gtx; 
+wire    wrap_rxreset_;
+wire    wrap_txreset_;
+// resets while PCS resets, active low
 assign  wrap_rxreset_ = rxuserrdy & rxresetdone_gtx;
 assign  wrap_txreset_ = txuserrdy & txresetdone_gtx;
 
@@ -149,6 +152,8 @@ if (DATA_BYTE_WIDTH == 4) begin
     )
     txdata_resynchro(
         .rst        (txreset),
+        .rrst       (txreset),
+        .wrst       (txreset),
         .rclk       (txusrclk),
         .wclk       (txusrclk2),
         .we         (1'b1),
@@ -166,8 +171,8 @@ end
 else
 if (DATA_BYTE_WIDTH == 2) begin
     // no resync is needed => straightforward assignments
-    assign  txdata_enc_in       = txdata;
-    assign  txcharisk_enc_in    = txcharisk;
+    assign  txdata_enc_in       = txdata[15:0];
+    assign  txcharisk_enc_in    = txcharisk[1:0];
     assign  txcominit_gtx       = txcominit;
     assign  txcomwake_gtx       = txcomwake;
     assign  txelecidle_gtx      = txelecidle;
@@ -261,6 +266,8 @@ wire    [1:0]   rxnotintable_els_out;
 wire    [1:0]   rxdisperr_els_out;
 wire            lword_strobe;
 wire            isaligned;
+wire            elastic_full;
+wire            elastic_empty;
 
 gtx_elastic #(
     .DEPTH_LOG2 (3),
@@ -302,8 +309,6 @@ gtx_elastic(
 */
 wire    rxcomwakedet_gtx;
 wire    rxcominitdet_gtx;
-wire    rxresetdone_gtx; 
-wire    txresetdone_gtx; 
 
 
 // insert resync if it's necessary
@@ -335,7 +340,7 @@ if (DATA_BYTE_WIDTH == 4) begin
                                 rxdata_els_out,                        // 16
                                 rxdata_resync_buf[21:0]};              // 22 / 51 total
     always @ (posedge rxusrclk)
-        rxdata_resync_buf    <= ~wrap_rxreset_ ? 36'h0 : ~rxdata_resync_strobe ? {elastic_full, elastic_empty, rxdisperr_els_out, rxnotintable_els_out, rxcharisk_els_out, rxdata_els_out} : rxdata_resync_buf;
+        rxdata_resync_buf    <= ~wrap_rxreset_ ? 24'h0 : ~rxdata_resync_strobe ? {elastic_full, elastic_empty, rxdisperr_els_out, rxnotintable_els_out, rxcharisk_els_out, rxdata_els_out} : rxdata_resync_buf;
 
     always @ (posedge rxusrclk2)
         rxdata_resync_nempty_r <= rxdata_resync_nempty;
@@ -346,6 +351,8 @@ if (DATA_BYTE_WIDTH == 4) begin
     )
     rxdata_resynchro(
         .rst        (~wrap_rxreset_),
+        .rrst       (~wrap_rxreset_),
+        .wrst       (~wrap_rxreset_),
         .rclk       (rxusrclk2),
         .wclk       (rxusrclk),
         .we         (rxdata_resync_strobe),
@@ -362,10 +369,10 @@ if (DATA_BYTE_WIDTH == 4) begin
     assign  txresetdone     = rxdata_resync_out[46];
     assign  rxelsfull       = rxdata_resync_out[45];
     assign  rxelsempty      = rxdata_resync_out[44];
-    assign  rxdisperr       = {rxdata_resync_out[43:42], rxdata_resync_out[20:20]};
-    assign  rxnotintable    = {rxdata_resync_out[41:40], rxdata_resync_out[19:18]};
-    assign  rxcharisk       = {rxdata_resync_out[39:38], rxdata_resync_out[17:16]};
-    assign  rxdata          = {rxdata_resync_out[37:22], rxdata_resync_out[15:0] };
+    assign  rxdisperr[3:0]      = {rxdata_resync_out[43:42], rxdata_resync_out[21:20]};
+    assign  rxnotintable[3:0]   = {rxdata_resync_out[41:40], rxdata_resync_out[19:18]};
+    assign  rxcharisk[3:0]      = {rxdata_resync_out[39:38], rxdata_resync_out[17:16]};
+    assign  rxdata[31:0]        = {rxdata_resync_out[37:22], rxdata_resync_out[15:0] };
 end
 else
 if (DATA_BYTE_WIDTH == 2) begin
@@ -375,12 +382,12 @@ if (DATA_BYTE_WIDTH == 2) begin
     assign  rxcominitdet    = rxcominitdet_gtx;
     assign  rxresetdone     = rxresetdone_gtx;
     assign  txresetdone     = txresetdone_gtx;
-    assign  rxelsfull       = elastic_full;
-    assign  rxelsempty      = elastic_empty;
-    assign  rxdisperr       = rxdisperr_els_out;
-    assign  rxnotintable    = rxnotintable_els_out;
-    assign  rxcharisk       = rxcharisk_els_out;
-    assign  rxdata          = rxdata_els_out;
+    assign  rxelsfull           = elastic_full;
+    assign  rxelsempty          = elastic_empty;
+    assign  rxdisperr[1:0]      = rxdisperr_els_out;
+    assign  rxnotintable[1:0]   = rxnotintable_els_out;
+    assign  rxcharisk[1:0]      = rxcharisk_els_out;
+    assign  rxdata[15:0]        = rxdata_els_out;
 end
 else begin
     // unconsidered case
@@ -601,12 +608,12 @@ gtxe2_channel_wrapper(
     .CPLLREFCLKLOST                 (),
     .CPLLREFCLKSEL                  (3'b001),
     .CPLLRESET                      (cpllreset),
-    .GTRSVD                         (1'b0),
-    .PCSRSVDIN                      (1'b0),
-    .PCSRSVDIN2                     (1'b0),
-    .PMARSVDIN                      (1'b0),
-    .PMARSVDIN2                     (1'b0),
-    .TSTIN                          (1'b1),
+    .GTRSVD                         (16'b0),
+    .PCSRSVDIN                      (16'b0),
+    .PCSRSVDIN2                     (5'b0),
+    .PMARSVDIN                      (5'b0),
+    .PMARSVDIN2                     (5'b0),
+    .TSTIN                          (20'h1),
     .TSTOUT                         (),
     .CLKRSVD                        (4'b0000),
     .GTGREFCLK                      (1'b0),
@@ -768,7 +775,7 @@ gtxe2_channel_wrapper(
     .TXCHARDISPVAL                  (txchardispval_gtx),
     .TXUSRCLK                       (txusrclk),
     .TXUSRCLK2                      (txusrclk),
-    .TXELECIDLE                     (txelecidle),
+    .TXELECIDLE                     (txelecidle_gtx),
     .TXMARGIN                       (3'd0),
     .TXRATE                         (3'd0),
     .TXSWING                        (1'b0),

host/link.v

@@ -100,6 +100,7 @@ module link #(
     output  wire    [DATA_BYTE_WIDTH*8 - 1:0] phy_data_out,
     output  wire    [DATA_BYTE_WIDTH   - 1:0] phy_isk_out // charisk
 );
+wire    frame_done;
 // scrambled data
 wire    [DATA_BYTE_WIDTH*8 - 1:0]   scrambler_out;
 wire    dec_err; // doc, p.311 
@@ -109,15 +110,11 @@ wire    crc_bad;
 // current crc
 wire    [31:0] crc_dword; 
 
-reg     data_txing; // if there are still some data to transmit and the transaction wasn't cancelled
-always @ (posedge clk)
-    data_txing <= rst | (data_last_in & data_strobe_out | dword_val & rcvd_dword[CODE_DMATP]) ? 1'b0 : frame_req ? 1'b1 : data_txing;
-
 // send primitives variety count, including CRC and DATA as primitives
 localparam  PRIM_NUM = 15;
-// list of bits of rcvd_dword
 wire    [PRIM_NUM - 1:0] rcvd_dword; // shows current processing primitive (or just data dword)
-wire                    dword_val;
+wire                     dword_val;
+// list of bits of rcvd_dword
 localparam  CODE_DATA   = 0;
 localparam  CODE_CRC    = 1;
 localparam  CODE_SYNCP  = 2;
@@ -134,6 +131,9 @@ localparam  CODE_DMATP  = 12;
 localparam  CODE_OKP    = 13;
 localparam  CODE_ERRP   = 14;
 
+reg                      data_txing; // if there are still some data to transmit and the transaction wasn't cancelled
+always @ (posedge clk)
+    data_txing <= rst | (data_last_in & data_strobe_out | dword_val & rcvd_dword[CODE_DMATP]) ? 1'b0 : frame_req ? 1'b1 : data_txing;
 
 // fsm
 // states and transitions are taken from the doc, "Link Layer State Machine" chapter
@@ -391,21 +391,21 @@ generate
 if (DATA_BYTE_WIDTH == 2)
 begin
     reg     prim_word; // word counter in a primitive TODO logic
-    assign  prim_data[CODE_SYNCP]     =  prim_word ? PRIM_SYNCP_HI    : PRIM_SYNCP_LO;
-    assign  prim_data[CODE_ALIGNP]    =  prim_word ? PRIM_ALIGNP_HI   : PRIM_ALIGNP_LO;
-    assign  prim_data[CODE_XRDYP]     =  prim_word ? PRIM_XRDYP_HI    : PRIM_XRDYP_LO;
-    assign  prim_data[CODE_SOFP]      =  prim_word ? PRIM_SOFP_HI     : PRIM_SOFP_LO;
-    assign  prim_data[CODE_DATA]      =  scrambler_out;
-    assign  prim_data[CODE_HOLDAP]    =  prim_word ? PRIM_HOLDAP_HI   : PRIM_HOLDAP_LO;
-    assign  prim_data[CODE_HOLDP]     =  prim_word ? PRIM_HOLDP_HI    : PRIM_HOLDP_LO;
-    assign  prim_data[CODE_CRC]       =  scrambler_out;
-    assign  prim_data[CODE_EOFP]      =  prim_word ? PRIM_EOFP_HI     : PRIM_EOFP_LO;
-    assign  prim_data[CODE_WTRMP]     =  prim_word ? PRIM_WTRMP_HI    : PRIM_WTRMP_LO;
-    assign  prim_data[CODE_RRDYP]     =  prim_word ? PRIM_RRDYP_HI    : PRIM_RRDYP_LO;
-    assign  prim_data[CODE_IPP]       =  prim_word ? PRIM_IPP_HI      : PRIM_IPP_LO;
-    assign  prim_data[CODE_DMATP]     =  prim_word ? PRIM_DMATP_HI    : PRIM_DMATP_LO;
-    assign  prim_data[CODE_OKP]       =  prim_word ? PRIM_OKP_HI      : PRIM_OKP_LO;
-    assign  prim_data[CODE_ERRP]      =  prim_word ? PRIM_ERRP_HI     : PRIM_ERRP_LO;
+    assign  prim_data[CODE_SYNCP] [15:0]    =  prim_word ? PRIM_SYNCP_HI    : PRIM_SYNCP_LO;
+    assign  prim_data[CODE_ALIGNP][15:0]    =  prim_word ? PRIM_ALIGNP_HI   : PRIM_ALIGNP_LO;
+    assign  prim_data[CODE_XRDYP] [15:0]    =  prim_word ? PRIM_XRDYP_HI    : PRIM_XRDYP_LO;
+    assign  prim_data[CODE_SOFP]  [15:0]    =  prim_word ? PRIM_SOFP_HI     : PRIM_SOFP_LO;
+    assign  prim_data[CODE_DATA]  [15:0]    =  scrambler_out[15:0];
+    assign  prim_data[CODE_HOLDAP][15:0]    =  prim_word ? PRIM_HOLDAP_HI   : PRIM_HOLDAP_LO;
+    assign  prim_data[CODE_HOLDP] [15:0]    =  prim_word ? PRIM_HOLDP_HI    : PRIM_HOLDP_LO;
+    assign  prim_data[CODE_CRC]   [15:0]    =  scrambler_out[15:0];
+    assign  prim_data[CODE_EOFP]  [15:0]    =  prim_word ? PRIM_EOFP_HI     : PRIM_EOFP_LO;
+    assign  prim_data[CODE_WTRMP] [15:0]    =  prim_word ? PRIM_WTRMP_HI    : PRIM_WTRMP_LO;
+    assign  prim_data[CODE_RRDYP] [15:0]    =  prim_word ? PRIM_RRDYP_HI    : PRIM_RRDYP_LO;
+    assign  prim_data[CODE_IPP]   [15:0]    =  prim_word ? PRIM_IPP_HI      : PRIM_IPP_LO;
+    assign  prim_data[CODE_DMATP] [15:0]    =  prim_word ? PRIM_DMATP_HI    : PRIM_DMATP_LO;
+    assign  prim_data[CODE_OKP]   [15:0]    =  prim_word ? PRIM_OKP_HI      : PRIM_OKP_LO;
+    assign  prim_data[CODE_ERRP]  [15:0]    =  prim_word ? PRIM_ERRP_HI     : PRIM_ERRP_LO;
     always @ (posedge clk)
     begin
         $display("%m: unsupported data width");
@@ -577,7 +577,6 @@ assign  rcvd_dword[CODE_ERRP]	= phy_isk_in[0] == 1'b1 & ~|phy_isk_in[DATA_BYTE_W
 assign  dec_err = |phy_err_in;
 
 // form a response to transport layer
-wire    frame_done;
 assign  frame_done      = frame_done_good | frame_done_bad;
 assign  frame_done_good = state_wait & dword_val & rcvd_dword[CODE_OKP];
 assign  frame_done_bad  = state_wait & dword_val & rcvd_dword[CODE_ERRP];

host/oob.v

@@ -411,7 +411,7 @@ end
 `endif
 
 always @ (posedge clk)
-    rxcom_timer <= rst | rxcominit_done & state_wait_cominit | rxcomwake_done & state_wait_comwake | rxcominitdet & state_wait_cominit | rxcomwakedet & state_wait_comwake ? 10'h0 : cominit_req_l & state_idle | rxcominitdet_l & state_wait_cominit | rxcomwakedet_l & state_wait_comwake ? rxcom_timer + CLK_TO_TIMER_CONTRIB : 10'h0;
+    rxcom_timer <= rst | rxcominit_done & state_wait_cominit | rxcomwake_done & state_wait_comwake | rxcominitdet & state_wait_cominit | rxcomwakedet & state_wait_comwake ? 10'h0 : cominit_req_l & state_idle | rxcominitdet_l & state_wait_cominit | rxcomwakedet_l & state_wait_comwake ? rxcom_timer + CLK_TO_TIMER_CONTRIB[9:0] : 10'h0;
 
 // set data outputs to gtx
 assign  txdata_out    = txdata;
@@ -420,7 +420,7 @@ assign  txcharisk_out = txcharisk;
 // rxelectidle timer logic
 assign  eidle_timer_done = eidle_timer == 64;
 always @ (posedge clk)
-    eidle_timer <= rst | rxelecidle | ~state_wait_eidle ? 8'b0 : eidle_timer + CLK_TO_TIMER_CONTRIB;
+    eidle_timer <= rst | rxelecidle | ~state_wait_eidle ? 8'b0 : eidle_timer + CLK_TO_TIMER_CONTRIB[7:0];
 
 
 endmodule

host/sata_host.v

@@ -147,7 +147,6 @@ wire    [7:0]   tl2cl_sh_status;
 wire    [7:0]   tl2cl_sh_estatus; // E_Status
 wire    [7:0]   tl2cl_sh_dev;
 wire    [3:0]   tl2cl_sh_port;
-wire            tl2cl_shter_in;
 wire            tl2cl_sh_dir;
 wire            tl2cl_sh_inter;
 wire    [63:0]  tl2cl_sh_dma_id;
@@ -164,7 +163,6 @@ wire            tl2cl_sh_status_val;
 wire            tl2cl_sh_estatus_val; // E_Status
 wire            tl2cl_sh_dev_val;
 wire            tl2cl_sh_port_val;
-wire            tl2cl_shter_val_in;
 wire            tl2cl_sh_dir_val;
 wire            tl2cl_sh_inter_val;
 wire            tl2cl_sh_dma_id_val;
@@ -560,7 +558,7 @@ transport transport(
 
 
 // oob sequence is reinitiated and link now is not established or rxelecidle
-wire    link_reset;
+//wire    link_reset; // use ~phy_ready instead
 
 // phy is ready - link is established
 wire    phy_ready;

host/sata_phy.v

@@ -61,6 +61,10 @@ wire    [DATA_BYTE_WIDTH - 1:0]     txcharisk;
 wire    [DATA_BYTE_WIDTH - 1:0]     rxcharisk;
 wire    [DATA_BYTE_WIDTH - 1:0]     txcharisk_in;
 wire    [DATA_BYTE_WIDTH - 1:0]     rxcharisk_out;
+wire    [DATA_BYTE_WIDTH - 1:0]     rxdisperr;
+wire    [DATA_BYTE_WIDTH - 1:0]     rxnotintable;
+
+assign  ll_err_out = rxdisperr | rxnotintable;
 
 // once gtx_ready -> 1, gtx_configured latches
 // after this point it's possible to perform additional resets and reconfigurations by higher-level logic
@@ -170,7 +174,7 @@ localparam  RXEYERESET_TIME     = 7'h0 + RXPMARESET_TIME + RXCDRPHRESET_TIME + R
 reg     [6:0]   rxeyereset_cnt;
 assign  rxeyereset_done = rxeyereset_cnt == RXEYERESET_TIME;
 always @ (posedge gtrefclk)
-    rxeyereset_cnt  <= rxreset ? 3'h0 : rxeyereset_done ? rxeyereset_cnt : rxeyereset_cnt + 1'b1;
+    rxeyereset_cnt  <= rxreset ? 7'h0 : rxeyereset_done ? rxeyereset_cnt : rxeyereset_cnt + 1'b1;
 
 /*
  * Resets
@@ -322,8 +326,7 @@ gtx_wrap #(
     .RXCDRPHRESET_TIME      (RXCDRPHRESET_TIME),
     .RXCDRFREQRESET_TIME    (RXCDRFREQRESET_TIME),
     .RXDFELPMRESET_TIME     (RXDFELPMRESET_TIME),
-    .RXISCANRESET_TIME      (RXISCANRESET_TIME),
-    .RXEYERESET_TIME        (RXEYERESET_TIME)
+    .RXISCANRESET_TIME      (RXISCANRESET_TIME)
 )
 gtx_wrap
 (
@@ -360,7 +363,9 @@ gtx_wrap
     .txdata             (txdata),
     .txcharisk          (txcharisk),
     .rxdata             (rxdata),
-    .rxcharisk          (rxcharisk)
+    .rxcharisk          (rxcharisk),
+    .rxdisperr          (rxdisperr),
+    .rxnotintable       (rxnotintable)
 );
 /*
  * Interfaces

host/transport.v

@@ -176,6 +176,8 @@ module transport #(
     output  wire    watchdog_dwords
 );
 
+reg [7:0]   state;
+
 //TODO
 assign sync_escape_req = 1'b0;
 assign incom_stop_req = 1'b0;
@@ -221,8 +223,6 @@ localparam [2:0] CMD_TYPE_DMA_SETUP   = 3'h2;
 localparam [2:0] CMD_TYPE_DATA        = 3'h3;
 localparam [2:0] CMD_TYPE_BIST_ACT    = 3'h4;
 
-// asserts after FIS is sent
-reg             cmd_done_f;
 // current header dword
 wire    [31:0]  ll_header_dword;
 // current dword shall be header's
@@ -237,9 +237,6 @@ reg     [13:0]  dword_cnt;
 assign  watchdog_dwords = dword_cnt == 14'd2049;
 // ask for a receiving termination in case of errors
 reg             incom_stop_req_timeout;
-// dma activate is received when its type met and no errors occurs
-assign  got_dma_activate        = state == STATE_INCOMING & cl_data_last_in & ll_data_val_in & ll_data_in[7:0] == 8'h39;
-assign  got_dma_activate_port   = {4{got_dma_activate}} & ll_data_in[11:8];
 
 // global TL fsm
 /*
@@ -287,8 +284,6 @@ localparam  STATE_OUT_BIST       = 8'hb0; // BIST Activate FIS Host to Device
 localparam  STATE_OUT_WAIT_RESP  = 8'hc0; // 
 localparam  STATE_IN_UNRECOG     = 8'hf0; // Unrecognized FIS from Device
 
-reg [7:0]   state;
-
 always @ (posedge clk)
     if (rst)
     begin
@@ -1127,17 +1122,17 @@ assign  header_regfis   = dword_cnt[2:0] == 3'h0 ?  {sh_feature_in[7:0], sh_comm
                        /*dword_cnt[2:0] == 3'h4 ?*/ {32'h0000}; // Reserved
 // DMA Setup FIS header
 wire    [31:0] header_dmas;
-assign  header_dmas     = dword_cnt[3:0] == 3'h0 ?  {8'h0, 8'h0, sh_autoact_in, sh_inter_in, sh_dir_in, 1'b0, cmd_port_r, 8'h41} : // Reserved, Reserved, A I D R PMPort, FIS Type
-                          dword_cnt[3:0] == 3'h1 ?  {sh_dma_id_in[31:0]} : // DMA Buffer Identifier Low
-                          dword_cnt[3:0] == 3'h2 ?  {sh_dma_id_in[63:32]} : // DMA Buffer Identifier High
-                          dword_cnt[3:0] == 3'h4 ?  {sh_buf_off_in[31:0]} : // DMA Buffer Offset
-                          dword_cnt[3:0] == 3'h5 ?  {sh_dma_cnt_in[31:0]} : // DMA Transfer Count
-                                  /* 3'h3 | 3'h6 */ {32'h0000}; // Reserved
+assign  header_dmas     = dword_cnt[3:0] == 4'h0 ?  {8'h0, 8'h0, sh_autoact_in, sh_inter_in, sh_dir_in, 1'b0, cmd_port_r, 8'h41} : // Reserved, Reserved, A I D R PMPort, FIS Type
+                          dword_cnt[3:0] == 4'h1 ?  {sh_dma_id_in[31:0]} : // DMA Buffer Identifier Low
+                          dword_cnt[3:0] == 4'h2 ?  {sh_dma_id_in[63:32]} : // DMA Buffer Identifier High
+                          dword_cnt[3:0] == 4'h4 ?  {sh_buf_off_in[31:0]} : // DMA Buffer Offset
+                          dword_cnt[3:0] == 4'h5 ?  {sh_dma_cnt_in[31:0]} : // DMA Transfer Count
+                                  /* 4'h3 | 4'h6 */ {32'h0000}; // Reserved
 // BIST Activate FIS header
 wire    [31:0] header_bist; // TODO
-assign  header_bist     = dword_cnt[3:0] == 3'h0 ?  {8'h00, 8'h00, 4'h0, cmd_port_r, 8'h58} : // Reserved, T A S L F P R V, R R R R PMPort, FIS Type
-                          dword_cnt[3:0] == 3'h1 ?  {32'h00000000} : // Data1
-                          dword_cnt[3:0] == 3'h2 ?  {32'h00000000} : // Data2
+assign  header_bist     = dword_cnt[2:0] == 3'h0 ?  {8'h00, 8'h00, 4'h0, cmd_port_r, 8'h58} : // Reserved, T A S L F P R V, R R R R PMPort, FIS Type
+                          dword_cnt[2:0] == 3'h1 ?  {32'h00000000} : // Data1
+                          dword_cnt[2:0] == 3'h2 ?  {32'h00000000} : // Data2
                                                     {32'h00000000};
 // Data FIS header
 wire    [31:0] header_data;
@@ -1212,6 +1207,9 @@ assign  sh_tran_cnt_val_out = ll_data_last_in;
 assign  sh_notif_val_out    = ll_data_last_in;
 assign  sh_autoact_val_out  = ll_data_last_in;
 
+// dma activate is received when its type met and no errors occurs
+assign  got_dma_activate        = state == STATE_INCOMING & cl_data_last_in & ll_data_val_in & ll_data_in[7:0] == 8'h39;
+assign  got_dma_activate_port   = {4{got_dma_activate}} & ll_data_in[11:8];
 
 `ifdef CHECKERS_ENABLED
 always @ (posedge clk)

tb/tb_top.v

@@ -18,11 +18,11 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/> .
  *******************************************************************************/
-// set of global defines
+// global defines
 `define SIMULATION
-`define CHECKERS_ENABLED
 `define OPEN_SOURCE_ONLY
-
+`define PRELOAD_BRAMS
+`define CHECKERS_ENABLED
 /*
  * using x393_testbench01.tf style, contains a lot of copy-pasted code from there
  */
@@ -31,8 +31,8 @@
 //`include "sata_device.v"
 
 module tb #(
-`include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - not used
-`include "includes/x393_simulation_parameters.vh"
+`include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - partially used
+`include "includes/x393_simulation_parameters.vh" // SuppressThisWarning VEditor - partially used
 )
 (
 );
@@ -46,9 +46,13 @@ initial #1 $display("HI THERE");
 initial
 begin
     $dumpfile(lxtname);
-    $dumpvars(0,tb);
+    $dumpvars(0, tb);       // SuppressThisWarning VEditor - no idea why here was a warning
 end
 
+reg EXTCLK_P = 1'b1;
+reg EXTCLK_N = 1'b0;
+//reg serial_clk = 1'b1;
+
 reg     [11:0]  ARID_IN_r;
 reg     [31:0]  ARADDR_IN_r;
 reg     [3:0]   ARLEN_IN_r;
@@ -78,7 +82,7 @@ reg  [31:0] SIMUL_AXI_READ;
 reg  [SIMUL_AXI_READ_WIDTH-1:0] SIMUL_AXI_ADDR;
 // SuppressWarnings VEditor
 reg         SIMUL_AXI_FULL; // some data available
-wire        SIMUL_AXI_EMPTY= ~rvalid && rready && (rid==LAST_ARID); //SuppressThisWarning VEditor : may be unused, just for simulation // use it to wait for?
+wire        SIMUL_AXI_EMPTY;
 reg  [31:0] registered_rdata; // here read data from task
 
 //reg        CLK;
@@ -149,6 +153,7 @@ reg  [15:0] ENABLED_CHANNELS = 0; // currently enabled memory channels
 //  integer     SCANLINE_CUR_X;
 //  integer     SCANLINE_CUR_Y;
 wire AXI_RD_EMPTY=NUM_WORDS_READ==NUM_WORDS_EXPECTED; //SuppressThisWarning VEditor : may be unused, just for simulation
+assign  SIMUL_AXI_EMPTY= ~rvalid && rready && (rid==LAST_ARID); //SuppressThisWarning VEditor : may be unused, just for simulation // use it to wait for?
 
 wire [11:0]  #(AXI_TASK_HOLD) ARID_IN = ARID_IN_r;
 wire [31:0]  #(AXI_TASK_HOLD) ARADDR_IN = ARADDR_IN_r;
@@ -344,9 +349,6 @@ simul_axi_read #(
   .burst(),     // burst in progress - just debug
   .err_out());  // data last does not match predicted or FIFO over/under run - just debug
 
-reg EXTCLK_P = 1'b1;
-reg EXTCLK_N = 1'b0;
-reg serial_clk = 1'b1;
 
 // device-under-test instance
 wire    rxn;
@@ -547,8 +549,8 @@ simul_axi_hp_wr #(
     end
 
 //tasks
-`include "includes/x393_tasks01.vh"
-`include "includes/x393_tasks_afi.vh"
+`include "includes/x393_tasks01.vh"     // SuppressThisWarning VEditor - partially used
+`include "includes/x393_tasks_afi.vh"   // SuppressThisWarning VEditor - partially used
 
 /*
  * Monitor maxi bus read data. 
@@ -570,8 +572,8 @@ integer maxi_monitor_raddr  = 0;
 integer maxi_monitor_waddr  = 0;
 reg     maxi_monitor_fifo_empty = 1;
 
-function maxiMonitorIsEmpty(
-    input dummy
+function maxiMonitorIsEmpty( // SuppressThisWarning VEditor - it's ok
+    input dummy // SuppressThisWarning VEditor - it's ok
     );
     begin
         maxiMonitorIsEmpty = maxi_monitor_fifo_empty;
@@ -587,7 +589,7 @@ task maxiMonitorPop;
             $finish;
         end
         data = maxi_monitor_fifo[maxi_monitor_raddr][31:0]; // RDATA
-        id = maxi_monitor_fifo[maxi_monitor_raddr][43:32]; // RID
+        id = maxi_monitor_fifo[maxi_monitor_raddr][43:32]; // RID // SuppressThisWarning VEditor - it's ok
         maxi_monitor_raddr = (maxi_monitor_raddr + 1) % maxi_monitor_fifo_size;
         if (maxi_monitor_waddr == maxi_monitor_raddr) begin
             maxi_monitor_fifo_empty = 1;
@@ -620,6 +622,6 @@ initial forever @ (posedge CLK) begin
 end
 
 // testing itself
-`include  "test_top.v"
+`include  "test_top.v" // SuppressThisWarning VEditor - to avoid strange warnings
 
 endmodule

tb_top.sav

+[*]
+[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
+[*] Wed Sep  9 00:34:20 2015
+[*]
+[dumpfile] "/home/alexey/tmp/sata2/simulation/tb_top-20150908183150922.lxt"
+[dumpfile_mtime] "Wed Sep  9 00:32:03 2015"
+[dumpfile_size] 22508590
+[savefile] "/home/alexey/tmp/sata2/tb_top.sav"
+[timestart] 0
+[size] 1920 1145
+[pos] -919 -4
+*0.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] tb.
+[treeopen] tb.dut.
+[treeopen] tb.dut.sata_top.
+[treeopen] tb.dut.sata_top.sata_host.
+[sst_width] 202
+[signals_width] 214
+[sst_expanded] 1
+[sst_vpaned_height] 352
+@c00200
+-host link layer
+@28
+tb.dut.sata_top.sata_host.link.alignes_pair[0]
+tb.dut.sata_top.sata_host.link.alignes_pair_0[0]
+tb.dut.sata_top.sata_host.link.alignes_pair_1[0]
+@22
+tb.dut.sata_top.sata_host.link.alignes_timer[8:0]
+@28
+tb.dut.sata_top.sata_host.link.clk[0]
+tb.dut.sata_top.sata_host.link.clr_align[0]
+tb.dut.sata_top.sata_host.link.clr_nocomm[0]
+tb.dut.sata_top.sata_host.link.clr_nocommerr[0]
+tb.dut.sata_top.sata_host.link.clr_rcvr_badend[0]
+tb.dut.sata_top.sata_host.link.clr_rcvr_data[0]
+tb.dut.sata_top.sata_host.link.clr_rcvr_eof[0]
+tb.dut.sata_top.sata_host.link.clr_rcvr_goodcrc[0]
+tb.dut.sata_top.sata_host.link.clr_rcvr_goodend[0]
+tb.dut.sata_top.sata_host.link.clr_rcvr_rdy[0]
+tb.dut.sata_top.sata_host.link.clr_rcvr_rhold[0]
+tb.dut.sata_top.sata_host.link.clr_rcvr_shold[0]
+tb.dut.sata_top.sata_host.link.clr_rcvr_wait[0]
+tb.dut.sata_top.sata_host.link.clr_reset[0]
+tb.dut.sata_top.sata_host.link.clr_send_crc[0]
+tb.dut.sata_top.sata_host.link.clr_send_data[0]
+tb.dut.sata_top.sata_host.link.clr_send_eof[0]
+tb.dut.sata_top.sata_host.link.clr_send_rdy[0]
+tb.dut.sata_top.sata_host.link.clr_send_rhold[0]
+tb.dut.sata_top.sata_host.link.clr_send_shold[0]
+tb.dut.sata_top.sata_host.link.clr_send_sof[0]
+tb.dut.sata_top.sata_host.link.clr_sync_esc[0]
+tb.dut.sata_top.sata_host.link.clr_wait[0]
+tb.dut.sata_top.sata_host.link.crc_bad[0]
+@22
+tb.dut.sata_top.sata_host.link.crc_dword[31:0]
+@28
+tb.dut.sata_top.sata_host.link.crc_good[0]
+tb.dut.sata_top.sata_host.link.data_busy_in[0]
+@22
+tb.dut.sata_top.sata_host.link.data_in[31:0]
+@28
+tb.dut.sata_top.sata_host.link.data_last_in[0]
+tb.dut.sata_top.sata_host.link.data_last_out[0]
+tb.dut.sata_top.sata_host.link.data_mask_in[1:0]
+tb.dut.sata_top.sata_host.link.data_mask_out[1:0]
+@22
+tb.dut.sata_top.sata_host.link.data_out[31:0]
+tb.dut.sata_top.sata_host.link.data_out_r[31:0]
+tb.dut.sata_top.sata_host.link.data_out_rr[31:0]
+@28
+tb.dut.sata_top.sata_host.link.data_strobe_out[0]
+tb.dut.sata_top.sata_host.link.data_txing[0]
+tb.dut.sata_top.sata_host.link.data_val_in[0]
+tb.dut.sata_top.sata_host.link.data_val_out[0]
+tb.dut.sata_top.sata_host.link.data_val_out_r[0]
+tb.dut.sata_top.sata_host.link.data_val_out_rr[0]
+tb.dut.sata_top.sata_host.link.dec_err[0]
+tb.dut.sata_top.sata_host.link.dword_val[0]
+tb.dut.sata_top.sata_host.link.frame_ack[0]
+tb.dut.sata_top.sata_host.link.frame_busy[0]
+tb.dut.sata_top.sata_host.link.frame_done[0]
+tb.dut.sata_top.sata_host.link.frame_done_bad[0]
+tb.dut.sata_top.sata_host.link.frame_done_good[0]
+tb.dut.sata_top.sata_host.link.frame_rej[0]
+tb.dut.sata_top.sata_host.link.frame_req[0]
+tb.dut.sata_top.sata_host.link.got_escape[0]
+tb.dut.sata_top.sata_host.link.inc_is_data[0]
+tb.dut.sata_top.sata_host.link.incom_ack_bad[0]
+tb.dut.sata_top.sata_host.link.incom_ack_good[0]
+tb.dut.sata_top.sata_host.link.incom_done[0]
+tb.dut.sata_top.sata_host.link.incom_invalidate[0]
+tb.dut.sata_top.sata_host.link.incom_start[0]
+tb.dut.sata_top.sata_host.link.incom_stop_f[0]
+tb.dut.sata_top.sata_host.link.incom_stop_req[0]
+tb.dut.sata_top.sata_host.link.link_reset[0]
+@22
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+tb.dut.sata_top.sata_host.phy.txpcsreset_req[0]
+tb.dut.sata_top.sata_host.phy.txpcsreset_stop[0]
+tb.dut.sata_top.sata_host.phy.txpmareset_cnt[2:0]
+tb.dut.sata_top.sata_host.phy.txpmareset_done[0]
+tb.dut.sata_top.sata_host.phy.txreset[0]
+tb.dut.sata_top.sata_host.phy.txresetdone[0]
+tb.dut.sata_top.sata_host.phy.txuserrdy[0]
+tb.dut.sata_top.sata_host.phy.txusrclk2[0]
+tb.dut.sata_top.sata_host.phy.txusrclk[0]
+tb.dut.sata_top.sata_host.phy.usrclk2[0]
+tb.dut.sata_top.sata_host.phy.usrclk[0]
+tb.dut.sata_top.sata_host.phy.usrpll_fb_clk[0]
+tb.dut.sata_top.sata_host.phy.usrpll_locked[0]
+@1401200
+-host phy level
+@c00200
+-host transport level
+@28
+tb.dut.sata_top.sata_host.transport.bad_fis_received[0]
+tb.dut.sata_top.sata_host.transport.chk_inc_dword_limit_exceeded[0]
+tb.dut.sata_top.sata_host.transport.chk_strobe_while_waitresp[0]
+tb.dut.sata_top.sata_host.transport.cl_data_busy_in[0]
+@22
+tb.dut.sata_top.sata_host.transport.cl_data_in[31:0]
+@28
+tb.dut.sata_top.sata_host.transport.cl_data_last_in[0]
+tb.dut.sata_top.sata_host.transport.cl_data_last_out[0]
+tb.dut.sata_top.sata_host.transport.cl_data_mask_in[1:0]
+tb.dut.sata_top.sata_host.transport.cl_data_mask_out[1:0]
+@22
+tb.dut.sata_top.sata_host.transport.cl_data_out[31:0]
+@28
+tb.dut.sata_top.sata_host.transport.cl_data_strobe_out[0]
+tb.dut.sata_top.sata_host.transport.cl_data_val_in[0]
+tb.dut.sata_top.sata_host.transport.cl_data_val_out[0]
+tb.dut.sata_top.sata_host.transport.clk[0]
+tb.dut.sata_top.sata_host.transport.cmd_busy[0]
+tb.dut.sata_top.sata_host.transport.cmd_done_bad[0]
+tb.dut.sata_top.sata_host.transport.cmd_done_good[0]
+@22
+tb.dut.sata_top.sata_host.transport.cmd_port[3:0]
+tb.dut.sata_top.sata_host.transport.cmd_port_r[3:0]
+@28
+tb.dut.sata_top.sata_host.transport.cmd_type[2:0]
+tb.dut.sata_top.sata_host.transport.cmd_type_r[2:0]
+tb.dut.sata_top.sata_host.transport.cmd_val[0]
+tb.dut.sata_top.sata_host.transport.data_limit_exceeded[0]
+@22
+tb.dut.sata_top.sata_host.transport.dword_cnt[13:0]
+@28
+tb.dut.sata_top.sata_host.transport.frame_ack[0]
+tb.dut.sata_top.sata_host.transport.frame_busy[0]
+tb.dut.sata_top.sata_host.transport.frame_done_bad[0]
+tb.dut.sata_top.sata_host.transport.frame_done_good[0]
+tb.dut.sata_top.sata_host.transport.frame_rej[0]
+tb.dut.sata_top.sata_host.transport.frame_req[0]
+tb.dut.sata_top.sata_host.transport.got_dma_activate[0]
+@22
+tb.dut.sata_top.sata_host.transport.got_dma_activate_port[3:0]
+tb.dut.sata_top.sata_host.transport.header_bist[31:0]
+tb.dut.sata_top.sata_host.transport.header_data[31:0]
+tb.dut.sata_top.sata_host.transport.header_dmas[31:0]
+tb.dut.sata_top.sata_host.transport.header_regfis[31:0]
+@28
+tb.dut.sata_top.sata_host.transport.incom_ack_bad[0]
+tb.dut.sata_top.sata_host.transport.incom_ack_good[0]
+tb.dut.sata_top.sata_host.transport.incom_done[0]
+tb.dut.sata_top.sata_host.transport.incom_done_bad_r[0]
+tb.dut.sata_top.sata_host.transport.incom_done_r[0]
+tb.dut.sata_top.sata_host.transport.incom_invalidate[0]
+tb.dut.sata_top.sata_host.transport.incom_start[0]
+tb.dut.sata_top.sata_host.transport.incom_stop_req[0]
+tb.dut.sata_top.sata_host.transport.incom_stop_req_timeout[0]
+tb.dut.sata_top.sata_host.transport.ll_data_busy_out[0]
+@22
+tb.dut.sata_top.sata_host.transport.ll_data_in[31:0]
+@28
+tb.dut.sata_top.sata_host.transport.ll_data_last_in[0]
+tb.dut.sata_top.sata_host.transport.ll_data_last_out[0]
+tb.dut.sata_top.sata_host.transport.ll_data_mask_in[1:0]
+tb.dut.sata_top.sata_host.transport.ll_data_mask_out[1:0]
+@22
+tb.dut.sata_top.sata_host.transport.ll_data_out[31:0]
+@28
+tb.dut.sata_top.sata_host.transport.ll_data_strobe_in[0]
+tb.dut.sata_top.sata_host.transport.ll_data_val_in[0]
+tb.dut.sata_top.sata_host.transport.ll_data_val_out[0]
+@22
+tb.dut.sata_top.sata_host.transport.ll_header_dword[31:0]
+@28
+tb.dut.sata_top.sata_host.transport.ll_header_last[0]
+tb.dut.sata_top.sata_host.transport.ll_header_val[0]
+tb.dut.sata_top.sata_host.transport.loc_autoact[0]
+@22
+tb.dut.sata_top.sata_host.transport.loc_command[7:0]
+tb.dut.sata_top.sata_host.transport.loc_count[15:0]
+tb.dut.sata_top.sata_host.transport.loc_dev[7:0]
+@28
+tb.dut.sata_top.sata_host.transport.loc_dir[0]
+@22
+tb.dut.sata_top.sata_host.transport.loc_dma_cnt[31:0]
+tb.dut.sata_top.sata_host.transport.loc_dma_id[63:0]
+tb.dut.sata_top.sata_host.transport.loc_dma_off[31:0]
+tb.dut.sata_top.sata_host.transport.loc_err[7:0]
+tb.dut.sata_top.sata_host.transport.loc_estatus[7:0]
+@28
+tb.dut.sata_top.sata_host.transport.loc_inter[0]
+@22
+tb.dut.sata_top.sata_host.transport.loc_lba[47:0]
+@28
+tb.dut.sata_top.sata_host.transport.loc_notif[0]
+@22
+tb.dut.sata_top.sata_host.transport.loc_port[3:0]
+tb.dut.sata_top.sata_host.transport.loc_status[7:0]
+tb.dut.sata_top.sata_host.transport.loc_tran_cnt[15:0]
+@28
+tb.dut.sata_top.sata_host.transport.rst[0]
+tb.dut.sata_top.sata_host.transport.sh_autoact_in[0]
+tb.dut.sata_top.sata_host.transport.sh_autoact_out[0]
+tb.dut.sata_top.sata_host.transport.sh_autoact_val_out[0]
+@22
+tb.dut.sata_top.sata_host.transport.sh_buf_off_in[31:0]
+tb.dut.sata_top.sata_host.transport.sh_command_in[7:0]
+tb.dut.sata_top.sata_host.transport.sh_command_out[7:0]
+@28
+tb.dut.sata_top.sata_host.transport.sh_command_val_out[0]
+@22
+tb.dut.sata_top.sata_host.transport.sh_control_in[7:0]
+tb.dut.sata_top.sata_host.transport.sh_count_in[15:0]
+tb.dut.sata_top.sata_host.transport.sh_count_out[15:0]
+@28
+tb.dut.sata_top.sata_host.transport.sh_count_val_out[0]
+@22
+tb.dut.sata_top.sata_host.transport.sh_data_in[31:0]
+tb.dut.sata_top.sata_host.transport.sh_dev_in[7:0]
+tb.dut.sata_top.sata_host.transport.sh_dev_out[7:0]
+@28
+tb.dut.sata_top.sata_host.transport.sh_dev_val_out[0]
+tb.dut.sata_top.sata_host.transport.sh_dir_in[0]
+tb.dut.sata_top.sata_host.transport.sh_dir_out[0]
+tb.dut.sata_top.sata_host.transport.sh_dir_val_out[0]
+@22
+tb.dut.sata_top.sata_host.transport.sh_dma_cnt_in[31:0]
+tb.dut.sata_top.sata_host.transport.sh_dma_cnt_out[31:0]
+@28
+tb.dut.sata_top.sata_host.transport.sh_dma_cnt_val_out[0]
+@22
+tb.dut.sata_top.sata_host.transport.sh_dma_id_in[63:0]
+tb.dut.sata_top.sata_host.transport.sh_dma_id_out[63:0]
+@28
+tb.dut.sata_top.sata_host.transport.sh_dma_id_val_out[0]
+@22
+tb.dut.sata_top.sata_host.transport.sh_dma_off_out[31:0]
+@28
+tb.dut.sata_top.sata_host.transport.sh_dma_off_val_out[0]
+@22
+tb.dut.sata_top.sata_host.transport.sh_err_out[7:0]
+@28
+tb.dut.sata_top.sata_host.transport.sh_err_val_out[0]
+@22
+tb.dut.sata_top.sata_host.transport.sh_estatus_out[7:0]
+@28
+tb.dut.sata_top.sata_host.transport.sh_estatus_val_out[0]
+@22
+tb.dut.sata_top.sata_host.transport.sh_feature_in[15:0]
+@28
+tb.dut.sata_top.sata_host.transport.sh_inter_in[0]
+tb.dut.sata_top.sata_host.transport.sh_inter_out[0]
+tb.dut.sata_top.sata_host.transport.sh_inter_val_out[0]
+@22
+tb.dut.sata_top.sata_host.transport.sh_lba_in[47:0]
+tb.dut.sata_top.sata_host.transport.sh_lba_out[47:0]
+@28
+tb.dut.sata_top.sata_host.transport.sh_lba_val_out[0]
+tb.dut.sata_top.sata_host.transport.sh_notif_in[0]
+tb.dut.sata_top.sata_host.transport.sh_notif_out[0]
+tb.dut.sata_top.sata_host.transport.sh_notif_val_out[0]
+@22
+tb.dut.sata_top.sata_host.transport.sh_port_in[3:0]
+tb.dut.sata_top.sata_host.transport.sh_port_out[3:0]
+@28
+tb.dut.sata_top.sata_host.transport.sh_port_val_out[0]
+@22
+tb.dut.sata_top.sata_host.transport.sh_status_out[7:0]
+@28
+tb.dut.sata_top.sata_host.transport.sh_status_val_out[0]
+@22
+tb.dut.sata_top.sata_host.transport.sh_tran_cnt_in[15:0]
+tb.dut.sata_top.sata_host.transport.sh_tran_cnt_out[15:0]
+@28
+tb.dut.sata_top.sata_host.transport.sh_tran_cnt_val_out[0]
+@22
+tb.dut.sata_top.sata_host.transport.state[7:0]
+@28
+tb.dut.sata_top.sata_host.transport.sync_escape_ack[0]
+tb.dut.sata_top.sata_host.transport.sync_escape_req[0]
+tb.dut.sata_top.sata_host.transport.watchdog_dwords[0]
+tb.dut.sata_top.sata_host.transport.watchdog_eof[0]
+@1401200
+-host transport level
+@c00200
+-shadow registers
+@28
+tb.dut.sata_top.dma_regs.ACLK[0]
+@22
+tb.dut.sata_top.dma_regs.bram_raddr[31:0]
+tb.dut.sata_top.dma_regs.bram_raddr_r[7:0]
+tb.dut.sata_top.dma_regs.bram_rdata[31:0]
+tb.dut.sata_top.dma_regs.bram_rdata_r[31:0]
+@28
+tb.dut.sata_top.dma_regs.bram_regen[0]
+tb.dut.sata_top.dma_regs.bram_ren[0]
+@22
+tb.dut.sata_top.dma_regs.bram_waddr[31:0]
+tb.dut.sata_top.dma_regs.bram_wdata[31:0]
+@28
+tb.dut.sata_top.dma_regs.bram_wen[0]
+@22
+tb.dut.sata_top.dma_regs.bram_wstb[3:0]
+tb.dut.sata_top.dma_regs.cmd_in[31:0]
+tb.dut.sata_top.dma_regs.cmd_out[31:0]
+@28
+tb.dut.sata_top.dma_regs.cmd_val_out[0]
+tb.dut.sata_top.dma_regs.dma_done[0]
+tb.dut.sata_top.dma_regs.dma_done_aclk[0]
+tb.dut.sata_top.dma_regs.dma_issued[0]
+tb.dut.sata_top.dma_regs.dma_start[0]
+tb.dut.sata_top.dma_regs.dma_start_aclk[0]
+tb.dut.sata_top.dma_regs.dma_type[0]
+@22
+tb.dut.sata_top.dma_regs.lba[31:0]
+tb.dut.sata_top.dma_regs.mem_address[31:7]
+tb.dut.sata_top.dma_regs.reg00[31:0]
+tb.dut.sata_top.dma_regs.reg0c[31:0]
+tb.dut.sata_top.dma_regs.reg04[31:0]
+tb.dut.sata_top.dma_regs.reg08[31:0]
+tb.dut.sata_top.dma_regs.reg10[31:0]
+tb.dut.sata_top.dma_regs.reg14[31:0]
+@28
+tb.dut.sata_top.dma_regs.rst[0]
+tb.dut.sata_top.dma_regs.sclk[0]
+@22
+tb.dut.sata_top.dma_regs.sector_cnt[31:0]
+@28
+tb.dut.sata_top.dma_regs.sh_autoact[0]
+tb.dut.sata_top.dma_regs.sh_autoact_in[0]
+tb.dut.sata_top.dma_regs.sh_autoact_val[0]
+@22
+tb.dut.sata_top.dma_regs.sh_buf_off[31:0]
+@28
+tb.dut.sata_top.dma_regs.sh_buf_off_val[0]
+@22
+tb.dut.sata_top.dma_regs.sh_command[7:0]
+tb.dut.sata_top.dma_regs.sh_command_in[7:0]
+@28
+tb.dut.sata_top.dma_regs.sh_command_val[0]
+@22
+tb.dut.sata_top.dma_regs.sh_control[7:0]
+tb.dut.sata_top.dma_regs.sh_control_in[7:0]
+@28
+tb.dut.sata_top.dma_regs.sh_control_val[0]
+@22
+tb.dut.sata_top.dma_regs.sh_count[15:0]
+tb.dut.sata_top.dma_regs.sh_count_in[15:0]
+@28
+tb.dut.sata_top.dma_regs.sh_count_val[0]
+@22
+tb.dut.sata_top.dma_regs.sh_data[31:0]
+tb.dut.sata_top.dma_regs.sh_data_in[31:0]
+@28
+tb.dut.sata_top.dma_regs.sh_data_strobe[0]
+tb.dut.sata_top.dma_regs.sh_data_val[0]
+tb.dut.sata_top.dma_regs.sh_data_val_in[0]
+@22
+tb.dut.sata_top.dma_regs.sh_dev[7:0]
+tb.dut.sata_top.dma_regs.sh_dev_in[7:0]
+@28
+tb.dut.sata_top.dma_regs.sh_dev_val[0]
+tb.dut.sata_top.dma_regs.sh_dir[0]
+tb.dut.sata_top.dma_regs.sh_dir_in[0]
+tb.dut.sata_top.dma_regs.sh_dir_val[0]
+@22
+tb.dut.sata_top.dma_regs.sh_dma_cnt[31:0]
+tb.dut.sata_top.dma_regs.sh_dma_cnt_in[31:0]
+@28
+tb.dut.sata_top.dma_regs.sh_dma_cnt_val[0]
+@22
+tb.dut.sata_top.dma_regs.sh_dma_id_hi[31:0]
+@28
+tb.dut.sata_top.dma_regs.sh_dma_id_hi_val[0]
+@22
+tb.dut.sata_top.dma_regs.sh_dma_id_in[63:0]
+tb.dut.sata_top.dma_regs.sh_dma_id_lo[31:0]
+@28
+tb.dut.sata_top.dma_regs.sh_dma_id_lo_val[0]
+@22
+tb.dut.sata_top.dma_regs.sh_dma_off_in[31:0]
+tb.dut.sata_top.dma_regs.sh_err_in[7:0]
+tb.dut.sata_top.dma_regs.sh_estatus_in[7:0]
+tb.dut.sata_top.dma_regs.sh_feature[15:0]
+tb.dut.sata_top.dma_regs.sh_feature_in[15:0]
+@28
+tb.dut.sata_top.dma_regs.sh_feature_val[0]
+tb.dut.sata_top.dma_regs.sh_inter[0]
+tb.dut.sata_top.dma_regs.sh_inter_in[0]
+tb.dut.sata_top.dma_regs.sh_inter_val[0]
+@22
+tb.dut.sata_top.dma_regs.sh_lba_hi[23:0]
+@28
+tb.dut.sata_top.dma_regs.sh_lba_hi_val[0]
+@22
+tb.dut.sata_top.dma_regs.sh_lba_in[47:0]
+tb.dut.sata_top.dma_regs.sh_lba_lo[23:0]
+@28
+tb.dut.sata_top.dma_regs.sh_lba_lo_val[0]
+tb.dut.sata_top.dma_regs.sh_notif[0]
+tb.dut.sata_top.dma_regs.sh_notif_in[0]
+tb.dut.sata_top.dma_regs.sh_notif_val[0]
+@22
+tb.dut.sata_top.dma_regs.sh_port[3:0]
+tb.dut.sata_top.dma_regs.sh_port_in[3:0]
+@28
+tb.dut.sata_top.dma_regs.sh_port_val[0]
+@22
+tb.dut.sata_top.dma_regs.sh_status_in[7:0]
+tb.dut.sata_top.dma_regs.sh_tran_cnt[15:0]
+tb.dut.sata_top.dma_regs.sh_tran_cnt_in[15:0]
+@28
+tb.dut.sata_top.dma_regs.sh_tran_cnt_val[0]
+@22
+tb.dut.sata_top.dma_regs.wdata[31:0]
+@1401200
+-shadow registers
+[pattern_trace] 1
+[pattern_trace] 0

wrapper/GTXE2_GPL.v

 /*******************************************************************************
  * Module: GTXE2_GPL
- * Date: 2015-09-07
+ * Date: 2015-09-08
  * Author: Alexey     
  * Description: emulates GTXE2_CHANNEL primitive behaviour. 
  *              The file is gathered from multiple files
@@ -82,13 +82,13 @@ module gtxe2_chnl_cpll(
     output  wire    CPLLLOCK,
     output  wire    CPLLREFCLKLOST,
 
-    input   wire    GTRSVD,
-    input   wire    PCSRSVDIN,
-    input   wire    PCSRSVDIN2,
-    input   wire    PMARSVDIN,
-    input   wire    PMARSVDIN2,
-    input   wire    TSTIN,
-    output  wire    TSTOUT,
+    input   wire    [15:0]  GTRSVD,
+    input   wire    [15:0]  PCSRSVDIN,
+    input   wire    [4:0]   PCSRSVDIN2,
+    input   wire    [4:0]   PMARSVDIN,
+    input   wire    [4:0]   PMARSVDIN2,
+    input   wire    [19:0]  TSTIN,
+    output  wire            TSTOUT,
 
 // internal
     input   wire    ref_clk,
@@ -284,7 +284,16 @@ module gtxe2_chnl_clocking(
     output  wire            RXOUTCLK,
     output  wire            RXOUTCLKFABRIC,
     output  wire            rx_serial_clk,
-    output  wire            tx_sipo_clk
+    output  wire            rx_sipo_clk,
+
+// additional ports to cpll
+    output              TSTOUT,
+    input   [15:0]      GTRSVD,
+    input   [15:0]      PCSRSVDIN,
+    input   [4:0]       PCSRSVDIN2,
+    input   [4:0]       PMARSVDIN,
+    input   [4:0]       PMARSVDIN2,
+    input   [19:0]      TSTIN
 );
 // CPLL
 parameter   [23:0]  CPLL_CFG        = 29'h00BC07DC;
@@ -365,7 +374,6 @@ tx_toserialclk_div(
 
     .div        (tx_serial_divider)
 );
-wire    rx_sipo_clk;
 clock_divider #(
 //    .divide_by  (rx_serial_divider),
     .divide_by_param (0)
@@ -385,6 +393,7 @@ clock_divider #(
     .divide_by (tx_pma_divider1)
 )
 tx_pma_div1(
+    .div        (1),
     .clk_in     (tx_piso_clk),
     .clk_out    (tx_pma_div1_clk)
 );
@@ -393,6 +402,7 @@ clock_divider #(
     .divide_by (tx_pma_divider2)
 )
 tx_pma_div2(
+    .div        (1),
     .clk_in     (tx_pma_div1_clk),
     .clk_out    (TXOUTCLKPMA)
 );
@@ -404,6 +414,7 @@ clock_divider #(
     .divide_by  (rx_pma_divider1)
 )
 rx_pma_div1(
+    .div        (1),
     .clk_in     (rx_sipo_clk),
     .clk_out    (rx_pma_div1_clk)
 );
@@ -412,6 +423,7 @@ clock_divider #(
     .divide_by  (rx_pma_divider2)
 )
 rx_pma_div2(
+    .div        (1),
     .clk_in     (rx_pma_div1_clk),
     .clk_out    (RXOUTCLKPMA)
 );
@@ -421,6 +433,7 @@ clock_divider #(
     .divide_by  (2)
 )
 txpllrefclk_div2(
+    .div        (1),
     .clk_in     (TXPLLREFCLK_DIV1),
     .clk_out    (TXPLLREFCLK_DIV2)
 );
@@ -428,6 +441,7 @@ clock_divider #(
     .divide_by  (2)
 )
 rxpllrefclk_div2(
+    .div        (1),
     .clk_in     (RXPLLREFCLK_DIV1),
     .clk_out    (RXPLLREFCLK_DIV2)
 );
@@ -491,7 +505,7 @@ cpll(
     
     .ref_clk            (clk_mux_out),
     .clk_out            (cpll_clk_out),
-    .pll_locked         (pll_locked)
+    .pll_locked         ()
 );
 
 endmodule
@@ -1030,6 +1044,7 @@ wire [internal_data_width - 1:0]    dataiface_data_out;
 wire [interface_data_width - 1:0]   dataiface_data_in;
 
 //assign  dataiface_data_in  = {TXCHARDISPMODE[interface_isk_width - 1:0], TXCHARDISPVAL[interface_isk_width - 1:0], TXDATA[iface_databus_width - 1:0]};
+genvar ii;
 localparam outdiv = interface_data_width / internal_data_width;
 generate
 for (ii = 1; ii < (outdiv + 1); ii = ii + 1)
@@ -1066,7 +1081,6 @@ dataiface
 wire    [internal_data_width - 1:0] polarized_data;
 
 // invert data (get words as [abdceifghj] after 8/10, each word shall be transmitter in a reverse bit order)
-genvar ii;
 genvar jj;
 generate
     for (ii = 0; ii < internal_data_width; ii = ii + 10)
@@ -1230,6 +1244,7 @@ wire                    full_wr;
 wire                    val_wr;
 wire                    val_rd;
 wire                    bitcounter_limit;
+wire                    almost_empty_rd;
 
 assign  bitcounter_limit = trim ? bitcounter == (trimmed_width - 1) : bitcounter == (width - 1);
 
@@ -1665,27 +1680,6 @@ always @ (posedge clk)
 wire    [comma_width - 1:0] comma_window [window_size - 1:0];
 //initial
 //  for (idx = 0; idx < window_size; idx = idx + 1) $dumpvars(0, comma_width[idx]);
-wire    [comma_width - 1:0] comma_window0 = comma_window[0];
-wire    [comma_width - 1:0] comma_window1 = comma_window[1];
-wire    [comma_width - 1:0] comma_window2 = comma_window[2];
-wire    [comma_width - 1:0] comma_window3 = comma_window[3];
-wire    [comma_width - 1:0] comma_window4 = comma_window[4];
-wire    [comma_width - 1:0] comma_window5 = comma_window[5];
-wire    [comma_width - 1:0] comma_window6 = comma_window[6];
-wire    [comma_width - 1:0] comma_window7 = comma_window[7];
-wire    [comma_width - 1:0] comma_window8 = comma_window[8];
-wire    [comma_width - 1:0] comma_window9 = comma_window[9];
-wire    [comma_width - 1:0] comma_window10 = comma_window[10];
-wire    [comma_width - 1:0] comma_window11 = comma_window[11];
-wire    [comma_width - 1:0] comma_window12 = comma_window[12];
-wire    [comma_width - 1:0] comma_window13 = comma_window[13];
-wire    [comma_width - 1:0] comma_window14 = comma_window[14];
-wire    [comma_width - 1:0] comma_window15 = comma_window[15];
-wire    [comma_width - 1:0] comma_window16 = comma_window[16];
-wire    [comma_width - 1:0] comma_window17 = comma_window[17];
-wire    [comma_width - 1:0] comma_window18 = comma_window[18];
-wire    [comma_width - 1:0] comma_window19 = comma_window[19];
-
 wire    [window_size - 1:0] comma_match; // shows all matches
 wire    [window_size - 1:0] comma_pos; // shows the first match
 wire    [window_size - 1:0] pcomma_match;
@@ -1763,7 +1757,7 @@ assign  RXBYTEREALIGN = RXCOMMADETEN & is_aligned & pointer_set;
 always @ (posedge clk)
 begin
     is_aligned      <= rst | pointer_set === 1'bx | rxelecidle ? 1'b0 : ~is_aligned & pointer_set | is_aligned;
-    pointer_latched <= rst ? 1'b0 : pointer_set ? pointer : pointer_latched;
+    pointer_latched <= rst ? {pwidth{1'b0}} : pointer_set ? pointer : pointer_latched;
 end
 
 endmodule
@@ -1801,23 +1795,24 @@ wire                    empty_rd;
 wire                    full_wr;
 wire                    val_wr;
 wire                    val_rd;
+wire                    almost_empty_rd;
 
 always @ (posedge usrclk)
-    wordcounter  <= reset ? 32'h0 : realign & ~(div == 0) ? 31'b1 : wordcounter == (div - 1) ? 32'h0 : wordcounter + 1'b1;
+    wordcounter  <= reset ? 32'h0 : realign & ~(div == 0) ? 32'd1 : wordcounter == (div - 1) ? 32'h0 : wordcounter + 1'b1;
 
 genvar ii;
 generate
 for (ii = 0; ii < div; ii = ii + 1)
 begin: splicing
     always @ (posedge usrclk)
-        inbuffer_data[(ii + 1) * internal_data_width - 1 -: internal_data_width] <= reset ? {interface_data_width{1'b0}} : ((wordcounter == ii) | realign & (0 == ii)) ? indata : inbuffer_data[(ii + 1) * internal_data_width - 1 -: internal_data_width];
+        inbuffer_data[(ii + 1) * internal_data_width - 1 -: internal_data_width] <= reset ? {internal_data_width{1'b0}} : ((wordcounter == ii) | realign & (0 == ii)) ? indata : inbuffer_data[(ii + 1) * internal_data_width - 1 -: internal_data_width];
 end
 endgenerate
 generate
 for (ii = 0; ii < div; ii = ii + 1)
 begin: splicing2
     always @ (posedge usrclk)
-        inbuffer_isk[(ii + 1) * internal_isk_width - 1 -: internal_isk_width] <= reset ? {interface_isk_width{1'b0}} : ((wordcounter == ii) | realign & (0 == ii)) ? inisk : inbuffer_isk[(ii + 1) * internal_isk_width - 1 -: internal_isk_width];
+        inbuffer_isk[(ii + 1) * internal_isk_width - 1 -: internal_isk_width] <= reset ? {internal_isk_width{1'b0}} : ((wordcounter == ii) | realign & (0 == ii)) ? inisk : inbuffer_isk[(ii + 1) * internal_isk_width - 1 -: internal_isk_width];
 end
 endgenerate
 
@@ -2067,10 +2062,10 @@ begin: asdadfdsf
 end
 endgenerate
 assign  RXDATA[63:iface_databus_width]       = {64 - iface_databus_width{1'bx}};
-assign  RXDISPERR[7:interface_isk_width]     = {7 - interface_isk_width{1'bx}};
-assign  RXCHARISK[7:interface_isk_width]     = {7 - interface_isk_width{1'bx}};
-assign  RXCHARISCOMMA[7:interface_isk_width] = {7 - interface_isk_width{1'bx}};
-assign  RXNOTINTABLE[7:interface_isk_width]  = {7 - interface_isk_width{1'bx}};
+assign  RXDISPERR[7:interface_isk_width]     = {8 - interface_isk_width{1'bx}};
+assign  RXCHARISK[7:interface_isk_width]     = {8 - interface_isk_width{1'bx}};
+assign  RXCHARISCOMMA[7:interface_isk_width] = {8 - interface_isk_width{1'bx}};
+assign  RXNOTINTABLE[7:interface_isk_width]  = {8 - interface_isk_width{1'bx}};
 
 gtxe2_chnl_rx_dataiface #(
     .internal_data_width    (internal_data_width + internal_data_extra),
@@ -2210,7 +2205,16 @@ module gtxe2_chnl(
     output  wire            RXOUTCLKPCS,
     output  wire            RXOUTCLK,
     output  wire            RXOUTCLKFABRIC,
-    output  wire            rx_serial_clk
+    output  wire            rx_serial_clk,
+
+// additional ports to pll
+    output              TSTOUT,
+    input   [15:0]      GTRSVD,
+    input   [15:0]      PCSRSVDIN,
+    input   [4:0]       PCSRSVDIN2,
+    input   [4:0]       PMARSVDIN,
+    input   [4:0]       PMARSVDIN2,
+    input   [19:0]      TSTIN
 );
 parameter   [23:0]  CPLL_CFG        = 29'h00BC07DC;
 parameter   integer CPLL_FBDIV      = 4;
@@ -2383,12 +2387,22 @@ clocking(
     .TXOUTCLK           (TXOUTCLK),
     .TXOUTCLKFABRIC     (TXOUTCLKFABRIC),
     .tx_serial_clk      (tx_serial_clk),
+    .tx_piso_clk        (),
 
+    .GTRSVD             (GTRSVD),
+    .PCSRSVDIN          (PCSRSVDIN),
+    .PCSRSVDIN2         (PCSRSVDIN2),
+    .PMARSVDIN          (PMARSVDIN),
+    .PMARSVDIN2         (PMARSVDIN2),
+    .TSTIN              (TSTIN),
+    .TSTOUT             (TSTOUT),
+    
     .RXOUTCLKPMA        (RXOUTCLKPMA),
     .RXOUTCLKPCS        (RXOUTCLKPCS),
     .RXOUTCLK           (RXOUTCLK),
     .RXOUTCLKFABRIC     (RXOUTCLKFABRIC),
-    .rx_serial_clk      (rx_serial_clk)
+    .rx_serial_clk      (rx_serial_clk),
+    .rx_sipo_clk        ()
 );
 
 endmodule
@@ -2415,12 +2429,12 @@ module GTXE2_GPL(
     output              CPLLLOCK,
     output              CPLLREFCLKLOST,
     output              TSTOUT,
-    input               GTRSVD,
-    input               PCSRSVDIN,
-    input               PCSRSVDIN2,
-    input               PMARSVDIN,
-    input               PMARSVDIN2,
-    input               TSTIN,
+    input   [15:0]      GTRSVD,
+    input   [15:0]      PCSRSVDIN,
+    input   [4:0]       PCSRSVDIN2,
+    input   [4:0]       PMARSVDIN,
+    input   [4:0]       PMARSVDIN2,
+    input   [19:0]      TSTIN,
 // Reset Mode ports, ug476 p.62
     input               GTRESETSEL,
     input               RESETOVRD,
@@ -2496,11 +2510,11 @@ module GTXE2_GPL(
     output              TXPHALIGNDONE,
     output              TXPHINITDONE,
     output              TXDLYSRESETDONE,
-    input               TXSYNCMODE,
+/*    input               TXSYNCMODE,
     input               TXSYNCALLIN,
     input               TXSYNCIN,
     output              TXSYNCOUT,
-    output              TXSYNCDONE,
+    output              TXSYNCDONE,*/
 // TX Pattern Generator, ug476 p.147
     input   [2:0]       TXPRBSSEL,
     input               TXPRBSFORCEERR,
@@ -3079,17 +3093,27 @@ channel(
     .CPLLLOCK               (CPLLLOCK),
     .CPLLREFCLKLOST         (CPLLREFCLKLOST),
 
-    .TXOUTCLKPMA            (TXOUTCLKPMA),
+    .GTRSVD                 (GTRSVD),
+    .PCSRSVDIN              (PCSRSVDIN),
+    .PCSRSVDIN2             (PCSRSVDIN2),
+    .PMARSVDIN              (PMARSVDIN),
+    .PMARSVDIN2             (PMARSVDIN2),
+    .TSTIN                  (TSTIN),
+    .TSTOUT                 (TSTOUT),
+    
+    .TXOUTCLKPMA            (),
     .TXOUTCLKPCS            (TXOUTCLKPCS),
     .TXOUTCLK               (TXOUTCLK),
     .TXOUTCLKFABRIC         (TXOUTCLKFABRIC),
     .tx_serial_clk          (),
 
-    .RXOUTCLKPMA            (RXOUTCLKPMA),
+    .RXOUTCLKPMA            (),
     .RXOUTCLKPCS            (RXOUTCLKPCS),
     .RXOUTCLK               (RXOUTCLK),
     .RXOUTCLKFABRIC         (RXOUTCLKFABRIC),
-    .rx_serial_clk          ()
+    .rx_serial_clk          (),
+
+    .RXDLYBYPASS            (RXDLYBYPASS)
 );
 
 

wrapper/gtxe2_channel_wrapper.v

@@ -41,12 +41,12 @@ module gtxe2_channel_wrapper(
     output              CPLLLOCK,
     output              CPLLREFCLKLOST,
     output              TSTOUT,
-    input               GTRSVD,
-    input               PCSRSVDIN,
-    input               PCSRSVDIN2,
-    input               PMARSVDIN,
-    input               PMARSVDIN2,
-    input               TSTIN,
+    input   [15:0]      GTRSVD,
+    input   [15:0]      PCSRSVDIN,
+    input   [4:0]       PCSRSVDIN2,
+    input   [4:0]       PMARSVDIN,
+    input   [4:0]       PMARSVDIN2,
+    input   [19:0]      TSTIN,
 // Reset Mode ports, ug476 p.62
     input               GTRESETSEL,
     input               RESETOVRD,
@@ -122,11 +122,11 @@ module gtxe2_channel_wrapper(
     output              TXPHALIGNDONE,
     output              TXPHINITDONE,
     output              TXDLYSRESETDONE,
-    input               TXSYNCMODE,
+/*    input               TXSYNCMODE,
     input               TXSYNCALLIN,
     input               TXSYNCIN,
     output              TXSYNCOUT,
-    output              TXSYNCDONE,
+    output              TXSYNCDONE,*/
 // TX Pattern Generator, ug476 p.147
     input   [2:0]       TXPRBSSEL,
     input               TXPRBSFORCEERR,
@@ -455,11 +455,6 @@ parameter   ES_QUAL_MASK                 = 80'h0;
 parameter   ES_EYE_SCAN_EN               = 1'b1;
 parameter   ES_ERRDET_EN                 = 1'b0;
 parameter   ES_CONTROL                   = 6'h0;
-parameter   es_control_status            = 4'b000;
-parameter   es_rdata                     = 80'h0;
-parameter   es_sdata                     = 80'h0;
-parameter   es_error_count               = 16'h0;
-parameter   es_sample_count              = 16'h0;
 parameter   RX_DATA_WIDTH                = 20;
 parameter   RX_INT_DATAWIDTH             = 0;
 parameter   ES_PMA_CFG                   = 10'h0;
@@ -915,11 +910,11 @@ gtx_unisims(
     .TXPHALIGNDONE                                              (TXPHALIGNDONE),
     .TXPHINITDONE                                               (TXPHINITDONE),
     .TXDLYSRESETDONE                                            (TXDLYSRESETDONE),
-    .TXSYNCMODE                                                 (TXSYNCMODE),
+/*    .TXSYNCMODE                                                 (TXSYNCMODE),
     .TXSYNCALLIN                                                (TXSYNCALLIN),
     .TXSYNCIN                                                   (TXSYNCIN),
     .TXSYNCOUT                                                  (TXSYNCOUT),
-    .TXSYNCDONE                                                 (TXSYNCDONE),
+    .TXSYNCDONE                                                 (TXSYNCDONE),*/
 // TX Pattern Generator, ug476 p.147
     .TXPRBSSEL                                                  (TXPRBSSEL),
     .TXPRBSFORCEERR                                             (TXPRBSFORCEERR),