auto-logging IRQ on/off in datascope, bitstream v12

ahci/ahci_top.v

@@ -1217,6 +1217,7 @@ wire [9:0] xmit_dbg_01;
                 .d2h_ready       (d2h_ready), // input
                 .debug_link_send_data(debug_link_send_data), // input
                 .debug_link_dmatp  (debug_link_dmatp),        // link received DMATp from device
+                .irq             (irq),           // system IRQ
                 .datascope_clk   (datascope_clk), // output
                 .datascope_waddr (datascope_waddr), // output[9:0] reg 
                 .datascope_we    (datascope_we), // output
@@ -1350,6 +1351,7 @@ module datascope_timing #(
     
     input                     debug_link_send_data, // @posedge mclk (sata_clk, 75MHz)  - last symbol was data output (to count sent out)
     input                     debug_link_dmatp,     // link received DMATp from device
+    input                     irq,                  // system irq
     output                        datascope_clk,
     output reg [ADDRESS_BITS-1:0] datascope_waddr,
     output                        datascope_we,
@@ -1408,6 +1410,10 @@ module datascope_timing #(
     
     reg                       reset_link_count; // data FIS from dma command until
     reg                       was_link_dmatp;   //
+    reg                       irq_r;
+    reg                       irq_was;
+    wire                      we_w = write_punch_time || fis_start || (fis_we ? pre_we_r : (!fis_run && (fis_run_d || fis_run_d2 || fis_run_d3 || fis_run_d4  || fis_run_d5))); // 3 after
+    wire                      we_irq= (irq_was ^ irq_r) && !we_w; // only when not irq  
     
 //    input              debug_link_dmatp,      // link received DMATp from device
     
@@ -1436,11 +1442,11 @@ module datascope_timing #(
         else if (!fis_run_d2 && fis_run_d3)  datascope_di <= {8'h55,   last_dma_cmd};
         else if (!fis_run_d3 && fis_run_d4)  datascope_di <= non_dma_act;
         else if (!fis_run_d4 && fis_run_d5)  datascope_di <= {h2d_nready_cntr[7:0], was_link_dmatp, 1'b0, link_count_latched};
-
+        else if (we_irq)                     datascope_di <= {3'h7,irq_r,cur_time};
         pre_we_r <= pre_we_w || fis_start ;
     
 //        we_r <= write_punch_time || fis_start || (fis_we ? pre_we_r : (!fis_run && fis_run_d));
-        we_r <= write_punch_time || fis_start || (fis_we ? pre_we_r : (!fis_run && (fis_run_d || fis_run_d2 || fis_run_d3 || fis_run_d4  || fis_run_d5))); // 3 after
+        we_r <= we_w || we_irq;
         
         if     (fis_start) fis_left <= FIS_LEN - 1;
         else if (pre_we_w) fis_left <= fis_left - 1;
@@ -1509,6 +1515,11 @@ module datascope_timing #(
         if      (rst)  datascope_waddr <= 0;
         else if (we_r) datascope_waddr <= datascope_waddr + 1;
         
+        irq_r <= irq;
+        
+        if      (rst)    irq_was <=0;
+        else if (we_irq) irq_was <= irq_r;
+        
     end
     
 endmodule

includes/ahci_defaults.vh

@@ -2,6 +2,6 @@
 , .INIT_08 (256'h000000000024000600000000000000000000000080000C000000000080000800)
 , .INIT_09 (256'h000000000000000000000000000000000000000000000000FFFFFFFF00000000)
 , .INIT_0B (256'h0000000000000000000000000000003300000000000000000000000000000000)
-, .INIT_0C (256'h000000000000000000000000000000000000000001010011001000000001FFFE)
+, .INIT_0C (256'h000000000000000000000000000000000000000001010012001000000001FFFE)
 , .INIT_0D (256'h000001000000000000000040000000000001FFFE000000008000000000000000)
 , .INIT_0E (256'h0000000000000000000000000000000000000000000000000000000040000001)

includes/ahci_localparams.vh

@@ -97,7 +97,7 @@
 // RO: HBA Revision ID
     localparam PCI_Header__RID__RID__ADDR = 'h62;
     localparam PCI_Header__RID__RID__MASK = 'hff;
-    localparam PCI_Header__RID__RID__DFLT = 'h11;
+    localparam PCI_Header__RID__RID__DFLT = 'h12;
 // RO: Base Class Code: 1 - Mass Storage Device
     localparam PCI_Header__CC__BCC__ADDR = 'h62;
     localparam PCI_Header__CC__BCC__MASK = 'hff000000;

py393sata/create_ahci_registers.py

@@ -31,7 +31,9 @@ __status__ = "Development"
 """
 **** Modify next value for new file versions, re-run this file  *****
 """
-RID = 0x011  # Revision ID
+# Revision ID
+RID =  0x012  # Revision ID: registering irq on/off in datascope, as if tag = 6/7
+#RID = 0x011  # Revision ID
 VID = 0xfffe # What to use for non-PCI "vendorID"?
 DID = 0x0001
 SSVID = 0xfffe

py393sata/x393sata.py

@@ -1531,7 +1531,7 @@ import x393_mem
 mem = x393_mem.X393Mem(1,0,1)
 sata = x393sata.x393sata()
 hex(mem.read_mem(sata.get_reg_address('PCI_Header__RID')))
-hex([((mem.read_mem(0x80000ffc) >> 10) & 0xffc) + 0x80001000,mem.mem_dump (0x80001000, 0x400,4),sata.reg_status()][0])
+hex([((mem.read_mem(0x80000ffc) >> 10) & 0xffc) + 0x80001000,mem.mem_dump (0x80001000, 0x400,4),sata.reg_status()][0])+" "+hex(mem.read_mem(0x80000ffc))
  
 sata.setup_pio_read_identify_command()
 

tb_ahci_01.sav

 [*]
 [*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
-[*] Sat Dec 10 21:15:47 2016
+[*] Sun Dec 11 04:31:36 2016
 [*]
-[dumpfile] "/home/eyesis/git/elphel393/fpga-elphel/x393_sata/simulation/tb_ahci-20161210125949381.fst"
-[dumpfile_mtime] "Sat Dec 10 20:00:43 2016"
-[dumpfile_size] 13297893
+[dumpfile] "/home/eyesis/git/elphel393/fpga-elphel/x393_sata/simulation/tb_ahci-20161210212639118.fst"
+[dumpfile_mtime] "Sun Dec 11 04:27:34 2016"
+[dumpfile_size] 13299181
 [savefile] "/home/eyesis/git/elphel393/fpga-elphel/x393_sata/tb_ahci_01.sav"
-[timestart] 48410000
+[timestart] 0
 [size] 1814 1171
 [pos] 68 0
-*-21.141130 55007308 32882854 55953880 57700372 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-24.068264 37475728 32882854 55953880 57700372 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] tb_ahci.
 [treeopen] tb_ahci.axi_read_addr.
 [treeopen] tb_ahci.dev.
@@ -41,6 +41,7 @@
 [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.tx.
 [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.
 [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.
+[treeopen] tb_ahci.dut.sata_top.ahci_top_i.
 [treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.
 [treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_rd_fifo_i.
 [treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_rd_fifo_i.ahci_dma_rd_stuff_i.
@@ -3938,9 +3939,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_h2d_i.ren
 -up
 @28
 tb_ahci.dut.sata_top.ahci_sata_layers_i.h2d_ready
-@29
 tb_ahci.dut.sata_top.ahci_sata_layers_i.h2d_valid
-@28
 tb_ahci.dut.sata_top.ahci_sata_layers_i.ll_frame_req
 tb_ahci.dut.sata_top.ahci_sata_layers_i.h2d_fifo_wr
 @200
@@ -5380,6 +5379,17 @@ tb_ahci.dev.linkSendPrim.type[111:0]
 @800200
 -datascope
 @28
+tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.irq
+tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.irq_r
+tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.irq_was
+@29
+tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.we_irq
+@28
+tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.we_r
+@22
+tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.h2d_nready_cntr[7:0]
+@28
+tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.h2d_ready
 tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.was_link_dmatp
 tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.reset_link_count
 tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.debug_link_send_data