MAxi clock now sourcing drp and cplllockdetclk

dma/sata_top.v

@@ -32,6 +32,10 @@
     output  wire    sclk,
     output  wire    sata_rst,
     input   wire    extrst,
+    
+    // reliable clock to source drp and cpll lock det circuits
+    input   wire    reliable_clk,
+
 /*
  * Commands interface
  */
@@ -605,6 +609,8 @@ sata_host sata_host(
     .rst                        (sata_rst),
     // sata clk
     .clk                        (sclk),
+    // reliable clock to source drp and cpll lock det circuits
+    .reliable_clk               (reliable_clk),
 // temporary
     .al_cmd_in                  (cmd_out), // == {cmd_type, cmd_port, cmd_val, cmd_done_bad, cmd_done_good; cmd_busy}
     .al_cmd_val_in              (cmd_val_out),

dma/top.v

@@ -139,8 +139,8 @@ BUFG bufg_axi_aclk0_i  (.O(axi_aclk0),.I(fclk[0]));
 BUFG bufg_axi_rst_i   (.O(axi_rst),.I(axi_rst_pre));
 BUFG bufg_extrst_i    (.O(extrst),.I(axi_rst_pre));
 axi_hp_clk #(
-    .CLKIN_PERIOD(6.666),
-    .CLKFBOUT_MULT_AXIHP(6),
+    .CLKIN_PERIOD(20.000),
+    .CLKFBOUT_MULT_AXIHP(18),
     .CLKFBOUT_DIV_AXIHP(6)
 ) axi_hp_clk_i (
     .rst          (axi_rst), // input
@@ -151,6 +151,8 @@ axi_hp_clk #(
 
 sata_top sata_top(
     .sclk                       (sclk),
+    // reliable clock to source drp and cpll lock det circuits
+    .reliable_clk               (axi_aclk0),
     .sata_rst                   (sata_rst),
     .extrst                     (extrst),
     .ACLK                       (axi_aclk),

host/sata_host.v

@@ -29,6 +29,10 @@ module sata_host(
     output  wire    rst,
     // sata clk
     output  wire    clk,
+
+    // reliable clock to source drp and cpll lock det circuits
+    input   wire    reliable_clk,
+
 // temporary
     input   wire    [31:0]  al_cmd_in, // == {cmd_type, cmd_port, cmd_val, cmd_done_bad, cmd_done_good; cmd_busy}
     input   wire            al_cmd_val_in,
@@ -657,6 +661,9 @@ sata_phy phy(
     // sata clk, generated in pll as usrclk2
     .clk                (clk),
 
+    // stable clock to source drp and cpll lock det circuits
+    .reliable_clk       (reliable_clk),
+
     // state
     .phy_ready          (phy_ready),
 

host/sata_phy.v

@@ -30,6 +30,9 @@ module sata_phy #(
     output  wire        clk,
     output  wire        rst,
 
+    // reliable clock to source drp and cpll lock det circuits
+    input   wire        reliable_clk,
+
     // state
     output  wire        phy_ready,
 
@@ -370,8 +373,8 @@ gtx_wrap
 /*
  * Interfaces
  */
-assign  cplllockdetclk  = gtrefclk; //TODO
-assign  drpclk          = gtrefclk;
+assign  cplllockdetclk  = reliable_clk; //gtrefclk;
+assign  drpclk          = reliable_clk; //gtrefclk;
 
 //assign  clk             = usrclk2;
 BUFG bufg_sclk   (.O(clk),.I(usrclk2));

tb/tb_top.v

@@ -74,8 +74,8 @@ reg         SIMUL_AXI_FULL; // some data available
 wire        SIMUL_AXI_EMPTY;
 reg  [31:0] registered_rdata; // here read data from task
 
-//reg        CLK;
-wire    CLK;
+reg        CLK;
+//wire    CLK;
 reg        RST;
 reg        AR_SET_CMD_r;
 wire       AR_READY;
@@ -162,12 +162,12 @@ wire         #(AXI_TASK_HOLD) AW_SET_CMD = AW_SET_CMD_r;
 wire         #(AXI_TASK_HOLD) W_SET_CMD =  W_SET_CMD_r;
 
 //always #(CLKIN_PERIOD/2) CLK = ~CLK;
-assign CLK = dut.axi_aclk;
+//assign CLK = dut.axi_aclk0;
 
 /*
  * connect axi ports to the dut
  */
-assign dut.ps7_i.FCLKCLK=        {4{EXTCLK_P}};
+assign dut.ps7_i.FCLKCLK=        {4{CLK}};
 assign dut.ps7_i.FCLKRESETN=     {RST,~RST,RST,~RST};
 // Read address
 assign dut.ps7_i.MAXIGP1ARADDR=  araddr;

tb/test_top.v

@@ -30,6 +30,12 @@ begin
     EXTCLK_N = ~EXTCLK_N;
 end
 
+// MAXI clock
+always #10
+begin
+    CLK = ~CLK;
+end
+
 integer i;
 integer status;
 integer id;
@@ -37,7 +43,7 @@ reg [31:0] data;
 // write registers
 initial
 begin
-//    CLK =1'b0;
+    CLK =1'b0;
     RST = 1'bx;
     AR_SET_CMD_r = 1'b0;
     AW_SET_CMD_r = 1'b0;