Major update

Board: Zynq 7z30

Board: Zynq 7z30

FPGA: Kintex-7

FPGA: Kintex-7

# Current step:

# Current step:

Connecting Ashwin's core (slow interface to the system is almost done, have to completely rewrite phy-level). Feels like making the phy works is going to require a lot of effort

Testing basic functionallity of a host.  

Trying out pio access.  

Fullfilling device-side drivers and monitors via tasks.  

Tests are mostly manual, relied on a common sense and waveforms instpection. Still, complatible both with gtx-gpl and unisims/gtx

# Going to do afterwards:

# Going to do afterwards:

Complete and test the 'current step'. Write host controller with ~same functionallity, check if it works with previously verified higher-level code.

Test dma functionallity of the host.  

And then to spin out the full-compatible functionallity (ideally somewhere to the level of ahci)

Make cocotb testbench - gtx-gpl only - random payload high-level verification testing purposes.  

Create a base of regression tests, containing lower-level tests - both gtx-gpl and unisims/gtx.  

Improve an implementation of DMA control module.  

Finally decide what to do with a driver and modify application level (actally, write it from scrap) correspodning to driver's interfaces.  

wire    [31:0]  phy2dev_data;

wire    [3:0]   phy2dev_charisk;

wire    [3:0]   phy2dev_err;

wire            dev_clk;

wire            dev_rst;

reg     [31:0]  dev2phy_data;

reg     [3:0]   dev2phy_charisk;

force   dev.dev2phy_data    = 

force   dev.dev2phy_charisk =

task 

/*******************************************************************************

 * Module: oob_ctrl

 * Date: 2015-07-11  

 * Author: Alexey     

 * Description: module to start oob sequences and to handle errors

 *

 * Copyright (c) 2015 Elphel, Inc.

 * oob_ctrl.v is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation, either version 3 of the License, or

 * (at your option) any later version.

 *

 * oob_ctrl.v file is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/> .

 *******************************************************************************/

`include "oob.v"

module oob_ctrl_dev #(

    parameter DATA_BYTE_WIDTH = 4,

    parameter CLK_SPEED_GRADE = 2 // 1 - 75 Mhz, 2 - 150Mhz, 4 - 300Mhz

)

(

    // sata clk = usrclk2

    input   wire    clk,

    // reset oob

    input   wire    rst,

    // gtx is ready = all resets are done

    input   wire    gtx_ready,

    // oob responces

    input   wire    rxcominitdet_in,

    input   wire    rxcomwakedet_in,

    input   wire    rxelecidle_in,

    // oob issues

    output  wire    txcominit,

    output  wire    txcomwake,

    output  wire    txelecidle,

    // input data stream (if any data during OOB setting => ignored)

    input   wire    [DATA_BYTE_WIDTH*8 - 1:0] txdata_in,

    input   wire    [DATA_BYTE_WIDTH - 1:0]   txcharisk_in,

    // output data stream to gtx

    output  wire    [DATA_BYTE_WIDTH*8 - 1:0] txdata_out,

    output  wire    [DATA_BYTE_WIDTH - 1:0]   txcharisk_out,

    // input data from gtx

    input   wire    [DATA_BYTE_WIDTH*8 - 1:0] rxdata_in,

    input   wire    [DATA_BYTE_WIDTH - 1:0]   rxcharisk_in,

    // bypassed data from gtx

    output  wire    [DATA_BYTE_WIDTH*8 - 1:0] rxdata_out,

    output  wire    [DATA_BYTE_WIDTH - 1:0]   rxcharisk_out,

    // obvious

    input   wire    rxbyteisaligned,

    // shows if channel is ready

    output  wire    phy_ready

);

// oob sequence needs to be issued

wire    oob_start;

// connection established, all further data is valid

wire    oob_done;

// doc p265, link is established after 3back-to-back non-ALIGNp

wire    link_up;

wire    link_down;

// the device itself sends cominit

wire    cominit_req;

// allow to respond to cominit

wire    cominit_allow;

// status information to handle by a control block if any exists

// incompatible host-device speed grades (host cannot lock to alignp)

wire    oob_incompatible; // TODO

// timeout in an unexpected place

wire    oob_error;

// noone responds to our cominits

wire    oob_silence;

// obvious

wire    oob_busy;

// for the resync sake

reg rxbyteisaligned_r;

reg rxbyteisaligned_rr;

always @ (posedge clk)

begin

    rxbyteisaligned_rr  <= rxbyteisaligned_r;

    rxbyteisaligned_r   <= rxbyteisaligned;

end

// 1 - link is up and running, 0 - probably not

reg     link_state;

// 1 - connection is being established OR already established, 0 - is not

reg     oob_state;

assign  phy_ready = link_state & gtx_ready & rxbyteisaligned_rr;

always @ (posedge clk)

    link_state  <= (link_state | link_up) & ~link_down & ~rst; 

always @ (posedge clk)

    oob_state   <= (oob_state | oob_start | cominit_req & cominit_allow) & ~oob_error & ~oob_silence & link_down & ~rst;

// decide when to issue oob: always when gtx is ready

assign  oob_start = gtx_ready & ~oob_state & ~oob_busy;

// set line to idle state before if we're waiting for a device to answer AND while oob sequence

wire    txelecidle_inner;

assign  txelecidle = ~oob_state | txelecidle_inner;

// let devices always begin oob sequence, if only it's not a glitch

assign  cominit_allow = cominit_req & link_state;

oob_dev #(

    .DATA_BYTE_WIDTH    (DATA_BYTE_WIDTH),

    .CLK_SPEED_GRADE    (CLK_SPEED_GRADE)

)

oob_dev

(

// sata clk = usrclk2

    .clk                            (clk),

// reset oob

    .rst                            (rst),

// oob responces

    .rxcominitdet_in                (rxcominitdet_in),

    .rxcomwakedet_in                (rxcomwakedet_in),

    .rxelecidle_in                  (rxelecidle_in),

// oob issues

    .txcominit                      (txcominit),

    .txcomwake                      (txcomwake),

    .txelecidle                     (txelecidle_inner),

// input data stream (if any data during OOB setting => ignored)

    .txdata_in                      (txdata_in),

    .txcharisk_in                   (txcharisk_in),

// output data stream to gtx

    .txdata_out                     (txdata_out),

    .txcharisk_out                  (txcharisk_out),

// input data from gtx

    .rxdata_in                      (rxdata_in),

    .rxcharisk_in                   (rxcharisk_in),

// bypassed data from gtx

    .rxdata_out                     (rxdata_out),

    .rxcharisk_out                  (rxcharisk_out),

// oob sequence needs to be issued

    .oob_start                      (oob_start),

// connection established, all further data is valid

    .oob_done                       (oob_done),

// doc p265, link is established after 3back-to-back non-ALIGNp

    .link_up                        (link_up),

    .link_down                      (link_down),

// the device itself sends cominit

    .cominit_req                    (cominit_req),

// allow to respond to cominit

    .cominit_allow                  (cominit_allow),

// status information to handle by a control block if any exists

// incompatible host-device speed grades (host cannot lock to alignp)

    .oob_incompatible               (oob_incompatible),

// timeout in an unexpected place

    .oob_error                      (oob_error),

// noone responds to our cominits

    .oob_silence                    (oob_silence),

// oob can't handle new start request

    .oob_busy                       (oob_busy)

);

endmodule

/*******************************************************************************

 * Module: oob

 * Date: 2015-07-11  

 * Author: Alexey     

 * Description: sata oob unit implementation

 *

 * Copyright (c) 2015 Elphel, Inc.

 * oob.v is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation, either version 3 of the License, or

 * (at your option) any later version.

 *

 * oob.v file is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/> .

 *******************************************************************************/

/*

 * For now both device and host shall be set up to SATA2 speeds.

 * Need to think how to change speed grades on fly (either to broaden 

 * data iface width or to change RXRATE/TXRATE)

 */

// All references to doc = to SerialATA_Revision_2_6_Gold.pdf

module oob_dev #(

    parameter DATA_BYTE_WIDTH = 4,

    parameter CLK_SPEED_GRADE = 2 // 1 - 75 Mhz, 2 - 150Mhz, 4 - 300Mhz

)

(

    // sata clk = usrclk2

    input   wire    clk,

    // reset oob

    input   wire    rst,

    input   wire    gtx_ready,

    // oob responces

    input   wire    rxcominitdet_in,

    input   wire    rxcomwakedet_in,

    input   wire    rxelecidle_in,

    // oob issues

    output  reg     txcominit,

    output  reg     txcomwake,

    output  reg     txelecidle,

    // output data stream to gtx

    output  wire    [DATA_BYTE_WIDTH*8 - 1:0] txdata_out,

    output  wire    [DATA_BYTE_WIDTH - 1:0]   txcharisk_out,

    // input data from gtx

    input   wire    [DATA_BYTE_WIDTH*8 - 1:0] rxdata_in,

    input   wire    [DATA_BYTE_WIDTH - 1:0]   rxcharisk_in,

    output  wire    link_up

);

localparam  STATE_RESET             = 0;

localparam  STATE_COMINIT           = 1;

localparam  STATE_AWAITCOMWAKE      = 2;

localparam  STATE_AWAITNOCOMWAKE    = 3;

localparam  STATE_CALIBRATE         = 4;

localparam  STATE_COMWAKE           = 5;

localparam  STATE_SENDALIGN         = 6;

localparam  STATE_READY             = 7;

localparam  STATE_PARTIAL           = 8;

localparam  STATE_SLUMBER           = 9;

localparam  STATE_REDUCESPEED       = 10;

localparam  STATE_ERROR             = 11;

reg     [9:0]   state;

wire    retry_interval_elapsed;

wire    wait_interval_elapsed;

wire    nocomwake;

wire    [31:0]  align;

wire    [31:0]  sync;

assign  align = {8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100}; // {D27.3, D10.2, D10.2, K28.5}

assign  sync  = {8'b10110101, 8'b10110101, 8'b10010101, 8'b01111100}; // {D21.5, D21.5, D21.4, K28.3}

reg [31:0]  nocomwake_timer;

assign  nocomwake = nocomwake_timer == 32'd38;

always @ (posedge clk)

    nocomwake_timer <= rst | rxcomwakedet_in ? 32'h0 : nocomwake ? nocomwake_timer : nocomwake_timer + 1'b1;

reg [31:0]  retry_timer;

assign  retry_interval_elapsed = retry_timer == 32'd1000;

always @ (posedge clk)

    retry_timer <= rst | ~(state == STATE_AWAITCOMWAKE) ? 32'h0 : retry_timer + 1'b1;

reg [31:0]  wait_timer;

assign  wait_interval_elapsed = wait_timer == 32'd1000;

always @ (posedge clk)

    wait_timer <= rst | ~(state == STATE_SENDALIGN) ? 32'h0 : wait_timer + 1'b1;

reg [31:0]  data;

reg [3:0]   isk;

assign  link_up = state == STATE_READY;

assign  txdata_out      = data;

assign  txcharisk_out   = isk;

// buf inputs from gtx

reg rxcominitdet;

reg rxcomwakedet;

reg rxelecidle;

reg [31:0]  rxdata; 

reg [3:0]   rxcharisk;

always @ (posedge clk)

begin

    rxcominitdet <= rxcominitdet_in;

    rxcomwakedet <= rxcomwakedet_in;

    rxelecidle   <= rxelecidle_in;

    rxdata       <= rxdata_in;

    rxcharisk    <= rxcharisk_in;

end

assign  aligndet = ~|(rxdata ^ {8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100}) & ~|(rxcharisk ^ 4'h1); // {D27.3, D10.2, D10.2, K28.5}

assign  syncdet  = ~|(rxdata ^ {8'b10110101, 8'b10110101, 8'b10010101, 8'b01111100}) & ~|(rxcharisk ^ 4'h1); // {D21.5, D21.5, D21.4, K28.3}

always @ (posedge clk)

    if (rst | ~gtx_ready)

    begin

        state       <= STATE_RESET;

        txelecidle  <= 1'b1;

        txcominit   <= 1'b0;

        txcomwake   <= 1'b0;

    end

    else

        case (state)

        STATE_RESET:

        begin

            if (rxcominitdet_in)

                state       <= STATE_COMINIT;

                txelecidle  <= 1'b1;

                txcominit   <= 1'b0;

                txcomwake   <= 1'b0;

        end

        STATE_COMINIT:

        begin

            state       <= STATE_AWAITCOMWAKE;

            txcominit   <= 1'b1;

        end

        STATE_AWAITCOMWAKE:

        begin

            txcominit   <= 1'b0;

            if (rxcomwakedet_in)

                state   <= STATE_AWAITNOCOMWAKE;

            else 

            if (retry_interval_elapsed)

                state   <= STATE_RESET;

            else

                state   <= STATE_AWAITCOMWAKE;

        end

        STATE_AWAITNOCOMWAKE:

        begin

            if (nocomwake)

            begin

                state   <= STATE_CALIBRATE;

            end

        end

        STATE_CALIBRATE:

        begin

            state   <= STATE_COMWAKE;

        end

        STATE_COMWAKE:

        begin

            txcomwake   <= 1'b1;

            state       <= STATE_SENDALIGN;

        end

        STATE_SENDALIGN:

        begin

            txcomwake   <= 1'b0;

            txelecidle  <= 1'b0;

            data    <= align;

            isk     <= 4'h1;

            if (aligndet)

                state   <= STATE_READY;

            else 

            if (wait_interval_elapsed)

                state   <= STATE_ERROR;

            else

                state   <= STATE_SENDALIGN;

        end

        STATE_READY:

        begin

            data    <= sync;

            isk     <= 4'h1;

            if (rxelecidle_in)

                state   <= STATE_ERROR;

        end

        STATE_ERROR:

        begin

            state   <= STATE_RESET;

        end

        endcase

/*

// 873.8 us error timer

// = 2621400 SATA2 serial ticks (period = 0.000333 us)

// = 131070 ticks @ 150Mhz

// = 65535  ticks @ 75Mhz 

localparam  [19:0]  CLK_TO_TIMER_CONTRIB = CLK_SPEED_GRADE == 1 ? 20'h4 :

                                           CLK_SPEED_GRADE == 2 ? 20'h2 :

                                           CLK_SPEED_GRADE == 4 ? 20'h1 : 20'h1;

`ifdef SIMULATION                                           

localparam  [19:0]  TIMER_LIMIT = 19'd200;

`else

localparam  [19:0]  TIMER_LIMIT = 19'd262140;

`endif

reg     [19:0]  timer;

wire            timer_clr;

wire            timer_fin;

// latching inputs from gtx

reg     rxcominitdet;

reg     rxcomwakedet;

reg     rxelecidle;

reg     [DATA_BYTE_WIDTH*8 - 1:0] rxdata;

reg     [DATA_BYTE_WIDTH - 1:0]   rxcharisk;

// primitives detection

wire    detected_alignp;

wire    detected_syncp;

// fsm, doc p265,266

wire    state_idle;

reg     state_wait_cominit;

reg     state_wait_comwake;

reg     state_wait_align;

reg     state_wait_synp;

reg     state_wait_linkup;

reg     state_error;

wire    set_wait_cominit;

wire    set_wait_comwake;

wire    set_wait_align;

wire    set_wait_synp;

wire    set_wait_linkup;

wire    set_error;

wire    clr_wait_cominit;

wire    clr_wait_comwake;

wire    clr_wait_align;

wire    clr_wait_synp;

wire    clr_wait_linkup;

wire    clr_error;

assign  state_idle = ~state_wait_cominit & ~state_wait_comwake & ~state_wait_align & ~state_wait_synp & ~state_wait_linkup & ~state_error;

always @ (posedge clk)

begin

    state_wait_cominit  <= (state_wait_cominit | set_wait_cominit) & ~clr_wait_cominit & ~rst;

    state_wait_comwake  <= (state_wait_comwake | set_wait_comwake) & ~clr_wait_comwake & ~rst;

    state_wait_align    <= (state_wait_align   | set_wait_align  ) & ~clr_wait_align   & ~rst;

    state_wait_synp     <= (state_wait_synp    | set_wait_synp   ) & ~clr_wait_synp    & ~rst;

    state_wait_linkup   <= (state_wait_linkup  | set_wait_linkup ) & ~clr_wait_linkup  & ~rst;

    state_error         <= (state_error        | set_error       ) & ~clr_error        & ~rst;

end

assign  set_wait_cominit = state_idle & oob_start & ~cominit_req;

assign  set_wait_comwake = state_idle & cominit_req & cominit_allow | state_wait_cominit & rxcominitdet;

assign  set_wait_align   = state_wait_comwake & rxcomwakedet;

assign  set_wait_synp    = state_wait_align & detected_alignp;

assign  set_wait_linkup  = state_wait_synp & detected_syncp;

assign  set_error        = timer_fin & (state_wait_cominit | state_wait_comwake | state_wait_align | state_wait_synp);

assign  clr_wait_cominit = set_wait_comwake | set_error;

assign  clr_wait_comwake = set_wait_align | set_error;

assign  clr_wait_align   = set_wait_synp | set_error;

assign  clr_wait_synp    = set_wait_linkup | set_error;

assign  clr_wait_linkup  = state_wait_linkup; //TODO not so important, but still have to trace 3 back-to-back non alignp primitives

assign  clr_error        = state_error;

// waiting timeout timer

assign  timer_fin = timer == TIMER_LIMIT;

assign  timer_clr = set_error | state_error | state_idle;

always @ (posedge clk)

    timer <= rst | timer_clr ? 20'h0 : timer + CLK_TO_TIMER_CONTRIB;

// something is wrong with speed grades if the host cannot lock to device's alignp stream

assign  oob_incompatible = state_wait_align & set_error;

// oob sequence is done, everything is okay

assign  oob_done = set_wait_linkup;

// noone responds to cominits

assign  oob_silence = set_error & state_wait_cominit;

// other timeouts

assign  oob_error = set_error & ~oob_silence & ~oob_incompatible;

// obvioud

assign  oob_busy = ~state_idle;

// set gtx controls

reg     txelecidle_r;

always @ (posedge clk)

    txelecidle_r <= rst ? 1'b1 : clr_wait_cominit ? 1'b0 : set_wait_cominit ? 1'b1 : txelecidle_r;

assign  txcominit  = set_wait_cominit;

assign  txcomwake  = set_wait_comwake;

assign  txelecidle = set_wait_cominit | txelecidle_r;

// indicate if link up condition was made

assign  link_up = clr_wait_linkup;

// link goes down when line is idle

reg     rxelecidle_r;

reg     rxelecidle_rr;

always @ (posedge clk)

begin

    rxelecidle_rr   <= rxelecidle_r;

    rxelecidle_r    <= rxelecidle;

end

assign  link_down = rxelecidle_rr;

// indicate that device is requesting for oob

reg     cominit_req_r;

wire    cominit_req_set;

assign  cominit_req_set = state_idle & rxcominitdet;

always @ (posedge clk)

    cominit_req_r <= (cominit_req_r | cominit_req_set) & ~(cominit_allow & cominit_req) & ~rst;

assign  cominit_req = cominit_req_set | cominit_req_r;

// detect which primitives sends the device after comwake was done

generate 

    if (DATA_BYTE_WIDTH == 2)