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Commit e06e9e1a authored by Andrey Filippov's avatar Andrey Filippov
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Fixed more bugs in link layer

parent fb82aa54
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Showing with 661 additions and 194 deletions
.project
View file @ e06e9e1a
...@@ -52,87 +52,87 @@ ...@@ -52,87 +52,87 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160214170313831.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160216194006906.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160214170313831.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160216194006906.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160214170313831.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160216194006906.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160214170313831.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160216194006906.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160214170313831.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160216194006906.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160214170313831.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160216194006906.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160214170151284.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160216193813011.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160214170313831.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160216194006906.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160214170151284.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160216193813011.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name> <name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160214170313831.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160216194006906.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name> <name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160214170151284.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160216193813011.log</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt-phys.dcp</name> <name>vivado_state/x393_sata-opt-phys.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160214170313831.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160216194006906.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt-power.dcp</name> <name>vivado_state/x393_sata-opt-power.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160214170313831.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160216194006906.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt.dcp</name> <name>vivado_state/x393_sata-opt.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160214170313831.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160216194006906.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-place.dcp</name> <name>vivado_state/x393_sata-place.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160214170313831.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160216194006906.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-route.dcp</name> <name>vivado_state/x393_sata-route.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160214170313831.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160216194006906.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-synth.dcp</name> <name>vivado_state/x393_sata-synth.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160214170151284.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160216193813011.dcp</location>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>
ahci/ahci_fis_receive.v
View file @ e06e9e1a
...@@ -112,6 +112,11 @@ module ahci_fis_receive#( ...@@ -112,6 +112,11 @@ module ahci_fis_receive#(
input dma_in_ready, // DMA engine ready to accept data input dma_in_ready, // DMA engine ready to accept data
output dma_in_valid // Write data to DMA dev->memory channel output dma_in_valid // Write data to DMA dev->memory channel
,output debug_data_in_ready,
output debug_fis_end_w,
output [1:0] debug_fis_end_r,
output [1:0] debug_get_fis_busy_r
); );
//localparam FA_BITS = 6; // number of bits in received FIS address //localparam FA_BITS = 6; // number of bits in received FIS address
//localparam CLB_OFFS32 = 'h200; // # In the second half of the register space (0x800..0xbff - 1KB) //localparam CLB_OFFS32 = 'h200; // # In the second half of the register space (0x800..0xbff - 1KB)
...@@ -241,6 +246,14 @@ localparam DATA_TYPE_ERR = 3; ...@@ -241,6 +246,14 @@ localparam DATA_TYPE_ERR = 3;
assign fis_first_invalid = fis_first_invalid_r; assign fis_first_invalid = fis_first_invalid_r;
//debug:
assign debug_data_in_ready = data_in_ready;
assign debug_fis_end_w = fis_end_w;
assign debug_fis_end_r = fis_end_r;
assign debug_get_fis_busy_r = get_fis_busy_r;
always @ (posedge mclk) begin always @ (posedge mclk) begin
if (hba_rst || dma_in_stop || pcmd_st_cleared) dma_in <= 0; if (hba_rst || dma_in_stop || pcmd_st_cleared) dma_in <= 0;
else if (dma_in_start) dma_in <= 1; else if (dma_in_start) dma_in <= 1;
......
ahci/ahci_sata_layers.v
View file @ e06e9e1a
...@@ -254,13 +254,25 @@ module ahci_sata_layers #( ...@@ -254,13 +254,25 @@ module ahci_sata_layers #(
assign serr_EI = phy_ready && (0); // RWC: Recovered Data integrity Error assign serr_EI = phy_ready && (0); // RWC: Recovered Data integrity Error
reg [1:0] debug_last_d2h_type_in; reg [1:0] debug_last_d2h_type_in;
reg [1:0] debug_last_d2h_type;
always @ (posedge clk) begin always @ (posedge clk) begin
if (d2h_fifo_wr) debug_last_d2h_type_in<= d2h_type_in; if (d2h_fifo_wr) debug_last_d2h_type_in<= d2h_type_in;
if (d2h_fifo_rd) debug_last_d2h_type<= d2h_type;
end end
assign debug_phy = {h2d_type_out[1:0],h2d_type[1:0], assign debug_phy = {h2d_type_out[1:0],h2d_type[1:0],
ll_h2d_last,d2h_valid, d2h_type[1:0], ll_h2d_last,d2h_valid, d2h_type[1:0],
debug_last_d2h_type_in, d2h_type_in[1:0], debug_last_d2h_type_in, d2h_type_in[1:0],
debug_phy0[19:0]}; debug_last_d2h_type[1:0],
d2h_fill[1:0],
1'b0,
d2h_fifo_wr,
d2h_fifo_re_regen[1:0],
d2h_waddr[1:0],
d2h_raddr[1:0],
debug_phy0[ 7:0]};
// debug_phy0[15:0]};
// debug_phy0[19:0]};
/* /*
// Data/type FIFO, device -> host // Data/type FIFO, device -> host
...@@ -341,7 +353,7 @@ module ahci_sata_layers #( ...@@ -341,7 +353,7 @@ module ahci_sata_layers #(
// FIS transmit H2D // FIS transmit H2D
// Start if all FIS is in FIFO (last word received) or at least that many is in FIFO // Start if all FIS is in FIFO (last word received) or at least that many is in FIFO
if (rst || ll_frame_req) h2d_pending <= 0; if (rst || ll_frame_req) h2d_pending <= 0; // ?
else if ((h2d_type == H2D_TYPE_FIS_HEAD) && h2d_fifo_wr) h2d_pending <= 1; else if ((h2d_type == H2D_TYPE_FIS_HEAD) && h2d_fifo_wr) h2d_pending <= 1;
if (rst) ll_frame_req <= 0; if (rst) ll_frame_req <= 0;
...@@ -400,7 +412,10 @@ module ahci_sata_layers #( ...@@ -400,7 +412,10 @@ module ahci_sata_layers #(
.datascope_waddr (datascope_waddr), // output[9:0] .datascope_waddr (datascope_waddr), // output[9:0]
.datascope_we (datascope_we), // output .datascope_we (datascope_we), // output
.datascope_di (datascope_di), // output[31:0] .datascope_di (datascope_di), // output[31:0]
.datascope_trig (ll_incom_invalidate), // ll_frame_ackn), // input datascope external trigger // .datascope_trig (ll_incom_invalidate ), // ll_frame_ackn), // input datascope external trigger
// .datascope_trig (debug_link[4:0] == 'h0a), // state_send_eof // input datascope external trigger
.datascope_trig (debug_link[4:0] == 'h02), // state_rcvr_goodcrc // input datascope external trigger
//debug_link
`endif `endif
`ifdef USE_DRP `ifdef USE_DRP
......
ahci/ahci_top.v
View file @ e06e9e1a
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generated/action_decoder.v
View file @ e06e9e1a
/******************************************************************************* /*******************************************************************************
* Module: action_decoder * Module: action_decoder
* Date:2016-02-13 * Date:2016-02-16
* Author: auto-generated file, see ahci_fsm_sequence.py * Author: auto-generated file, see ahci_fsm_sequence.py
* Description: Decode sequencer code to 1-hot actions * Description: Decode sequencer code to 1-hot actions
*******************************************************************************/ *******************************************************************************/
......
generated/condition_mux.v
View file @ e06e9e1a
/******************************************************************************* /*******************************************************************************
* Module: condition_mux * Module: condition_mux
* Date:2016-02-13 * Date:2016-02-16
* Author: auto-generated file, see ahci_fsm_sequence.py * Author: auto-generated file, see ahci_fsm_sequence.py
* Description: Select condition * Description: Select condition
*******************************************************************************/ *******************************************************************************/
......
helpers/ahci_fsm_sequence.py
View file @ e06e9e1a
This diff is collapsed.
host/link.v
View file @ e06e9e1a
This diff is collapsed.
includes/ahxi_fsm_code.vh
View file @ e06e9e1a
, .INIT_00 (256'h00100000000E0000000C00000033000000200000000A0000000A0000000A0000) , .INIT_00 (256'h00100000000E0000000C00000033000000200000000A0000000A0000000A0000)
, .INIT_01 (256'h001944521C399446543044170000001900880019003002020204008400220006) , .INIT_01 (256'h001944521C399446543044170000001900880019003002020204008400220006)
, .INIT_02 (256'h001900050019C82E000C04020110002924FB2502024000190003004204040000) , .INIT_02 (256'h001900050019C82E000C04020110002924FB2503024000190003004204040000)
, .INIT_03 (256'h845284BE44374C682C4214190012003900880018000A02080022001901020090) , .INIT_03 (256'h845284BE44374C682C4214190012003900880018000A02080022001901020090)
, .INIT_04 (256'h00190110003901100019144601020030020202040039B07D707A041000398C6B) , .INIT_04 (256'h00190110003901100019144601020030020202040039B07D707A041000398C6B)
, .INIT_05 (256'h64540C2504580000004E24FB250200C0004C24FB250200C0005C000000390000) , .INIT_05 (256'h64540C2504580000004E24FB250300C0004C24FB250300C0005C000000390000)
, .INIT_06 (256'hD10250F8903900A00104006B0202005000E2A89368F018E918CB98A758D73882) , .INIT_06 (256'hD10550F8903900A00104006B0202005000E2A89368F018E918CB98A758D73882)
, .INIT_07 (256'h0060003900000039B07D00000050004400220039B07D707A307730F001080071) , .INIT_07 (256'h0060003900000039B07D00000050004400220039B07D707A307730F001080071)
, .INIT_08 (256'h00050091C88F002200240091288B28FE000C0110008624FB25020240009CD0FB) , .INIT_08 (256'h00050091C88F002200240091288B28FF000C0110008624FB25030240009CD0FD)
, .INIT_09 (256'h48A528A128FE00140039487F0CAD28FE0110009724FB25020140005004020091) , .INIT_09 (256'h48A528A128FF00140039487F0CAD28FF0110009724FB25030140005004020091)
, .INIT_0A (256'h8839089C040800AD011000AB24FB250200C000500081005048A5002200240039) , .INIT_0A (256'h8839089C040800AD011000AB24FB250300C000500081005048A5002200240039)
, .INIT_0B (256'h00C004080039889C040800090039889C50BA0024004800B5D0FB50F8012000B1) , .INIT_0B (256'h00C004080039889C040800090039889C50BA0024004800B5D0FD50F8012000B1)
, .INIT_0C (256'h011000CF24FB250204200039889C50BA00240028011000C5C50224FB24FB0220) , .INIT_0C (256'h011000CF24FB250304200039889C50BA00240028011000C5C50324FB24FB0220)
, .INIT_0D (256'h0050C8E028FE000C011000DB24FB25020440003934D2000000D4001100D4C8D2) , .INIT_0D (256'h0050C8E028FF000C011000DB24FB25030440003934D2000000D4001100D4C8D2)
, .INIT_0E (256'h00F60082011000ED24FB250200C000390401011000E624FB2502018000500101) , .INIT_0E (256'h00F60082011000ED24FB250300C000390401011000E624FB2503018000500101)
, .INIT_0F (256'h0100020101000021021001000021004400F6000000F6011000F424FB250200C0) , .INIT_0F (256'h02010101002100FD021001010021004400F6000000F6011000F424FB250300C0)
, .INIT_10 (256'h0000000000000000000000000000000000000000000000390041000001000000) , .INIT_10 (256'h0000000000000000000000000000000000000039004101050210010100000101)
, .INITP_00 (256'hC8220098170902401E272722222800309418810820809C802018880022222222) , .INITP_00 (256'hC8220098170902401E272722222800309418810820809C802018880022222222)
, .INITP_01 (256'h22082227209C82720A09C22089C680272181A01CB889C8605A2A89C882068270) , .INITP_01 (256'h88882227209C82720A09C22089C680272181A01CB889C8605A2A89C882068270)
, .INITP_02 (256'h0000000000000000000000000000000000000000000000000000000000000082) , .INITP_02 (256'h0000000000000000000000000000000000000000000000000000000000000888)
py393sata/x393sata.py
View file @ e06e9e1a
...@@ -628,6 +628,12 @@ class x393sata(object): ...@@ -628,6 +628,12 @@ class x393sata(object):
print("Datascope (debug) data:") print("Datascope (debug) data:")
print("_=mem.mem_dump (0x%x, 0x20,4)"%(DATASCOPE_ADDR)) print("_=mem.mem_dump (0x%x, 0x20,4)"%(DATASCOPE_ADDR))
self.x393_mem.mem_dump (DATASCOPE_ADDR, 0xa0,4) self.x393_mem.mem_dump (DATASCOPE_ADDR, 0xa0,4)
dd =0
for a in range(0x80001000,0x80001014,4):
dd |= self.x393_mem.read_mem(a)
if dd == 0:
print ("*** Probably got cache/write buffer problem, continuing ***")
break
raise Exception("Failed to get interrupt") raise Exception("Failed to get interrupt")
break break
...@@ -638,13 +644,13 @@ class x393sata(object): ...@@ -638,13 +644,13 @@ class x393sata(object):
print("_=mem.mem_dump (0x%x, 0x4,4)"%(MAXI1_ADDR + DBG_OFFS)) print("_=mem.mem_dump (0x%x, 0x4,4)"%(MAXI1_ADDR + DBG_OFFS))
self.x393_mem.mem_dump (MAXI1_ADDR + DBG_OFFS, 0x4,4) self.x393_mem.mem_dump (MAXI1_ADDR + DBG_OFFS, 0x4,4)
print("Datascope (debug) data:") print("Datascope (debug) data:")
print("_=mem.mem_dump (0x%x, 0x20,4)"%(DATASCOPE_ADDR)) print("_=mem.mem_dump (0x%x, 0x100,4)"%(DATASCOPE_ADDR))
self.x393_mem.mem_dump (DATASCOPE_ADDR, 0xa0,4) self.x393_mem.mem_dump (DATASCOPE_ADDR, 0x200,4)
raise Exception("Failed to get interrupt") raise Exception("Failed to get interrupt")
print("Datascope (debug) data:") print("Datascope (debug) data:")
print("_=mem.mem_dump (0x%x, 0x20,4)"%(DATASCOPE_ADDR)) print("_=mem.mem_dump (0x%x, 0x200,4)"%(DATASCOPE_ADDR))
self.x393_mem.mem_dump (DATASCOPE_ADDR, 0xa0,4) self.x393_mem.mem_dump (DATASCOPE_ADDR, 0x200,4)
print("Memory read data:") print("Memory read data:")
print("_=mem.mem_dump (0x%x, 0x%x, 1)"%(DATAIN_ADDRESS, count * 0x200)) print("_=mem.mem_dump (0x%x, 0x%x, 1)"%(DATAIN_ADDRESS, count * 0x200))
self.x393_mem.mem_dump (DATAIN_ADDRESS, count * 0x200, 1) self.x393_mem.mem_dump (DATAIN_ADDRESS, count * 0x200, 1)
...@@ -886,7 +892,7 @@ class x393sata(object): ...@@ -886,7 +892,7 @@ class x393sata(object):
(" R_IPp ",0x5555b57c), (" R_IPp ",0x5555b57c),
(" R_OKp ",0x3535b57c), (" R_OKp ",0x3535b57c),
(" R_RDYp ",0x4a4a957c), (" R_RDYp ",0x4a4a957c),
(" SOFp ",0x3131b57c), (" SOFp ",0x3737b57c),
(" SYNCp ",0xb5b5957c), (" SYNCp ",0xb5b5957c),
(" WTRMp ",0x5858b57c), (" WTRMp ",0x5858b57c),
(" X_RDYp ",0x5757b57c)) (" X_RDYp ",0x5757b57c))
...@@ -1053,6 +1059,17 @@ sata.reg_status() ...@@ -1053,6 +1059,17 @@ sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4) _=mem.mem_dump (0x80000ff0, 4,4)
sata.reg_status(),sata.reset_ie(),sata.err_count() sata.reg_status(),sata.reset_ie(),sata.err_count()
for block in range (1,1024):
print("\n======== Reading block %d ==============="%block)
sata.arm_logger()
sata.dd_read_dma(block, 1)
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reg_status(),sata.reset_ie(),sata.err_count()
sata.arm_logger() sata.arm_logger()
sata.setup_pio_read_identify_command() sata.setup_pio_read_identify_command()
......
tb_ahci_01.sav
View file @ e06e9e1a
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