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Commit e06e9e1a authored by Andrey Filippov's avatar Andrey Filippov
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Fixed more bugs in link layer

parent fb82aa54
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.project
View file @ e06e9e1a
...@@ -52,87 +52,87 @@ ...@@ -52,87 +52,87 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160214170313831.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160216194006906.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160214170313831.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160216194006906.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160214170313831.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160216194006906.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160214170313831.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160216194006906.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160214170313831.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160216194006906.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160214170313831.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160216194006906.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160214170151284.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160216193813011.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160214170313831.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160216194006906.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160214170151284.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160216193813011.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name> <name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160214170313831.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160216194006906.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name> <name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160214170151284.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160216193813011.log</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt-phys.dcp</name> <name>vivado_state/x393_sata-opt-phys.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160214170313831.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160216194006906.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt-power.dcp</name> <name>vivado_state/x393_sata-opt-power.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160214170313831.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160216194006906.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt.dcp</name> <name>vivado_state/x393_sata-opt.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160214170313831.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160216194006906.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-place.dcp</name> <name>vivado_state/x393_sata-place.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160214170313831.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160216194006906.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-route.dcp</name> <name>vivado_state/x393_sata-route.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160214170313831.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160216194006906.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-synth.dcp</name> <name>vivado_state/x393_sata-synth.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160214170151284.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160216193813011.dcp</location>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>
ahci/ahci_fis_receive.v
View file @ e06e9e1a
...@@ -111,6 +111,11 @@ module ahci_fis_receive#( ...@@ -111,6 +111,11 @@ module ahci_fis_receive#(
// Forwarding data to the DMA engine // Forwarding data to the DMA engine
input dma_in_ready, // DMA engine ready to accept data input dma_in_ready, // DMA engine ready to accept data
output dma_in_valid // Write data to DMA dev->memory channel output dma_in_valid // Write data to DMA dev->memory channel
,output debug_data_in_ready,
output debug_fis_end_w,
output [1:0] debug_fis_end_r,
output [1:0] debug_get_fis_busy_r
); );
//localparam FA_BITS = 6; // number of bits in received FIS address //localparam FA_BITS = 6; // number of bits in received FIS address
...@@ -241,6 +246,14 @@ localparam DATA_TYPE_ERR = 3; ...@@ -241,6 +246,14 @@ localparam DATA_TYPE_ERR = 3;
assign fis_first_invalid = fis_first_invalid_r; assign fis_first_invalid = fis_first_invalid_r;
//debug:
assign debug_data_in_ready = data_in_ready;
assign debug_fis_end_w = fis_end_w;
assign debug_fis_end_r = fis_end_r;
assign debug_get_fis_busy_r = get_fis_busy_r;
always @ (posedge mclk) begin always @ (posedge mclk) begin
if (hba_rst || dma_in_stop || pcmd_st_cleared) dma_in <= 0; if (hba_rst || dma_in_stop || pcmd_st_cleared) dma_in <= 0;
else if (dma_in_start) dma_in <= 1; else if (dma_in_start) dma_in <= 1;
......
ahci/ahci_sata_layers.v
View file @ e06e9e1a
...@@ -254,13 +254,25 @@ module ahci_sata_layers #( ...@@ -254,13 +254,25 @@ module ahci_sata_layers #(
assign serr_EI = phy_ready && (0); // RWC: Recovered Data integrity Error assign serr_EI = phy_ready && (0); // RWC: Recovered Data integrity Error
reg [1:0] debug_last_d2h_type_in; reg [1:0] debug_last_d2h_type_in;
reg [1:0] debug_last_d2h_type;
always @ (posedge clk) begin always @ (posedge clk) begin
if (d2h_fifo_wr) debug_last_d2h_type_in<= d2h_type_in; if (d2h_fifo_wr) debug_last_d2h_type_in<= d2h_type_in;
if (d2h_fifo_rd) debug_last_d2h_type<= d2h_type;
end end
assign debug_phy = {h2d_type_out[1:0],h2d_type[1:0], assign debug_phy = {h2d_type_out[1:0],h2d_type[1:0],
ll_h2d_last,d2h_valid, d2h_type[1:0], ll_h2d_last,d2h_valid, d2h_type[1:0],
debug_last_d2h_type_in, d2h_type_in[1:0], debug_last_d2h_type_in, d2h_type_in[1:0],
debug_phy0[19:0]}; debug_last_d2h_type[1:0],
d2h_fill[1:0],
1'b0,
d2h_fifo_wr,
d2h_fifo_re_regen[1:0],
d2h_waddr[1:0],
d2h_raddr[1:0],
debug_phy0[ 7:0]};
// debug_phy0[15:0]};
// debug_phy0[19:0]};
/* /*
// Data/type FIFO, device -> host // Data/type FIFO, device -> host
...@@ -341,7 +353,7 @@ module ahci_sata_layers #( ...@@ -341,7 +353,7 @@ module ahci_sata_layers #(
// FIS transmit H2D // FIS transmit H2D
// Start if all FIS is in FIFO (last word received) or at least that many is in FIFO // Start if all FIS is in FIFO (last word received) or at least that many is in FIFO
if (rst || ll_frame_req) h2d_pending <= 0; if (rst || ll_frame_req) h2d_pending <= 0; // ?
else if ((h2d_type == H2D_TYPE_FIS_HEAD) && h2d_fifo_wr) h2d_pending <= 1; else if ((h2d_type == H2D_TYPE_FIS_HEAD) && h2d_fifo_wr) h2d_pending <= 1;
if (rst) ll_frame_req <= 0; if (rst) ll_frame_req <= 0;
...@@ -400,7 +412,10 @@ module ahci_sata_layers #( ...@@ -400,7 +412,10 @@ module ahci_sata_layers #(
.datascope_waddr (datascope_waddr), // output[9:0] .datascope_waddr (datascope_waddr), // output[9:0]
.datascope_we (datascope_we), // output .datascope_we (datascope_we), // output
.datascope_di (datascope_di), // output[31:0] .datascope_di (datascope_di), // output[31:0]
.datascope_trig (ll_incom_invalidate), // ll_frame_ackn), // input datascope external trigger // .datascope_trig (ll_incom_invalidate ), // ll_frame_ackn), // input datascope external trigger
// .datascope_trig (debug_link[4:0] == 'h0a), // state_send_eof // input datascope external trigger
.datascope_trig (debug_link[4:0] == 'h02), // state_rcvr_goodcrc // input datascope external trigger
//debug_link
`endif `endif
`ifdef USE_DRP `ifdef USE_DRP
......
ahci/ahci_top.v
View file @ e06e9e1a
...@@ -664,6 +664,10 @@ module ahci_top#( ...@@ -664,6 +664,10 @@ module ahci_top#(
.last_jump_addr (last_jump_addr) .last_jump_addr (last_jump_addr)
); );
wire debug_data_in_ready; // output
wire debug_fis_end_w; // output
wire[1:0] debug_fis_end_r; // output[1:0]
wire[1:0] debug_get_fis_busy_r; // output[1:0]
axi_ahci_regs #( axi_ahci_regs #(
...@@ -724,15 +728,18 @@ module ahci_top#( ...@@ -724,15 +728,18 @@ module ahci_top#(
.afi_cache_set (set_axi_cache_mode), // output .afi_cache_set (set_axi_cache_mode), // output
.was_hba_rst (was_hba_rst), // output .was_hba_rst (was_hba_rst), // output
.was_port_rst (was_port_rst), // output .was_port_rst (was_port_rst), // output
.debug_in0 (debug_dma), // input[31:0] .debug_in0 ({ debug_data_in_ready, // output
debug_fis_end_w, // output
debug_fis_end_r[1:0], // output[1:0]
debug_get_fis_busy_r[1:0], // output[1:0]
debug_dma[25:0]}), // input[31:0]
// .debug_in1 ({xclk_period[7:0], // lower 8 bits of 12-bit value. Same frequency would be 0x800 (msb opposite to 3 next bits) // .debug_in1 ({xclk_period[7:0], // lower 8 bits of 12-bit value. Same frequency would be 0x800 (msb opposite to 3 next bits)
// debug_dma1[23:0]}), // debug_in_link), // input[31:0] // debug_dma1[23:0]}), // debug_in_link), // input[31:0]
.debug_in1 ({2'b0, .debug_in1 ({debug_in_link[15:8],
debug_in_link[13:8],
debug_dma1[23:0]}), // debug_in_link), // input[31:0] debug_dma1[23:0]}), // debug_in_link), // input[31:0]
.debug_in2 (debug_in_phy), // input[31:0] // debug from phy/link .debug_in2 (debug_in_phy), // input[31:0] // debug from phy/link
// .debug_in3 ({22'b0, last_jump_addr[9:0]}) // input[31:0]// Last jump address in the AHDCI sequencer // .debug_in3 ({22'b0, last_jump_addr[9:0]}) // input[31:0]// Last jump address in the AHDCI sequencer
.debug_in3 ({3'b0, debug_in_link[4:0], .debug_in3 ({debug_in_link[7:0],
frcv_busy,frcv_ok, // 2'b0, frcv_busy,frcv_ok, // 2'b0,
datascope_waddr[9:0], datascope_waddr[9:0],
frcv_err,frcv_ferr, // 2'b0, frcv_err,frcv_ferr, // 2'b0,
...@@ -1010,6 +1017,11 @@ module ahci_top#( ...@@ -1010,6 +1017,11 @@ module ahci_top#(
.hba_data_in_ready (d2h_ready), // output .hba_data_in_ready (d2h_ready), // output
.dma_in_ready (dma_in_ready), // input .dma_in_ready (dma_in_ready), // input
.dma_in_valid (dma_we) // output .dma_in_valid (dma_we) // output
,.debug_data_in_ready (debug_data_in_ready), // output
.debug_fis_end_w (debug_fis_end_w), // output
.debug_fis_end_r (debug_fis_end_r), // output[1:0]
.debug_get_fis_busy_r (debug_get_fis_busy_r) // output[1:0]
); );
wire ahci_fis_transmit_busy; wire ahci_fis_transmit_busy;
wire [9:0] xmit_dbg_01; wire [9:0] xmit_dbg_01;
...@@ -1075,28 +1087,147 @@ wire [9:0] xmit_dbg_01; ...@@ -1075,28 +1087,147 @@ wire [9:0] xmit_dbg_01;
// Datascope code // Datascope code
`ifdef USE_DATASCOPE `ifdef USE_DATASCOPE
// Datascope interface (write to memory that can be software-read) // Datascope interface (write to memory that can be software-read)
// wire datascope_clk;
// wire [ADDRESS_BITS-1:0] datascope_waddr;
// wire datascope_we;
// wire [31:0] datascope_di;
localparam DATASCOPE_CFIS_START=0; localparam DATASCOPE_CFIS_START=0;
localparam DATASCOPE_INCOMING_POST=32;
reg [ADDRESS_BITS-1:0] datascope_waddr_r; reg [ADDRESS_BITS-1:0] datascope_waddr_r;
reg [1:0] datascope_run; reg [1:0] datascope_run;
/// reg [8:0] datascope_cntr;
/// reg datascope_was_busy; reg datascope_link_run;
wire dataskope_is_state_send_ready = (debug_in_link[4:0] == 16);
wire dataskope_is_state_idle = (debug_in_link[4:0] == 22);
reg dataskope_was_state_send_ready;
reg [3:0] datascope_id;
wire datascope_incoming_start = debug_in_link[22]; // set_rcvr_wait; // start logging
wire datascope_incoming_started = debug_in_phy[21:20] == 1; //
wire datascope_incomining_preend = debug_in_phy[21]; // d2h_type_in[1
reg [2:0] datascope_incoming_run;
reg [7:0] datascope_incoming_cntr;
reg datascope_receive_fis;
always @(posedge mclk) begin
if (mrst) datascope_receive_fis <= 0;
else if (datascope_incoming_start) datascope_receive_fis <= 1;
else if (frcv_get_dsfis ||
frcv_get_psfis ||
frcv_get_rfis ||
frcv_get_sdbfis ||
frcv_get_ufis ||
frcv_get_data_fis ||
frcv_get_ignore) datascope_receive_fis <= 0;
if (mrst) datascope_incoming_run[0] <= 0;
else if (datascope_incoming_start || datascope_receive_fis) datascope_incoming_run[0] <= 1;
else if (datascope_incoming_cntr == 0) datascope_incoming_run[0] <= 0;
if (mrst || datascope_incoming_start) datascope_incoming_run[1] <= 0;
else if (datascope_incoming_run[0] && datascope_incoming_started) datascope_incoming_run[1] <= 1;
else if (datascope_incoming_run[2]) datascope_incoming_run[1] <= 0;
if (mrst || datascope_incoming_start) datascope_incoming_run[2] <= 0;
else if (datascope_incoming_run[1] && datascope_incomining_preend) datascope_incoming_run[2] <= 1;
else if (datascope_incoming_cntr == 0) datascope_incoming_run[2] <= 0;
if (mrst || !datascope_incoming_run[2] ||
datascope_incoming_start ||
datascope_receive_fis) datascope_incoming_cntr <= DATASCOPE_INCOMING_POST;
else if (|datascope_incoming_cntr) datascope_incoming_cntr <= datascope_incoming_cntr - 1;
end
assign datascope_clk = mclk; assign datascope_clk = mclk;
assign datascope_waddr = datascope_waddr_r; assign datascope_waddr = datascope_waddr_r;
// assign datascope_di = datascope_run[0]? {h2d_type, dma_dav, datascope_was_busy, xmit_dbg_01, datascope_cntr[3:0], h2d_data[15:0]} : {{32-ADDRESS_BITS{1'b0}},datascope_waddr_r};
/// assign datascope_di = datascope_run[0]? {h2d_type, xmit_dbg_01, datascope_cntr[3:0], h2d_data[15:0]} : {{32-ADDRESS_BITS{1'b0}},datascope_waddr_r};
// Datascope provides just outgoing data, followed by the dword counter with 16'hffff in the high word
// assign datascope_we = (datascope_run[0] && h2d_valid && h2d_ready) || (datascope_run == 2);
// assign datascope_di = datascope_run[0]? {h2d_data[31:0]} : {16'hffff,{16-ADDRESS_BITS{1'b0}},datascope_waddr_r};
// assign datascope_we = (datascope_run[0] && h2d_valid && h2d_ready) || (datascope_run == 2) || d2h_ready; // assign datascope_we = (datascope_run[0] && h2d_valid && h2d_ready) || fsnd_done || d2h_ready || xmit_ok || xmit_err;
// assign datascope_di = d2h_ready? {d2h_type, d2h_data[29:0]}:(datascope_run[0]? {h2d_data[31:0]} : {16'hffff,{16-ADDRESS_BITS{1'b0}},datascope_waddr_r}); // assign datascope_we = (datascope_run[0] && h2d_valid && h2d_ready) || d2h_ready || datascope_link_run;
assign datascope_we = (datascope_run[0] && h2d_valid && h2d_ready) || fsnd_done || d2h_ready; assign datascope_we = (datascope_run[0] && h2d_valid && h2d_ready) || datascope_incoming_run[0] || datascope_link_run;
assign datascope_di = d2h_ready? {d2h_type, d2h_data[29:0]}:(datascope_run[0]? {h2d_data[31:0]} : {13'hffff,fsnd_dx_err[2:0],{16-ADDRESS_BITS{1'b0}},datascope_waddr_r}); //
// assign datascope_di = d2h_ready? {d2h_type,
assign datascope_di = datascope_incoming_run[0]? {d2h_type,
debug_in_link[26], // state idle
debug_in_link[4:0], // encoded state (1 cycle later)
d2h_ready,
d2h_valid,
debug_in_phy[21:20],
datascope_incoming_start,
datascope_incoming_run[2:0],
datascope_id[3:0],
d2h_type[1:0],
frcv_busy,
1'b0,
debug_in_phy[15:8]}:
// d2h_data[8:0]}:
(datascope_run[0]? {h2d_data[31:0]} : {// will appear for fsnd_done || xmit_ok || xmit_err
debug_in_link[7:0],
debug_in_link[31],
debug_in_link[30],
debug_in_link[29], // xmit_ok,
debug_in_link[28], //xmit_err,
debug_in_link[27], // 1'b0,
debug_in_link[26],
debug_in_link[25],
debug_in_link[24], // fsnd_dx_err[1], //fsnd_dx_err[2:0],
debug_in_link[23],
datascope_id[2:0], {12-ADDRESS_BITS{1'b0}}, datascope_waddr_r});
/*
assign debug_out[ 4: 0] = debug_states_encoded;
assign debug_out[7: 5] = {
rcvd_dword[CODE_SYNCP],
rcvd_dword[CODE_OKP],
alignes_pair};
assign debug_out[31] = rcvd_dword[CODE_ALIGNP];
assign debug_out[30] = set_send_sof;
assign debug_out[29] = clr_send_rdy;
assign debug_out[28] = state_send_rdy;
assign debug_out[27] = state_send_sof;
assign debug_out[26] = state_idle;
assign debug_out[25] = state_send_data;
assign debug_out[24] = (state_send_sof | set_send_sof & ~alignes_pair);
assign debug_out[23] = (clr_send_sof & ~alignes_pair);
//assign debug_out[15: 5] = debug_to_first_err[14:4];
assign debug_out[22:16] = debug_rcvd_dword[6:0];
assign debug_out[15: 8] = {
debug_was_wait, // state was wait when last CODE_ERRP/CODE_OKP was received
debug_was_idle, // state was idle when last CODE_ERRP/CODE_OKP was received
debug_was_OK_ERR[1:0],
debug_was_state_wait,
debug_was_frame_done,
debug_was_got_escape,
~debug_CODE_SYNCP[1]};
assign datascope_di = d2h_ready? {d2h_type, d2h_data[29:0]}:(datascope_run[0]? {h2d_data[31:0]} : {// will appear for fsnd_done || xmit_ok || xmit_err
debug_in_link[7:0],
debug_in_link[31],
debug_in_link[30],
debug_in_link[29], // xmit_ok,
debug_in_link[28], //xmit_err,
debug_in_link[27], // 1'b0,
debug_in_link[26],
debug_in_link[25],
debug_in_link[24],//fsnd_dx_err[2:0],
debug_in_link[23], debug_in_link[25],
datascope_id[2:0], {12-ADDRESS_BITS{1'b0}}, datascope_waddr_r});
assign debug_out[27] = state_send_sof;
assign debug_out[26] = state_idle;
_out[31] = rcvd_dword[CODE_ALIGNP];
assign debug_out[ 4: 0] = debug_states_encoded;
assign debug_out[7: 5] = {
rcvd_dword[CODE_SYNCP],
rcvd_dword[CODE_OKP],
alignes_pair};
*/
/// assign datascope_we = |datascope_run; /// assign datascope_we = |datascope_run;
/* /*
assign datascope_di = datascope_run[0]? {h2d_type, // 2 bits assign datascope_di = datascope_run[0]? {h2d_type, // 2 bits
...@@ -1112,12 +1243,23 @@ wire [9:0] xmit_dbg_01; ...@@ -1112,12 +1243,23 @@ wire [9:0] xmit_dbg_01;
if (mrst) datascope_run[0] <= 0; if (mrst) datascope_run[0] <= 0;
else if (fsnd_cfis_xmit) datascope_run[0] <= 1; else if (fsnd_cfis_xmit) datascope_run[0] <= 1;
else if (h2d_valid && h2d_ready && (h2d_type == 2)) datascope_run[0] <= 0; else if (h2d_valid && h2d_ready && (h2d_type == 2)) datascope_run[0] <= 0;
if (mrst) datascope_link_run <= 0;
else if (dataskope_is_state_send_ready && !dataskope_was_state_send_ready) datascope_link_run <= 1; // state_send_sof
else if (dataskope_is_state_idle) datascope_link_run <= 0; // state_idle
dataskope_was_state_send_ready <= dataskope_is_state_send_ready;
datascope_run[1] <= datascope_run[0]; datascope_run[1] <= datascope_run[0];
if (fsnd_cfis_xmit) datascope_waddr_r <= DATASCOPE_CFIS_START; if (fsnd_cfis_xmit) datascope_waddr_r <= DATASCOPE_CFIS_START;
else if (datascope_we) datascope_waddr_r <= datascope_waddr_r + 1; else if (datascope_we) datascope_waddr_r <= datascope_waddr_r + 1;
if (mrst) datascope_id <= 0;
else if (fsnd_cfis_xmit) datascope_id <= datascope_id + 1;
/// if (fsnd_cfis_xmit) datascope_cntr <= 0; /// if (fsnd_cfis_xmit) datascope_cntr <= 0;
/// else datascope_cntr <= datascope_cntr + 1; /// else datascope_cntr <= datascope_cntr + 1;
......
generated/action_decoder.v
View file @ e06e9e1a
/******************************************************************************* /*******************************************************************************
* Module: action_decoder * Module: action_decoder
* Date:2016-02-13 * Date:2016-02-16
* Author: auto-generated file, see ahci_fsm_sequence.py * Author: auto-generated file, see ahci_fsm_sequence.py
* Description: Decode sequencer code to 1-hot actions * Description: Decode sequencer code to 1-hot actions
*******************************************************************************/ *******************************************************************************/
......
generated/condition_mux.v
View file @ e06e9e1a
/******************************************************************************* /*******************************************************************************
* Module: condition_mux * Module: condition_mux
* Date:2016-02-13 * Date:2016-02-16
* Author: auto-generated file, see ahci_fsm_sequence.py * Author: auto-generated file, see ahci_fsm_sequence.py
* Description: Select condition * Description: Select condition
*******************************************************************************/ *******************************************************************************/
......
helpers/ahci_fsm_sequence.py
View file @ e06e9e1a
...@@ -135,8 +135,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP}, ...@@ -135,8 +135,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{ GOTO:'P:NotRunning'}, { GOTO:'P:NotRunning'},
{LBL:'P:RegFisUpdate', ACT: 'GET_RFIS*'}, # get_rfis {LBL:'P:RegFisUpdate', ACT: 'GET_RFIS*'}, # get_rfis
{IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal'}, # 1. fis_err {IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal_R_ERR'}, # 1. fis_err
{IF: 'FIS_FERR', GOTO:'ERR:Fatal'}, # 2. fis_ferr {IF: 'FIS_FERR', GOTO:'ERR:Fatal_R_ERR'}, # 2. fis_ferr
{ GOTO:'P:RegFisAccept'}, { GOTO:'P:RegFisAccept'},
{LBL:'P:RegFisAccept', ACT: 'R_OK'}, # send R_OK {LBL:'P:RegFisAccept', ACT: 'R_OK'}, # send R_OK
...@@ -203,18 +203,18 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP}, ...@@ -203,18 +203,18 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{LBL:'NDR:Entry', ACT: 'NOP'}, {LBL:'NDR:Entry', ACT: 'NOP'},
# {IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal'}, # 1. fis_err # {IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal_R_ERR'}, # 1. fis_err
# {IF: 'FIS_FERR', GOTO:'ERR:Fatal'}, # 2. fis_ferr # {IF: 'FIS_FERR', GOTO:'ERR:Fatal_R_ERR'}, # 2. fis_ferr
{ GOTO:'NDR:Accept'}, # 4. { GOTO:'NDR:Accept'}, # 4.
{LBL:'NDR:IgnoreNR', ACT: 'GET_IGNORE*'}, # get_ignore This one is not in docs, just to empty FIS FIFO {LBL:'NDR:IgnoreNR', ACT: 'GET_IGNORE*'}, # get_ignore This one is not in docs, just to empty FIS FIFO
{IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal'}, # 1. fis_err {IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal_R_ERR'}, # 1. fis_err
{IF: 'FIS_FERR', GOTO:'ERR:Fatal'}, # 2. fis_ferr {IF: 'FIS_FERR', GOTO:'ERR:Fatal_R_ERR'}, # 2. fis_ferr
{ GOTO:'P:OkIdle'}, # { GOTO:'P:OkIdle'}, #
{LBL:'NDR:IgnoreIdle', ACT: 'GET_IGNORE*'}, # get_ignore This one is not in docs, just to empty FIS FIFO {LBL:'NDR:IgnoreIdle', ACT: 'GET_IGNORE*'}, # get_ignore This one is not in docs, just to empty FIS FIFO
{IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal'}, # 1. fis_err {IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal_R_ERR'}, # 1. fis_err
{IF: 'FIS_FERR', GOTO:'ERR:Fatal'}, # 2. fis_ferr {IF: 'FIS_FERR', GOTO:'ERR:Fatal_R_ERR'}, # 2. fis_ferr
{ GOTO:'P:OkNotRunning'}, # { GOTO:'P:OkNotRunning'}, #
...@@ -273,8 +273,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP}, ...@@ -273,8 +273,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{ GOTO:'PIO:Update'}, # 2. { GOTO:'PIO:Update'}, # 2.
#5.3.8 D2H Register FIS Receive States #5.3.8 D2H Register FIS Receive States
{LBL:'RegFIS:Entry', ACT: 'GET_RFIS*'}, # get_rfis {LBL:'RegFIS:Entry', ACT: 'GET_RFIS*'}, # get_rfis
{IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal'}, # 1. fis_err {IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal_R_ERR'}, # 1. fis_err
{IF: 'FIS_FERR', GOTO:'ERR:Fatal'}, # 2. fis_ferr {IF: 'FIS_FERR', GOTO:'ERR:Fatal_R_ERR'}, # 2. fis_ferr
{ GOTO:'RegFIS:Accept'}, # { GOTO:'RegFIS:Accept'}, #
{LBL:'RegFIS:Accept', ACT: 'R_OK'}, # send R_OK {LBL:'RegFIS:Accept', ACT: 'R_OK'}, # send R_OK
...@@ -296,8 +296,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP}, ...@@ -296,8 +296,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
#RegFIS:SetSig skipped, done in RegFIS:UpdateSig #RegFIS:SetSig skipped, done in RegFIS:UpdateSig
#5.3.9 PIO Setup Receive States #5.3.9 PIO Setup Receive States
{LBL:'PIO:Entry', ACT: 'GET_PSFIS*'}, # get_psfis, includes all steps 1..9 {LBL:'PIO:Entry', ACT: 'GET_PSFIS*'}, # get_psfis, includes all steps 1..9
{IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal'}, # 1. fis_err {IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal_R_ERR'}, # 1. fis_err
{IF: 'FIS_FERR', GOTO:'ERR:Fatal'}, # 2. fis_ferr {IF: 'FIS_FERR', GOTO:'ERR:Fatal_R_ERR'}, # 2. fis_ferr
{ GOTO:'PIO:Accept' }, { GOTO:'PIO:Accept' },
{LBL:'PIO:Accept', ACT: 'R_OK'}, # get_psfis, includes all steps 1..9 {LBL:'PIO:Accept', ACT: 'R_OK'}, # get_psfis, includes all steps 1..9
...@@ -322,8 +322,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP}, ...@@ -322,8 +322,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
#PIO:SetIS, PIO:GenIntr are handled by hardware, skipping #PIO:SetIS, PIO:GenIntr are handled by hardware, skipping
#5.3.10 Data Transmit States #5.3.10 Data Transmit States
{LBL:'DX:EntryIgnore', ACT: 'GET_IGNORE*'}, # Read/Ignore FIS in FIFO (not in docs) {LBL:'DX:EntryIgnore', ACT: 'GET_IGNORE*'}, # Read/Ignore FIS in FIFO (not in docs)
{IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal'}, # 1. fis_err {IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal_R_ERR'}, # 1. fis_err
{IF: 'FIS_FERR', GOTO:'ERR:Fatal'}, # 2. fis_ferr {IF: 'FIS_FERR', GOTO:'ERR:Fatal_R_ERR'}, # 2. fis_ferr
{ GOTO:'DX:Accept'}, # { GOTO:'DX:Accept'}, #
{LBL:'DX:Accept', ACT: 'R_OK'}, # send R_OK {LBL:'DX:Accept', ACT: 'R_OK'}, # send R_OK
...@@ -355,10 +355,10 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP}, ...@@ -355,10 +355,10 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{ GOTO:'DR:Receive'}, { GOTO:'DR:Receive'},
{LBL:'DR:Receive', ACT: 'GET_DATA_FIS*'}, # get_data_fis {LBL:'DR:Receive', ACT: 'GET_DATA_FIS*'}, # get_data_fis
{IF: 'FIS_ERR', GOTO:'ERR:Fatal'}, # 3. fis_err - checking for errors first to give some time for fis_extra {IF: 'FIS_ERR', GOTO:'ERR:Fatal_R_ERR'}, # 3. fis_err - checking for errors first to give some time for fis_extra
# to reveal itself from the ahci_dma module (ahci_fis_receive does not need it) # to reveal itself from the ahci_dma module (ahci_fis_receive does not need it)
{IF: 'FIS_FERR', GOTO:'ERR:Fatal'}, # 3a. fis_ferr {IF: 'FIS_FERR', GOTO:'ERR:Fatal_R_ERR'}, # 3a. fis_ferr
{IF: 'FIS_EXTRA', GOTO:'ERR:Non-Fatal'}, # 1. fis_extra {IF: 'FIS_EXTRA', GOTO:'ERR:Non-Fatal_R_ERR'}, # 1. fis_extra
{ GOTO:'DR:UpdateByteCount'}, # 2. fis_ok implied { GOTO:'DR:UpdateByteCount'}, # 2. fis_ok implied
{LBL:'DR:UpdateByteCount', ACT: 'R_OK'}, # send_R_OK to device {LBL:'DR:UpdateByteCount', ACT: 'R_OK'}, # send_R_OK to device
...@@ -370,8 +370,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP}, ...@@ -370,8 +370,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
# 5.3.12 DMA Setup Receive States # 5.3.12 DMA Setup Receive States
{LBL:'DmaSet:Entry', ACT: 'GET_DSFIS*'}, # get_dsfis {LBL:'DmaSet:Entry', ACT: 'GET_DSFIS*'}, # get_dsfis
{IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal'}, # 1. fis_err {IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal_R_ERR'}, # 1. fis_err
{IF: 'FIS_FERR', GOTO:'ERR:Fatal'}, # 2. fis_ferr {IF: 'FIS_FERR', GOTO:'ERR:Fatal_R_ERR'}, # 2. fis_ferr
{ GOTO:'DmaSet:Accept'}, # { GOTO:'DmaSet:Accept'}, #
{LBL:'DmaSet:Accept', ACT: 'R_OK'}, # send R_OK {LBL:'DmaSet:Accept', ACT: 'R_OK'}, # send R_OK
...@@ -386,8 +386,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP}, ...@@ -386,8 +386,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{ GOTO:'P:Idle' }, # 3. { GOTO:'P:Idle' }, # 3.
#5.3.13 Set Device Bits States #5.3.13 Set Device Bits States
{LBL:'SDB:Entry', ACT: 'GET_SDBFIS*'}, # get_sdbfis Is in only for Native CC ? {LBL:'SDB:Entry', ACT: 'GET_SDBFIS*'}, # get_sdbfis Is in only for Native CC ?
{IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal'}, # 1. fis_err {IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal_R_ERR'}, # 1. fis_err
{IF: 'FIS_FERR', GOTO:'ERR:Fatal'}, # 2. fis_ferr {IF: 'FIS_FERR', GOTO:'ERR:Fatal_R_ERR'}, # 2. fis_ferr
{ GOTO:'SDB:Accept' }, # 3. { GOTO:'SDB:Accept' }, # 3.
{LBL:'SDB:Accept', ACT: 'R_OK'}, # get_sdbfis Is in only for Native CC ? {LBL:'SDB:Accept', ACT: 'R_OK'}, # get_sdbfis Is in only for Native CC ?
...@@ -400,8 +400,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP}, ...@@ -400,8 +400,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{ GOTO:'PM:Aggr' }, # 5. { GOTO:'PM:Aggr' }, # 5.
#5.3.14 Unknown FIS Receive States #5.3.14 Unknown FIS Receive States
{LBL:'UFIS:Entry', ACT: 'GET_UFIS*'}, # get_ufis {LBL:'UFIS:Entry', ACT: 'GET_UFIS*'}, # get_ufis
{IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal'}, # 1. fis_err {IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal_R_ERR'}, # 1. fis_err
{IF: 'FIS_FERR', GOTO:'ERR:Fatal'}, # 2. fis_ferr {IF: 'FIS_FERR', GOTO:'ERR:Fatal_R_ERR'}, # 2. fis_ferr
{ GOTO:'UFIS:Accept' }, # { GOTO:'UFIS:Accept' }, #
{LBL:'UFIS:Accept', ACT: 'R_OK'}, # get_ufis {LBL:'UFIS:Accept', ACT: 'R_OK'}, # get_ufis
...@@ -411,8 +411,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP}, ...@@ -411,8 +411,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
#5.3.15 BIST States #5.3.15 BIST States
{LBL:'BIST:FarEndLoopback', ACT: 'GET_IGNORE*'}, # get_ignore {LBL:'BIST:FarEndLoopback', ACT: 'GET_IGNORE*'}, # get_ignore
{IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal'}, # 1. fis_err {IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal_R_ERR'}, # 1. fis_err
{IF: 'FIS_FERR', GOTO:'ERR:Fatal'}, # 2. fis_ferr {IF: 'FIS_FERR', GOTO:'ERR:Fatal_R_ERR'}, # 2. fis_ferr
{ GOTO:'BIST:FarEndLoopbackAccept'}, # 1. (IRQ states are handled) { GOTO:'BIST:FarEndLoopbackAccept'}, # 1. (IRQ states are handled)
{LBL:'BIST:FarEndLoopbackAccept', ACT: 'R_OK'}, # send R_OK {LBL:'BIST:FarEndLoopbackAccept', ACT: 'R_OK'}, # send R_OK
...@@ -420,8 +420,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP}, ...@@ -420,8 +420,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{ GOTO:'BIST:TestLoop'}, # 1. { GOTO:'BIST:TestLoop'}, # 1.
{LBL:'BIST:TestOngoing', ACT: 'GET_IGNORE*'}, # get_ignore {LBL:'BIST:TestOngoing', ACT: 'GET_IGNORE*'}, # get_ignore
{IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal'}, # 1. fis_err {IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal_R_ERR'}, # 1. fis_err
{IF: 'FIS_FERR', GOTO:'ERR:Fatal'}, # 2. fis_ferr {IF: 'FIS_FERR', GOTO:'ERR:Fatal_R_ERR'}, # 2. fis_ferr
{ GOTO:'BIST:TestLoopAccept'}, # { GOTO:'BIST:TestLoopAccept'}, #
{LBL:'BIST:TestLoopAccept', ACT: 'R_OK'}, # {LBL:'BIST:TestLoopAccept', ACT: 'R_OK'}, #
...@@ -434,8 +434,10 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP}, ...@@ -434,8 +434,10 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{ ACT: 'SIRQ_IF'}, # sirq_IF { ACT: 'SIRQ_IF'}, # sirq_IF
{ GOTO:'ERR:WaitForClear' }, { GOTO:'ERR:WaitForClear' },
{LBL:'ERR:Fatal', ACT: 'R_ERR'}, # Send R_ERR to device {LBL:'ERR:Fatal_R_ERR', ACT: 'R_ERR'}, # Send 'R_ERR' to device. SATA sais it should be Transport L, AHCI - Link L
{ ACT: 'SIRQ_IF'}, # sirq_IF { GOTO:'ERR:Fatal' }, #
{LBL:'ERR:Fatal', ACT: 'SIRQ_IF'}, # sirq_IF
{ GOTO:'ERR:WaitForClear' }, { GOTO:'ERR:WaitForClear' },
{LBL:'ERR:FatalTaskfile', ACT: 'SIRQ_TFE'}, # sirq_TFE {LBL:'ERR:FatalTaskfile', ACT: 'SIRQ_TFE'}, # sirq_TFE
...@@ -444,8 +446,10 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP}, ...@@ -444,8 +446,10 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{LBL:'ERR:WaitForClear', ACT: 'NOP'}, # {LBL:'ERR:WaitForClear', ACT: 'NOP'}, #
{ GOTO:'ERR:WaitForClear' }, # Loop until PxCMD.ST is cleared by software { GOTO:'ERR:WaitForClear' }, # Loop until PxCMD.ST is cleared by software
{LBL:'ERR:Non-Fatal', ACT: 'NOP'}, # Do anything else here? {LBL:'ERR:Non-Fatal_R_ERR', ACT: 'R_ERR'}, # Send 'R_ERR' to device. SATA says it should be Transport L, AHCI - Link L
{ ACT: 'SIRQ_INF'}, # sirq_INF { GOTO:'ERR:Non-Fatal' }, #
{LBL:'ERR:Non-Fatal', ACT: 'SIRQ_INF'}, # sirq_INF
{ GOTO:'P:Idle'}, # { GOTO:'P:Idle'}, #
] ]
def get_cnk (start,end,level): def get_cnk (start,end,level):
......
host/link.v
View file @ e06e9e1a
...@@ -36,7 +36,11 @@ ...@@ -36,7 +36,11 @@
module link #( module link #(
// 4 = dword. 4-bytes aligned data transfers TODO 2 = word - easy, 8 = qword - difficult // 4 = dword. 4-bytes aligned data transfers TODO 2 = word - easy, 8 = qword - difficult
parameter DATA_BYTE_WIDTH = 4, parameter DATA_BYTE_WIDTH = 4,
`ifdef SIMULATION
parameter ALIGNES_PERIOD = 10 // period of sending ALIGNp pairs
`else
parameter ALIGNES_PERIOD = 252 // period of sending ALIGNp pairs parameter ALIGNES_PERIOD = 252 // period of sending ALIGNp pairs
`endif
) )
( (
// TODO insert watchdogs // TODO insert watchdogs
...@@ -130,8 +134,9 @@ wire [31:0] crc_dword; ...@@ -130,8 +134,9 @@ wire [31:0] crc_dword;
assign link_established = phy_ready; assign link_established = phy_ready;
// send primitives variety count, including CRC and DATA as primitives // send primitives variety count, including CRC and DATA as primitives
localparam PRIM_NUM = 16; // 15; localparam PRIM_NUM = 16; // 15;
wire [PRIM_NUM - 1:0] rcvd_dword; // shows current processing primitive (or just data dword) wire [PRIM_NUM - 1:0] rcvd_dword; // shows current processing primitive (or just data dword)
wire dword_val; wire dword_val; // any valid primitive/data
wire dword_val_na; // any valid primitive but ALIGNp
// list of bits of rcvd_dword // list of bits of rcvd_dword
localparam CODE_DATA = 0; // DATA localparam CODE_DATA = 0; // DATA
localparam CODE_CRC = 1; // CRC localparam CODE_CRC = 1; // CRC
...@@ -179,17 +184,17 @@ wire data_txing = data_txing_r & ~state_send_crc; ...@@ -179,17 +184,17 @@ wire data_txing = data_txing_r & ~state_send_crc;
// does not work with ALIGNp pair // does not work with ALIGNp pair
/* /*
always @ (posedge clk) begin always @ (posedge clk) begin
/// data_txing <= rst | (data_last_in & data_strobe_out | dword_val & rcvd_dword[CODE_DMATP]) ? 1'b0 : frame_req ? 1'b1 : data_txing; /// data_txing <= rst | (data_last_in & data_strobe_out | dword_val_na & rcvd_dword[CODE_DMATP]) ? 1'b0 : frame_req ? 1'b1 : data_txing;
if (rst || if (rst ||
(data_last_in && data_strobe_out) || (data_last_in && data_strobe_out) ||
(dword_val && rcvd_dword[CODE_DMATP])) data_txing <= 0; (dword_val_na && rcvd_dword[CODE_DMATP])) data_txing <= 0;
else if (frame_req) data_txing <= 1; else if (frame_req) data_txing <= 1;
end end
*/ */
// Trying alternative, as SM sometimes got stuck in state_send_data, last was set // Trying alternative, as SM sometimes got stuck in state_send_data, last was set
// Make it safe // Make it safe
always @ (posedge clk) begin always @ (posedge clk) begin
/// data_txing <= rst | (data_last_in & data_strobe_out | dword_val & rcvd_dword[CODE_DMATP]) ? 1'b0 : frame_req ? 1'b1 : data_txing; /// data_txing <= rst | (data_last_in & data_strobe_out | dword_val_na & rcvd_dword[CODE_DMATP]) ? 1'b0 : frame_req ? 1'b1 : data_txing;
if (rst) data_txing_r <= 0; if (rst) data_txing_r <= 0;
else if (frame_req) data_txing_r <= 1; else if (frame_req) data_txing_r <= 1;
else if (state_send_crc) data_txing_r <= 0; else if (state_send_crc) data_txing_r <= 0;
...@@ -309,14 +314,24 @@ assign state_idle = ~state_sync_esc ...@@ -309,14 +314,24 @@ assign state_idle = ~state_sync_esc
& ~state_rcvr_badend; & ~state_rcvr_badend;
// got an escaping primitive = request to cancel the transmission // got an escaping primitive = request to cancel the transmission
wire got_escape; // may be 1 cycle, need to extend over alignes_pair
assign got_escape = dword_val & rcvd_dword[CODE_SYNCP]; //wire got_escape_w;
//reg got_escape_pend;
//wire got_escape = got_escape_w || got_escape_pend;
//assign got_escape_w = dword_val & rcvd_dword[CODE_SYNCP];
wire got_escape = dword_val & rcvd_dword[CODE_SYNCP]; // can wait over alignes pair
reg sync_escape_req_r; // ahci sends 1 single-clock pulse, it may hit alignes_pair
always @ (posedge clk) begin
// got_escape_pend <= alignes_pair && (got_escape_w || got_escape_pend);
sync_escape_req_r <= alignes_pair && (sync_escape_req || sync_escape_req_r);
end
//sync_escape_req
// escaping is done // escaping is done
assign sync_escape_ack = state_sync_esc; assign sync_escape_ack = state_sync_esc;
wire alignes_pair; // pauses every state go give a chance to insert 2 align primitives on a line at least every 256 dwords due to spec reg alignes_pair; // pauses every state go give a chance to insert 2 align primitives on a line at least every 256 dwords due to spec
//wire alignes_pair_0; // time for 1st align primitive //wire alignes_pair_0; // time for 1st align primitive
//wire alignes_pair_1; // time for 2nd align primitive //wire alignes_pair_1; // time for 2nd align primitive
reg [8:0] alignes_timer; reg [8:0] alignes_timer;
...@@ -333,17 +348,20 @@ reg [8:0] alignes_timer; ...@@ -333,17 +348,20 @@ reg [8:0] alignes_timer;
//select_prim[CODE_ALIGNP] //select_prim[CODE_ALIGNP]
//ALIGNES_PERIOD //ALIGNES_PERIOD
reg alignes_pair_0; // time for 1st align primitive reg alignes_pair_0; // time for 1st align primitive
reg alignes_pair_1; // time for 2nd align primitive //reg alignes_pair_1; // time for 2nd align primitive
always @ (posedge clk) begin always @ (posedge clk) begin
/// if (!link_established_r || select_prim[CODE_ALIGNP]) alignes_timer <= ALIGNES_PERIOD; /// if (!link_established_r || select_prim[CODE_ALIGNP]) alignes_timer <= ALIGNES_PERIOD;
if (!phy_ready || select_prim[CODE_ALIGNP]) alignes_timer <= ALIGNES_PERIOD; if (!phy_ready || select_prim[CODE_ALIGNP]) alignes_timer <= ALIGNES_PERIOD;
else alignes_timer <= alignes_timer -1; else alignes_timer <= alignes_timer -1;
alignes_pair_0 <= alignes_timer == 0; alignes_pair_0 <= alignes_timer == 0;
alignes_pair_1 <= alignes_pair_0; // alignes_pair_1 <= alignes_pair_0;
alignes_pair <= phy_ready && ((alignes_timer == 0) || alignes_pair_0);
end end
///assign alignes_pair = link_established_r && (alignes_pair_0 | alignes_pair_1); ///assign alignes_pair = link_established_r && (alignes_pair_0 | alignes_pair_1);
assign alignes_pair = phy_ready && (alignes_pair_0 | alignes_pair_1); // assign alignes_pair = phy_ready && (alignes_pair_0 | alignes_pair_1);
always @ (posedge clk) begin always @ (posedge clk) begin
link_bad_crc <= state_rcvr_eof & crc_bad; link_bad_crc <= state_rcvr_eof & crc_bad;
...@@ -358,41 +376,60 @@ always @ (posedge clk) begin ...@@ -358,41 +376,60 @@ always @ (posedge clk) begin
end end
// Whole transitions table, literally from doc pages 311-328 // Whole transitions table, literally from doc pages 311-328
assign set_sync_esc = sync_escape_req; assign set_sync_esc = sync_escape_req || sync_escape_req_r; // extended over alignes_pair
assign set_nocommerr = ~phy_ready & ~state_nocomm & ~state_reset; assign set_nocommerr = ~phy_ready & ~state_nocomm & ~state_reset;
assign set_nocomm = state_nocommerr; assign set_nocomm = state_nocommerr;
///assign set_align = state_reset & ~link_reset; ///assign set_align = state_reset & ~link_reset;
///assign set_align = state_reset & ~link_reset & rcvd_dword[CODE_ALIGNP]; ///assign set_align = state_reset & ~link_reset & rcvd_dword[CODE_ALIGNP];
assign set_align = 0; // never, as this state is handled by OOB assign set_align = 0; // never, as this state is handled by OOB
assign set_reset = link_reset; assign set_reset = link_reset;
assign set_send_rdy = state_idle & frame_req; assign set_send_rdy = state_idle & frame_req;
assign set_send_sof = state_send_rdy & phy_ready & dword_val & rcvd_dword[CODE_RRDYP];
assign set_send_sof = state_send_rdy & phy_ready & dword_val & rcvd_dword[CODE_RRDYP];
assign set_send_data = state_send_sof & phy_ready assign set_send_data = state_send_sof & phy_ready
| state_send_rhold & data_txing & ~dec_err & dword_val & ~rcvd_dword[CODE_HOLDP] & ~rcvd_dword[CODE_SYNCP] & ~rcvd_dword[CODE_DMATP] // | state_send_rhold & data_txing & ~dec_err & dword_val_na & ~rcvd_dword[CODE_HOLDP] & ~rcvd_dword[CODE_SYNCP] & ~rcvd_dword[CODE_DMATP]
| state_send_shold & data_txing & data_val_in & dword_val & ~rcvd_dword[CODE_HOLDP] & ~rcvd_dword[CODE_SYNCP]; // | state_send_shold & data_txing & data_val_in & dword_val_na & ~rcvd_dword[CODE_HOLDP] & ~rcvd_dword[CODE_SYNCP];
assign set_send_rhold = state_send_data & data_txing & data_val_in & ~data_last_in & dword_val & rcvd_dword[CODE_HOLDP] | state_send_rhold & data_txing & ~dec_err & dword_val_na & ~rcvd_dword[CODE_HOLDP] & ~rcvd_dword[CODE_SYNCP] & ~rcvd_dword[CODE_DMATP]
| state_send_shold & data_txing & data_val_in & dword_val & rcvd_dword[CODE_HOLDP]; | state_send_shold & data_txing & data_val_in & dword_val_na & ~rcvd_dword[CODE_HOLDP] & ~rcvd_dword[CODE_SYNCP];
assign set_send_shold = state_send_data & data_txing & ~data_val_in & dword_val & ~rcvd_dword[CODE_SYNCP];
assign set_send_crc = state_send_data & data_txing & data_val_in & data_last_in & dword_val & ~rcvd_dword[CODE_SYNCP] assign set_send_rhold = state_send_data & data_txing & data_val_in & ~data_last_in & dword_val & rcvd_dword[CODE_HOLDP]
| state_send_data & dword_val & rcvd_dword[CODE_DMATP]; | state_send_shold & data_txing & data_val_in & dword_val & rcvd_dword[CODE_HOLDP];
assign set_send_eof = state_send_crc & phy_ready & dword_val & ~rcvd_dword[CODE_SYNCP];
assign set_wait = state_send_eof & phy_ready & dword_val & ~rcvd_dword[CODE_SYNCP]; assign set_send_shold = state_send_data & data_txing & ~data_val_in & dword_val & ~rcvd_dword[CODE_SYNCP];
assign set_send_crc = state_send_data & data_txing & data_val_in & data_last_in & dword_val & ~rcvd_dword[CODE_SYNCP]
| state_send_data & dword_val & rcvd_dword[CODE_DMATP];
assign set_send_eof = state_send_crc & phy_ready & dword_val & ~rcvd_dword[CODE_SYNCP];
assign set_wait = state_send_eof & phy_ready & dword_val & ~rcvd_dword[CODE_SYNCP];
// receiver's branch // receiver's branch
assign set_rcvr_wait = state_idle & dword_val & rcvd_dword[CODE_XRDYP] assign set_rcvr_wait = state_idle & dword_val & rcvd_dword[CODE_XRDYP]
| state_send_rdy & dword_val & rcvd_dword[CODE_XRDYP]; | state_send_rdy & dword_val & rcvd_dword[CODE_XRDYP];
assign set_rcvr_rdy = state_rcvr_wait & dword_val & rcvd_dword[CODE_XRDYP] & ~data_busy_in;
assign set_rcvr_data = state_rcvr_rdy & dword_val & rcvd_dword[CODE_SOFP] assign set_rcvr_rdy = state_rcvr_wait & dword_val & rcvd_dword[CODE_XRDYP] & ~data_busy_in;
| state_rcvr_rhold & dword_val & ~rcvd_dword[CODE_HOLDP] & ~rcvd_dword[CODE_EOFP] & ~rcvd_dword[CODE_SYNCP] & ~data_busy_in
| state_rcvr_shold & dword_val & ~rcvd_dword[CODE_HOLDP] & ~rcvd_dword[CODE_EOFP] & ~rcvd_dword[CODE_SYNCP]; assign set_rcvr_data = state_rcvr_rdy & dword_val & rcvd_dword[CODE_SOFP]
assign set_rcvr_rhold = state_rcvr_data & dword_val & rcvd_dword[CODE_DATA] & data_busy_in; | state_rcvr_rhold & dword_val_na & ~rcvd_dword[CODE_HOLDP] & ~rcvd_dword[CODE_EOFP] & ~rcvd_dword[CODE_SYNCP] & ~data_busy_in
assign set_rcvr_shold = state_rcvr_data & dword_val & rcvd_dword[CODE_HOLDP] | state_rcvr_shold & dword_val_na & ~rcvd_dword[CODE_HOLDP] & ~rcvd_dword[CODE_EOFP] & ~rcvd_dword[CODE_SYNCP];
| state_rcvr_rhold & dword_val & rcvd_dword[CODE_HOLDP] & ~data_busy_in;
assign set_rcvr_eof = state_rcvr_data & dword_val & rcvd_dword[CODE_EOFP] assign set_rcvr_rhold = state_rcvr_data & dword_val & rcvd_dword[CODE_DATA] & data_busy_in;
| state_rcvr_rhold & dword_val & rcvd_dword[CODE_EOFP]
| state_rcvr_shold & dword_val & rcvd_dword[CODE_EOFP]; assign set_rcvr_shold = state_rcvr_data & dword_val & rcvd_dword[CODE_HOLDP]
| state_rcvr_rhold & dword_val & rcvd_dword[CODE_HOLDP] & ~data_busy_in;
assign set_rcvr_eof = state_rcvr_data & dword_val & rcvd_dword[CODE_EOFP]
| state_rcvr_rhold & dword_val & rcvd_dword[CODE_EOFP]
| state_rcvr_shold & dword_val & rcvd_dword[CODE_EOFP];
assign set_rcvr_goodcrc = state_rcvr_eof & crc_good; assign set_rcvr_goodcrc = state_rcvr_eof & crc_good;
assign set_rcvr_goodend = state_rcvr_goodcrc& incom_ack_good_or_pend; // incom_ack_good; // may arrive at aligns_pair assign set_rcvr_goodend = state_rcvr_goodcrc& incom_ack_good_or_pend; // incom_ack_good; // may arrive at aligns_pair
assign set_rcvr_badend = state_rcvr_data & dword_val & rcvd_dword[CODE_WTRMP]
assign set_rcvr_badend = state_rcvr_data & dword_val & rcvd_dword[CODE_WTRMP]
| state_rcvr_eof & crc_bad | state_rcvr_eof & crc_bad
| state_rcvr_goodcrc& incom_ack_bad_or_pend; // incom_ack_bad; // may arrive at aligns_pair | state_rcvr_goodcrc& incom_ack_bad_or_pend; // incom_ack_bad; // may arrive at aligns_pair
...@@ -405,52 +442,52 @@ assign clr_align = 0; // never - this state is handled in OOB ...@@ -405,52 +442,52 @@ assign clr_align = 0; // never - this state is handled in OOB
assign clr_reset = ~link_reset; assign clr_reset = ~link_reset;
///assign clr_reset = set_align; ///assign clr_reset = set_align;
assign clr_send_rdy = set_nocommerr | set_reset | set_sync_esc | set_send_sof | set_rcvr_wait; assign clr_send_rdy = set_nocommerr | set_reset | set_sync_esc | set_send_sof | set_rcvr_wait;
assign clr_send_sof = set_nocommerr | set_reset | set_sync_esc | set_send_data | got_escape; assign clr_send_sof = set_nocommerr | set_reset | set_sync_esc | set_send_data; // | got_escape;
assign clr_send_data = set_nocommerr | set_reset | set_sync_esc | set_send_rhold | set_send_shold | set_send_crc | got_escape; assign clr_send_data = set_nocommerr | set_reset | set_sync_esc | set_send_rhold | set_send_shold | set_send_crc; // | got_escape;
assign clr_send_rhold = set_nocommerr | set_reset | set_sync_esc | set_send_data | set_send_crc | got_escape; assign clr_send_rhold = set_nocommerr | set_reset | set_sync_esc | set_send_data | set_send_crc; // | got_escape;
assign clr_send_shold = set_nocommerr | set_reset | set_sync_esc | set_send_data | set_send_rhold | set_send_crc | got_escape; assign clr_send_shold = set_nocommerr | set_reset | set_sync_esc | set_send_data | set_send_rhold | set_send_crc; // | got_escape;
assign clr_send_crc = set_nocommerr | set_reset | set_sync_esc | set_send_eof | got_escape; assign clr_send_crc = set_nocommerr | set_reset | set_sync_esc | set_send_eof; // | got_escape;
assign clr_send_eof = set_nocommerr | set_reset | set_sync_esc | set_wait | got_escape; assign clr_send_eof = set_nocommerr | set_reset | set_sync_esc | set_wait; // | got_escape;
assign clr_wait = set_nocommerr | set_reset | set_sync_esc | frame_done | got_escape; assign clr_wait = set_nocommerr | set_reset | set_sync_esc | frame_done; // | got_escape;
/* /*
assign clr_rcvr_wait = set_nocommerr | set_reset | set_sync_esc | set_rcvr_rdy | dword_val & ~rcvd_dword[CODE_XRDYP]; assign clr_rcvr_wait = set_nocommerr | set_reset | set_sync_esc | set_rcvr_rdy | dword_val_na & ~rcvd_dword[CODE_XRDYP];
assign clr_rcvr_rdy = set_nocommerr | set_reset | set_sync_esc | set_rcvr_data | dword_val & ~rcvd_dword[CODE_XRDYP] & ~rcvd_dword[CODE_SOFP]; assign clr_rcvr_rdy = set_nocommerr | set_reset | set_sync_esc | set_rcvr_data | dword_val_na & ~rcvd_dword[CODE_XRDYP] & ~rcvd_dword[CODE_SOFP];
assign clr_rcvr_data = set_nocommerr | set_reset | set_sync_esc | set_rcvr_rhold | set_rcvr_shold | set_rcvr_eof | set_rcvr_badend | got_escape; assign clr_rcvr_data = set_nocommerr | set_reset | set_sync_esc | set_rcvr_rhold | set_rcvr_shold | set_rcvr_eof | set_rcvr_badend | got_escape;
assign clr_rcvr_rhold = set_nocommerr | set_reset | set_sync_esc | set_rcvr_data | set_rcvr_eof | set_rcvr_shold | got_escape; assign clr_rcvr_rhold = set_nocommerr | set_reset | set_sync_esc | set_rcvr_data | set_rcvr_eof | set_rcvr_shold | got_escape;
assign clr_rcvr_shold = set_nocommerr | set_reset | set_sync_esc | set_rcvr_data | set_rcvr_eof | got_escape; assign clr_rcvr_shold = set_nocommerr | set_reset | set_sync_esc | set_rcvr_data | set_rcvr_eof | got_escape;
assign clr_rcvr_eof = set_nocommerr | set_reset | set_sync_esc | set_rcvr_goodcrc | set_rcvr_badend; assign clr_rcvr_eof = set_nocommerr | set_reset | set_sync_esc | set_rcvr_goodcrc | set_rcvr_badend;
assign clr_rcvr_goodcrc = set_nocommerr | set_reset | set_sync_esc | set_rcvr_goodend | set_rcvr_badend | got_escape; assign clr_rcvr_goodcrc = set_nocommerr | set_reset | set_sync_esc | set_rcvr_goodend | set_rcvr_badend | got_escape;
*/ */
assign clr_rcvr_wait = set_nocommerr | set_reset | set_sync_esc /*| set_rcvr_rdy */ | (dword_val & ~rcvd_dword[CODE_XRDYP]); assign clr_rcvr_wait = set_nocommerr | set_reset | set_sync_esc /*| set_rcvr_rdy */ | (dword_val_na & ~rcvd_dword[CODE_XRDYP]);
assign clr_rcvr_rdy = set_nocommerr | set_reset | set_sync_esc /*| set_rcvr_data */ | (dword_val & ~rcvd_dword[CODE_XRDYP] & ~rcvd_dword[CODE_SOFP]); assign clr_rcvr_rdy = set_nocommerr | set_reset | set_sync_esc /*| set_rcvr_data */ | (dword_val_na & ~rcvd_dword[CODE_XRDYP] & ~rcvd_dword[CODE_SOFP]);
assign clr_rcvr_data = set_nocommerr | set_reset | set_sync_esc /*| set_rcvr_rhold | set_rcvr_shold | set_rcvr_eof */ | set_rcvr_badend | got_escape; assign clr_rcvr_data = set_nocommerr | set_reset | set_sync_esc /*| set_rcvr_rhold | set_rcvr_shold | set_rcvr_eof */ | set_rcvr_badend; // | got_escape;
assign clr_rcvr_rhold = set_nocommerr | set_reset | set_sync_esc /*| set_rcvr_data | set_rcvr_eof | set_rcvr_shold */ | got_escape; assign clr_rcvr_rhold = set_nocommerr | set_reset | set_sync_esc /*| set_rcvr_data | set_rcvr_eof | set_rcvr_shold */; // | got_escape;
assign clr_rcvr_shold = set_nocommerr | set_reset | set_sync_esc /*| set_rcvr_data | set_rcvr_eof */ | got_escape; assign clr_rcvr_shold = set_nocommerr | set_reset | set_sync_esc /*| set_rcvr_data | set_rcvr_eof */; // | got_escape;
assign clr_rcvr_eof = set_nocommerr | set_reset | set_sync_esc /*|set_rcvr_goodcrc | set_rcvr_badend*/; assign clr_rcvr_eof = set_nocommerr | set_reset | set_sync_esc /*|set_rcvr_goodcrc | set_rcvr_badend*/;
assign clr_rcvr_goodcrc = set_nocommerr | set_reset | set_sync_esc | /*set_rcvr_goodend | set_rcvr_badend |*/ got_escape; assign clr_rcvr_goodcrc = set_nocommerr | set_reset | set_sync_esc /*set_rcvr_goodend | set_rcvr_badend |*/; // | got_escape;
assign clr_rcvr_goodend = set_nocommerr | set_reset | set_sync_esc | got_escape; assign clr_rcvr_goodend = set_nocommerr | set_reset | set_sync_esc; // | got_escape; // can be 1 cycle only
assign clr_rcvr_badend = set_nocommerr | set_reset | set_sync_esc | got_escape; assign clr_rcvr_badend = set_nocommerr | set_reset | set_sync_esc; // | got_escape;
// the only truely asynchronous transaction between states is -> state_ reset. It shall not be delayed by sending alignes // the only truely asynchronous transaction between states is -> state_ reset. It shall not be delayed by sending alignes
// Luckily, while in that state, the line is off, so we dont need to care about merging alignes and state-bounded primitives // Luckily, while in that state, the line is off, so we dont need to care about merging alignes and state-bounded primitives
// Others transitions are straightforward // Others transitions are straightforward
always @ (posedge clk) always @ (posedge clk)
begin begin
state_sync_esc <= (state_sync_esc | set_sync_esc & ~alignes_pair) & ~(clr_sync_esc & ~alignes_pair) & ~rst; state_sync_esc <= (state_sync_esc | set_sync_esc & ~alignes_pair) & ~(clr_sync_esc & ~alignes_pair) & ~rst;
state_nocommerr <= (state_nocommerr | set_nocommerr & ~alignes_pair) & ~(clr_nocommerr & ~alignes_pair) & ~rst; state_nocommerr <= (state_nocommerr | set_nocommerr & ~alignes_pair) & ~(clr_nocommerr & ~alignes_pair) & ~rst;
state_nocomm <= (state_nocomm | set_nocomm & ~alignes_pair) & ~(clr_nocomm & ~alignes_pair) & ~rst; state_nocomm <= (state_nocomm | set_nocomm & ~alignes_pair) & ~(clr_nocomm & ~alignes_pair) & ~rst;
// state_align is not used, it is handled by OOB // state_align is not used, it is handled by OOB
state_align <= (state_align | set_align & ~alignes_pair) & ~(clr_align & ~alignes_pair) & ~rst; state_align <= (state_align | set_align & ~alignes_pair) & ~(clr_align & ~alignes_pair) & ~rst;
state_reset <= (state_reset | set_reset ) & ~ clr_reset & ~rst; state_reset <= (state_reset | set_reset ) & ~ clr_reset & ~rst;
state_send_rdy <= (state_send_rdy | set_send_rdy & ~alignes_pair) & ~(clr_send_rdy & ~alignes_pair) & ~rst; state_send_rdy <= (state_send_rdy | set_send_rdy & ~alignes_pair) & ~(clr_send_rdy & ~alignes_pair) & ~rst;
state_send_sof <= (state_send_sof | set_send_sof & ~alignes_pair) & ~(clr_send_sof & ~alignes_pair) & ~rst; state_send_sof <= (state_send_sof | set_send_sof & ~alignes_pair) & ~(got_escape | (clr_send_sof & ~alignes_pair)) & ~rst;
state_send_data <= (state_send_data | set_send_data & ~alignes_pair) & ~(clr_send_data & ~alignes_pair) & ~rst; state_send_data <= (state_send_data | set_send_data & ~alignes_pair) & ~(got_escape | (clr_send_data & ~alignes_pair)) & ~rst;
state_send_rhold <= (state_send_rhold | set_send_rhold & ~alignes_pair) & ~(clr_send_rhold & ~alignes_pair) & ~rst; state_send_rhold <= (state_send_rhold | set_send_rhold & ~alignes_pair) & ~(got_escape | (clr_send_rhold & ~alignes_pair)) & ~rst;
state_send_shold <= (state_send_shold | set_send_shold & ~alignes_pair) & ~(clr_send_shold & ~alignes_pair) & ~rst; state_send_shold <= (state_send_shold | set_send_shold & ~alignes_pair) & ~(got_escape | (clr_send_shold & ~alignes_pair)) & ~rst;
state_send_crc <= (state_send_crc | set_send_crc & ~alignes_pair) & ~(clr_send_crc & ~alignes_pair) & ~rst; state_send_crc <= (state_send_crc | set_send_crc & ~alignes_pair) & ~(got_escape | (clr_send_crc & ~alignes_pair)) & ~rst;
state_send_eof <= (state_send_eof | set_send_eof & ~alignes_pair) & ~(clr_send_eof & ~alignes_pair) & ~rst; state_send_eof <= (state_send_eof | set_send_eof & ~alignes_pair) & ~(got_escape | (clr_send_eof & ~alignes_pair)) & ~rst;
state_wait <= (state_wait | set_wait & ~alignes_pair) & ~(clr_wait & ~alignes_pair) & ~rst; state_wait <= (state_wait | set_wait & ~alignes_pair) & ~(got_escape | (clr_wait & ~alignes_pair)) & ~rst;
// Andrey: most receiver states can not wait for transmitting aligns_pair. What host sends in this states matters when confirmed by the device // Andrey: most receiver states can not wait for transmitting aligns_pair. What host sends in this states matters when confirmed by the device
// So it seems OK if alignes_pair will just overwrite whatever host was going to send in these state. // So it seems OK if alignes_pair will just overwrite whatever host was going to send in these state.
// Care should be taken only for transitions between these states and others (transmit) that need to wait for alignes_pair to finish // Care should be taken only for transitions between these states and others (transmit) that need to wait for alignes_pair to finish
...@@ -463,24 +500,28 @@ begin ...@@ -463,24 +500,28 @@ begin
state_rcvr_data <= (state_rcvr_data | set_rcvr_data ) & ~(set_rcvr_shold | state_rcvr_data <= (state_rcvr_data | set_rcvr_data ) & ~(set_rcvr_shold |
set_rcvr_shold | set_rcvr_shold |
set_rcvr_eof | (clr_rcvr_data & ~alignes_pair)) & ~rst; set_rcvr_eof |
got_escape | (clr_rcvr_data & ~alignes_pair)) & ~rst;
state_rcvr_rhold <= (state_rcvr_rhold | set_rcvr_rhold ) & ~(set_rcvr_data | state_rcvr_rhold <= (state_rcvr_rhold | set_rcvr_rhold ) & ~(set_rcvr_data |
set_rcvr_shold | set_rcvr_shold |
set_rcvr_eof | (clr_rcvr_rhold & ~alignes_pair)) & ~rst; set_rcvr_eof |
got_escape | (clr_rcvr_rhold & ~alignes_pair)) & ~rst;
state_rcvr_shold <= (state_rcvr_shold | set_rcvr_shold ) & ~(set_rcvr_data | state_rcvr_shold <= (state_rcvr_shold | set_rcvr_shold ) & ~(set_rcvr_data |
set_rcvr_eof | (clr_rcvr_shold & ~alignes_pair)) & ~rst; set_rcvr_eof |
got_escape | (clr_rcvr_shold & ~alignes_pair)) & ~rst;
state_rcvr_eof <= (state_rcvr_eof | set_rcvr_eof ) & ~(set_rcvr_goodcrc | state_rcvr_eof <= (state_rcvr_eof | set_rcvr_eof ) & ~(set_rcvr_goodcrc |
state_rcvr_badend |(clr_rcvr_eof & ~alignes_pair)) & ~rst; state_rcvr_badend |(clr_rcvr_eof & ~alignes_pair)) & ~rst;
state_rcvr_goodcrc <= (state_rcvr_goodcrc | set_rcvr_goodcrc ) & ~(set_rcvr_goodend | state_rcvr_goodcrc <= (state_rcvr_goodcrc | set_rcvr_goodcrc ) & ~(set_rcvr_goodend |
set_rcvr_badend | (clr_rcvr_goodcrc & ~alignes_pair)) & ~rst; set_rcvr_badend |
got_escape | (clr_rcvr_goodcrc & ~alignes_pair)) & ~rst;
state_rcvr_goodend <= (state_rcvr_goodend | set_rcvr_goodend ) & ~(clr_rcvr_goodend & ~alignes_pair) & ~rst; state_rcvr_goodend <= (state_rcvr_goodend | set_rcvr_goodend ) & ~(got_escape | (clr_rcvr_goodend & ~alignes_pair)) & ~rst;
state_rcvr_badend <= (state_rcvr_badend | set_rcvr_badend ) & ~(clr_rcvr_badend & ~alignes_pair) & ~rst; state_rcvr_badend <= (state_rcvr_badend | set_rcvr_badend ) & ~(got_escape | (clr_rcvr_badend & ~alignes_pair)) & ~rst;
/* /*
state_rcvr_wait <= (state_rcvr_wait | set_rcvr_wait & ~alignes_pair) & ~(clr_rcvr_wait & ~alignes_pair) & ~rst; state_rcvr_wait <= (state_rcvr_wait | set_rcvr_wait & ~alignes_pair) & ~(clr_rcvr_wait & ~alignes_pair) & ~rst;
...@@ -644,7 +685,7 @@ always @ (posedge clk) ...@@ -644,7 +685,7 @@ always @ (posedge clk)
// incoming data is data // incoming data is data
wire inc_is_data; wire inc_is_data;
assign inc_is_data = dword_val & rcvd_dword[CODE_DATA] & (state_rcvr_data | state_rcvr_rhold); assign inc_is_data = dword_val & rcvd_dword[CODE_DATA] & (state_rcvr_data | state_rcvr_rhold);
//wire inc_is_crc = dword_val & rcvd_dword[CODE_CRC] & (state_rcvr_data | state_rcvr_rhold); //wire inc_is_crc = dword_val_na & rcvd_dword[CODE_CRC] & (state_rcvr_data | state_rcvr_rhold);
/* /*
* Scrambler can work both as a scrambler and a descramler, because data stream could be * Scrambler can work both as a scrambler and a descramler, because data stream could be
* one direction at a time * one direction at a time
...@@ -681,6 +722,7 @@ reg data_val_out_r; ...@@ -681,6 +722,7 @@ reg data_val_out_r;
reg [31:0] data_out_rr; reg [31:0] data_out_rr;
reg data_val_out_rr; reg data_val_out_rr;
// if current == EOF => _r == CRC and _rr == last data piece // if current == EOF => _r == CRC and _rr == last data piece
/*
always @ (posedge clk) always @ (posedge clk)
begin begin
data_out_r <= scrambler_out; data_out_r <= scrambler_out;
...@@ -688,6 +730,23 @@ begin ...@@ -688,6 +730,23 @@ begin
data_val_out_r <= inc_is_data; data_val_out_r <= inc_is_data;
data_val_out_rr <= data_val_out_r & ~set_rcvr_eof; // means that @ previous clock cycle the delivered data was crc data_val_out_rr <= data_val_out_r & ~set_rcvr_eof; // means that @ previous clock cycle the delivered data was crc
end end
*/
reg data_held; // some data is held in data_out_r over primitives - to be restored if not EOF
// no need to check for set_rcvr_eof - last dword will be always lost
always @ (posedge clk) begin
if (dword_val & rcvd_dword[CODE_SOFP]) data_held <= 0;
else if (inc_is_data) data_held <= 1;
if (inc_is_data) data_out_r <= scrambler_out;
if (data_val_out_r) data_out_rr <= data_out_r;
data_val_out_r <= inc_is_data;
data_val_out_rr <= inc_is_data && data_held;
end
assign data_out = data_out_rr; assign data_out = data_out_rr;
assign data_mask_out = 2'b11;//{DATA_BYTE_WIDTH/2{1'b1}}; assign data_mask_out = 2'b11;//{DATA_BYTE_WIDTH/2{1'b1}};
assign data_val_out = data_val_out_rr; assign data_val_out = data_val_out_rr;
...@@ -735,18 +794,20 @@ assign incom_start_w = set_rcvr_wait; // & ~alignes_pair; ...@@ -735,18 +794,20 @@ assign incom_start_w = set_rcvr_wait; // & ~alignes_pair;
// ... and processed // ... and processed
assign incom_done_w = set_rcvr_goodcrc; // & ~alignes_pair; assign incom_done_w = set_rcvr_goodcrc; // & ~alignes_pair;
// or the FIS had errors // or the FIS had errors
//assign incom_invalidate = state_rcvr_eof & crc_bad & ~alignes_pair | state_rcvr_data & dword_val & rcvd_dword[CODE_WTRMP] //assign incom_invalidate = state_rcvr_eof & crc_bad & ~alignes_pair | state_rcvr_data & dword_val_na & rcvd_dword[CODE_WTRMP]
// | (state_rcvr_wait | state_rcvr_rdy | state_rcvr_data | state_rcvr_rhold | state_rcvr_shold | state_rcvr_eof | state_rcvr_goodcrc) & got_escape; // | (state_rcvr_wait | state_rcvr_rdy | state_rcvr_data | state_rcvr_rhold | state_rcvr_shold | state_rcvr_eof | state_rcvr_goodcrc) & got_escape;
// Separating different types of errors, sync_escape from other problems. TODO: route individual errors to set SERR bits // Separating different types of errors, sync_escape from other problems. TODO: route individual errors to set SERR bits
//assign incom_invalidate = (state_rcvr_eof & crc_bad & ~alignes_pair) | // CRC mismatch //assign incom_invalidate = (state_rcvr_eof & crc_bad & ~alignes_pair) | // CRC mismatch
// (state_rcvr_data & dword_val & rcvd_dword[CODE_WTRMP]); // (state_rcvr_data & dword_val_na & rcvd_dword[CODE_WTRMP]);
assign incom_invalidate_w = (state_rcvr_eof & crc_bad) | // CRC mismatch assign incom_invalidate_w = (state_rcvr_eof & crc_bad) | // CRC mismatch
(state_rcvr_data & dword_val & rcvd_dword[CODE_WTRMP]); // missed EOF? (state_rcvr_data & dword_val & rcvd_dword[CODE_WTRMP]); // missed EOF?
assign incom_sync_escape = (state_rcvr_wait | state_rcvr_rdy | state_rcvr_data | state_rcvr_rhold | assign incom_sync_escape = (state_rcvr_wait | state_rcvr_rdy | state_rcvr_data | state_rcvr_rhold |
state_rcvr_shold | state_rcvr_eof | state_rcvr_goodcrc) & got_escape; state_rcvr_shold | state_rcvr_eof | state_rcvr_goodcrc) & got_escape;
// shows that incoming primitive or data is ready to be processed // TODO somehow move alignes_pair into dword_val // shows that incoming primitive or data is ready to be processed // TODO somehow move alignes_pair into dword_val_na
assign dword_val = |rcvd_dword & phy_ready & ~rcvd_dword[CODE_ALIGNP];
assign dword_val = |rcvd_dword & phy_ready; // any valid primitive/data
assign dword_val_na = |rcvd_dword & phy_ready & ~rcvd_dword[CODE_ALIGNP]; // any valid primitive/data but ALIGNp
// determine imcoming primitive type // determine imcoming primitive type
/* /*
// determine imcoming primitive type // determine imcoming primitive type
...@@ -1013,16 +1074,98 @@ reg state_rcvr_badend; // BadEnd ...@@ -1013,16 +1074,98 @@ reg state_rcvr_badend; // BadEnd
///assign debug_out[31:20] = debug_num_other[11:0]; ///assign debug_out[31:20] = debug_num_other[11:0];
///assign debug_out = debug_unknown_dword; // first unknown dword ///assign debug_out = debug_unknown_dword; // first unknown dword
reg [1:0] debug_data_last_in_r;
reg [1:0] debug_alignes_pair_r;
reg [1:0] debug_state_send_data_r;
reg [1:0] debug_dword_val_na;
reg [1:0] debug_CODE_SYNCP;
reg [1:0] debug_set_send_crc;
reg [1:0] debug_data_val_in;
reg [1:0] debug_was_OK_ERR;
reg debug_was_wait;
reg debug_was_idle;
reg debug_was_ok_err;
reg debug_was_state_wait;
reg debug_was_frame_done;
reg debug_was_got_escape;
// frame_done | got_escape
always @(posedge clk) begin
if (data_strobe_out) begin
debug_data_last_in_r <= {debug_data_last_in_r[0],data_last_in};
debug_alignes_pair_r <= {debug_alignes_pair_r[0],alignes_pair};
debug_state_send_data_r <= {debug_state_send_data_r[0],state_send_data};
debug_dword_val_na <= {debug_dword_val_na[0],dword_val_na};
debug_CODE_SYNCP <= {debug_CODE_SYNCP[0],rcvd_dword[CODE_SYNCP]};
debug_set_send_crc <= {debug_set_send_crc[0],set_send_crc};
debug_data_val_in <= {debug_data_val_in[0],data_val_in};
end
debug_was_ok_err <= rcvd_dword[CODE_ERRP] | rcvd_dword[CODE_OKP];
if (frame_req) debug_was_OK_ERR <= 0;
else debug_was_OK_ERR <= debug_was_OK_ERR | {rcvd_dword[CODE_ERRP], rcvd_dword[CODE_OKP]};
if (frame_req) debug_was_state_wait <= 0;
else debug_was_state_wait <= debug_was_state_wait | state_wait;
if (state_wait && clr_wait && !alignes_pair) debug_was_frame_done <= frame_done;
if (state_wait && clr_wait && !alignes_pair) debug_was_got_escape <= got_escape;
if ((rcvd_dword[CODE_ERRP] || rcvd_dword[CODE_OKP]) && !debug_was_ok_err) begin
debug_was_wait <= state_wait;
debug_was_idle <= state_idle;
end
end
assign debug_out[ 4: 0] = debug_states_encoded; assign debug_out[ 4: 0] = debug_states_encoded;
assign debug_out[7: 5] = {
rcvd_dword[CODE_SYNCP],
rcvd_dword[CODE_OKP],
alignes_pair};
assign debug_out[31] = rcvd_dword[CODE_ALIGNP];
assign debug_out[30] = set_send_sof;
assign debug_out[29] = clr_send_rdy;
assign debug_out[28] = state_send_rdy;
assign debug_out[27] = state_send_sof;
assign debug_out[26] = state_idle;
assign debug_out[25] = state_send_data;
assign debug_out[24] = (state_send_sof | set_send_sof & ~alignes_pair);
assign debug_out[23] = (clr_send_sof & ~alignes_pair);
assign debug_out[22] = set_rcvr_wait; // start logging input
//assign debug_out[15: 5] = debug_to_first_err[14:4]; //assign debug_out[15: 5] = debug_to_first_err[14:4];
assign debug_out[31:16] = debug_rcvd_dword; assign debug_out[21:16] = debug_rcvd_dword[5:0];
assign debug_out[7: 5] = 0;
assign debug_out[15: 8] = {2'b0, state_send_data, data_txing, assign debug_out[15: 8] = {
data_val_in, data_last_in, dword_val, ~rcvd_dword[CODE_SYNCP]}; debug_was_wait, // state was wait when last CODE_ERRP/CODE_OKP was received
debug_was_idle, // state was idle when last CODE_ERRP/CODE_OKP was received
debug_was_OK_ERR[1:0],
debug_was_state_wait,
debug_was_frame_done,
debug_was_got_escape,
/* debug_data_last_in_r[1],
debug_alignes_pair_r[1],
debug_state_send_data_r[1],
debug_state_send_data_r[0],
debug_data_val_in[1],
debug_data_val_in[0],
debug_set_send_crc[1],
*/
// debug_dword_val_na[1],
~debug_CODE_SYNCP[1]};
/* /*
assign set_send_crc = state_send_data & data_txing & data_val_in & data_last_in & dword_val & ~rcvd_dword[CODE_SYNCP] state_send_sof <= (state_send_sof | set_send_sof & ~alignes_pair) & ~(clr_send_sof & ~alignes_pair) & ~rst;
| state_send_data & dword_val & rcvd_dword[CODE_DMATP];
_send_crc = state_send_data & data_txing & data_val_in & data_last_in & dword_val_na & ~rcvd_dword[CODE_SYNCP]
| state_send_data & dword_val_na & rcvd_dword[CODE_DMATP];
*/ */
......
includes/ahxi_fsm_code.vh
View file @ e06e9e1a
, .INIT_00 (256'h00100000000E0000000C00000033000000200000000A0000000A0000000A0000) , .INIT_00 (256'h00100000000E0000000C00000033000000200000000A0000000A0000000A0000)
, .INIT_01 (256'h001944521C399446543044170000001900880019003002020204008400220006) , .INIT_01 (256'h001944521C399446543044170000001900880019003002020204008400220006)
, .INIT_02 (256'h001900050019C82E000C04020110002924FB2502024000190003004204040000) , .INIT_02 (256'h001900050019C82E000C04020110002924FB2503024000190003004204040000)
, .INIT_03 (256'h845284BE44374C682C4214190012003900880018000A02080022001901020090) , .INIT_03 (256'h845284BE44374C682C4214190012003900880018000A02080022001901020090)
, .INIT_04 (256'h00190110003901100019144601020030020202040039B07D707A041000398C6B) , .INIT_04 (256'h00190110003901100019144601020030020202040039B07D707A041000398C6B)
, .INIT_05 (256'h64540C2504580000004E24FB250200C0004C24FB250200C0005C000000390000) , .INIT_05 (256'h64540C2504580000004E24FB250300C0004C24FB250300C0005C000000390000)
, .INIT_06 (256'hD10250F8903900A00104006B0202005000E2A89368F018E918CB98A758D73882) , .INIT_06 (256'hD10550F8903900A00104006B0202005000E2A89368F018E918CB98A758D73882)
, .INIT_07 (256'h0060003900000039B07D00000050004400220039B07D707A307730F001080071) , .INIT_07 (256'h0060003900000039B07D00000050004400220039B07D707A307730F001080071)
, .INIT_08 (256'h00050091C88F002200240091288B28FE000C0110008624FB25020240009CD0FB) , .INIT_08 (256'h00050091C88F002200240091288B28FF000C0110008624FB25030240009CD0FD)
, .INIT_09 (256'h48A528A128FE00140039487F0CAD28FE0110009724FB25020140005004020091) , .INIT_09 (256'h48A528A128FF00140039487F0CAD28FF0110009724FB25030140005004020091)
, .INIT_0A (256'h8839089C040800AD011000AB24FB250200C000500081005048A5002200240039) , .INIT_0A (256'h8839089C040800AD011000AB24FB250300C000500081005048A5002200240039)
, .INIT_0B (256'h00C004080039889C040800090039889C50BA0024004800B5D0FB50F8012000B1) , .INIT_0B (256'h00C004080039889C040800090039889C50BA0024004800B5D0FD50F8012000B1)
, .INIT_0C (256'h011000CF24FB250204200039889C50BA00240028011000C5C50224FB24FB0220) , .INIT_0C (256'h011000CF24FB250304200039889C50BA00240028011000C5C50324FB24FB0220)
, .INIT_0D (256'h0050C8E028FE000C011000DB24FB25020440003934D2000000D4001100D4C8D2) , .INIT_0D (256'h0050C8E028FF000C011000DB24FB25030440003934D2000000D4001100D4C8D2)
, .INIT_0E (256'h00F60082011000ED24FB250200C000390401011000E624FB2502018000500101) , .INIT_0E (256'h00F60082011000ED24FB250300C000390401011000E624FB2503018000500101)
, .INIT_0F (256'h0100020101000021021001000021004400F6000000F6011000F424FB250200C0) , .INIT_0F (256'h02010101002100FD021001010021004400F6000000F6011000F424FB250300C0)
, .INIT_10 (256'h0000000000000000000000000000000000000000000000390041000001000000) , .INIT_10 (256'h0000000000000000000000000000000000000039004101050210010100000101)
, .INITP_00 (256'hC8220098170902401E272722222800309418810820809C802018880022222222) , .INITP_00 (256'hC8220098170902401E272722222800309418810820809C802018880022222222)
, .INITP_01 (256'h22082227209C82720A09C22089C680272181A01CB889C8605A2A89C882068270) , .INITP_01 (256'h88882227209C82720A09C22089C680272181A01CB889C8605A2A89C882068270)
, .INITP_02 (256'h0000000000000000000000000000000000000000000000000000000000000082) , .INITP_02 (256'h0000000000000000000000000000000000000000000000000000000000000888)
py393sata/x393sata.py
View file @ e06e9e1a
...@@ -628,6 +628,12 @@ class x393sata(object): ...@@ -628,6 +628,12 @@ class x393sata(object):
print("Datascope (debug) data:") print("Datascope (debug) data:")
print("_=mem.mem_dump (0x%x, 0x20,4)"%(DATASCOPE_ADDR)) print("_=mem.mem_dump (0x%x, 0x20,4)"%(DATASCOPE_ADDR))
self.x393_mem.mem_dump (DATASCOPE_ADDR, 0xa0,4) self.x393_mem.mem_dump (DATASCOPE_ADDR, 0xa0,4)
dd =0
for a in range(0x80001000,0x80001014,4):
dd |= self.x393_mem.read_mem(a)
if dd == 0:
print ("*** Probably got cache/write buffer problem, continuing ***")
break
raise Exception("Failed to get interrupt") raise Exception("Failed to get interrupt")
break break
...@@ -638,13 +644,13 @@ class x393sata(object): ...@@ -638,13 +644,13 @@ class x393sata(object):
print("_=mem.mem_dump (0x%x, 0x4,4)"%(MAXI1_ADDR + DBG_OFFS)) print("_=mem.mem_dump (0x%x, 0x4,4)"%(MAXI1_ADDR + DBG_OFFS))
self.x393_mem.mem_dump (MAXI1_ADDR + DBG_OFFS, 0x4,4) self.x393_mem.mem_dump (MAXI1_ADDR + DBG_OFFS, 0x4,4)
print("Datascope (debug) data:") print("Datascope (debug) data:")
print("_=mem.mem_dump (0x%x, 0x20,4)"%(DATASCOPE_ADDR)) print("_=mem.mem_dump (0x%x, 0x100,4)"%(DATASCOPE_ADDR))
self.x393_mem.mem_dump (DATASCOPE_ADDR, 0xa0,4) self.x393_mem.mem_dump (DATASCOPE_ADDR, 0x200,4)
raise Exception("Failed to get interrupt") raise Exception("Failed to get interrupt")
print("Datascope (debug) data:") print("Datascope (debug) data:")
print("_=mem.mem_dump (0x%x, 0x20,4)"%(DATASCOPE_ADDR)) print("_=mem.mem_dump (0x%x, 0x200,4)"%(DATASCOPE_ADDR))
self.x393_mem.mem_dump (DATASCOPE_ADDR, 0xa0,4) self.x393_mem.mem_dump (DATASCOPE_ADDR, 0x200,4)
print("Memory read data:") print("Memory read data:")
print("_=mem.mem_dump (0x%x, 0x%x, 1)"%(DATAIN_ADDRESS, count * 0x200)) print("_=mem.mem_dump (0x%x, 0x%x, 1)"%(DATAIN_ADDRESS, count * 0x200))
self.x393_mem.mem_dump (DATAIN_ADDRESS, count * 0x200, 1) self.x393_mem.mem_dump (DATAIN_ADDRESS, count * 0x200, 1)
...@@ -886,7 +892,7 @@ class x393sata(object): ...@@ -886,7 +892,7 @@ class x393sata(object):
(" R_IPp ",0x5555b57c), (" R_IPp ",0x5555b57c),
(" R_OKp ",0x3535b57c), (" R_OKp ",0x3535b57c),
(" R_RDYp ",0x4a4a957c), (" R_RDYp ",0x4a4a957c),
(" SOFp ",0x3131b57c), (" SOFp ",0x3737b57c),
(" SYNCp ",0xb5b5957c), (" SYNCp ",0xb5b5957c),
(" WTRMp ",0x5858b57c), (" WTRMp ",0x5858b57c),
(" X_RDYp ",0x5757b57c)) (" X_RDYp ",0x5757b57c))
...@@ -1053,6 +1059,17 @@ sata.reg_status() ...@@ -1053,6 +1059,17 @@ sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4) _=mem.mem_dump (0x80000ff0, 4,4)
sata.reg_status(),sata.reset_ie(),sata.err_count() sata.reg_status(),sata.reset_ie(),sata.err_count()
for block in range (1,1024):
print("\n======== Reading block %d ==============="%block)
sata.arm_logger()
sata.dd_read_dma(block, 1)
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reg_status(),sata.reset_ie(),sata.err_count()
sata.arm_logger() sata.arm_logger()
sata.setup_pio_read_identify_command() sata.setup_pio_read_identify_command()
......
tb_ahci_01.sav
View file @ e06e9e1a
[*] [*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Sun Feb 14 23:58:57 2016 [*] Wed Feb 17 00:41:51 2016
[*] [*]
[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160214134023147.fst" [dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160216095816459.fst"
[dumpfile_mtime] "Sun Feb 14 20:41:46 2016" [dumpfile_mtime] "Tue Feb 16 16:59:52 2016"
[dumpfile_size] 10591039 [dumpfile_size] 10761673
[savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav" [savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav"
[timestart] 14876900 [timestart] 33334000
[size] 1823 1180 [size] 1823 1180
[pos] 2026 0 [pos] 2026 0
*-16.443789 15151294 29549854 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-17.446142 33882754 29549854 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb_ahci. [treeopen] tb_ahci.
[treeopen] tb_ahci.axi_read_addr. [treeopen] tb_ahci.axi_read_addr.
[treeopen] tb_ahci.dev.linkMonitorFIS. [treeopen] tb_ahci.dev.linkMonitorFIS.
...@@ -60,7 +60,7 @@ ...@@ -60,7 +60,7 @@
[treeopen] tb_ahci.simul_axi_hp_wr_i.wdata_i. [treeopen] tb_ahci.simul_axi_hp_wr_i.wdata_i.
[treeopen] tb_ahci.simul_axi_read_i. [treeopen] tb_ahci.simul_axi_read_i.
[sst_width] 296 [sst_width] 296
[signals_width] 252 [signals_width] 254
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 573 [sst_vpaned_height] 573
@820 @820
...@@ -1040,6 +1040,9 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_d2h_control_i.mem_regen ...@@ -1040,6 +1040,9 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_d2h_control_i.mem_regen
-ahci_sata_layers -ahci_sata_layers
@c00200 @c00200
-ahci_top -ahci_top
@28
tb_ahci.dut.sata_top.ahci_top_i.xmit_ok
tb_ahci.dut.sata_top.ahci_top_i.datascope_we
@22 @22
tb_ahci.dut.sata_top.ahci_top_i.regs_waddr[9:0] tb_ahci.dut.sata_top.ahci_top_i.regs_waddr[9:0]
tb_ahci.dut.sata_top.ahci_top_i.regs_raddr[9:0] tb_ahci.dut.sata_top.ahci_top_i.regs_raddr[9:0]
...@@ -1866,7 +1869,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_ackn ...@@ -1866,7 +1869,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_ackn
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_from_st tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_from_st
@1401200 @1401200
-ahci_fsm -ahci_fsm
@800200 @c00200
-ahci_fis_receive -ahci_fis_receive
@22 @22
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.hba_data_in[31:0] tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.hba_data_in[31:0]
...@@ -1964,11 +1967,13 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.fis_dcount[3:0] ...@@ -1964,11 +1967,13 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.fis_dcount[3:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.fis_dcount[3:0] (3)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.fis_dcount[3:0]
@1001200 @1001200
-group_end -group_end
@1000200 @1401200
-ahci_fis_receive -ahci_fis_receive
@c00200 @c00200
-ahci_fis_transmit -ahci_fis_transmit
@28 @28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.xmit_ok
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.xmit_err
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.todev_full_r tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.todev_full_r
@22 @22
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.todev_type[1:0] tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.todev_type[1:0]
...@@ -3428,14 +3433,78 @@ tb_ahci.simul_axi_hp_rd_i.rdata_i.out_full ...@@ -3428,14 +3433,78 @@ tb_ahci.simul_axi_hp_rd_i.rdata_i.out_full
- -
@1401200 @1401200
-ahci_dma -ahci_dma
@c00200
-datascope0
@22
tb_ahci.dut.sata_top.ahci_top_i.datascope_id[3:0]
tb_ahci.dut.sata_top.ahci_top_i.datascope_incoming_cntr[7:0]
@800028
tb_ahci.dut.sata_top.ahci_top_i.datascope_incoming_run[2:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.datascope_incoming_run[2:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.datascope_incoming_run[2:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.datascope_incoming_run[2:0]
@c00022
tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(10)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(11)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(12)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(13)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(14)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(15)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(16)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(17)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(18)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(19)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(20)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(21)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(22)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(23)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(24)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(25)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(26)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(27)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(28)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(29)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(30)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(31)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
@1401200
-group_end
@1001200
-group_end
@200
-
@1401200
-datascope0
@800200 @800200
-link -link
@28 @28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.scrambler.rst
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.scrambler.val_in
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.scrambler_out[31:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_out_r[31:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_out_rr[31:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.inc_is_data
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.set_rcvr_eof
@29
tb_ahci.dut.sata_top.ahci_sata_layers_i.ll_d2h_valid tb_ahci.dut.sata_top.ahci_sata_layers_i.ll_d2h_valid
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.fis_over_r tb_ahci.dut.sata_top.ahci_sata_layers_i.fis_over_r
tb_ahci.dut.sata_top.ahci_sata_layers_i.d2h_fifo_wr tb_ahci.dut.sata_top.ahci_sata_layers_i.d2h_fifo_wr
tb_ahci.dut.sata_top.ahci_sata_layers_i.d2h_type_in[1:0] tb_ahci.dut.sata_top.ahci_sata_layers_i.d2h_type_in[1:0]
@29
tb_ahci.dut.sata_top.ahci_sata_layers_i.ll_incom_done tb_ahci.dut.sata_top.ahci_sata_layers_i.ll_incom_done
@200 @200
- -
...@@ -3571,9 +3640,75 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.is_cont_p_w ...@@ -3571,9 +3640,75 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.is_cont_p_w
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.is_non_cont_non_align_p_w tb_ahci.dut.sata_top.ahci_sata_layers_i.link.is_non_cont_non_align_p_w
@22 @22
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.last_not_cont_di[31:0] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.last_not_cont_di[31:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.clr_rcvr_goodend
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_req
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_ack
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_busy
@c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(2)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(3)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(4)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(5)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(6)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(7)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(8)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(9)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(10)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(11)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(12)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(13)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(14)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(15)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_top_i.datascope_we
@c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(2)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(3)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(4)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(5)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(6)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(7)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(8)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(9)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(10)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(11)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(12)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(13)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(14)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(15)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(16)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(17)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(18)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(19)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(20)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(21)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(22)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(23)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(24)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(25)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(26)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(27)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(28)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(29)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(30)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
(31)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
@1401200
-group_end
@800200 @800200
-states -states
@28 @28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_pair
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_idle tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_idle
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_sync_esc tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_sync_esc
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_nocommerr tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_nocommerr
...@@ -3761,7 +3896,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_strobe_out ...@@ -3761,7 +3896,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_strobe_out
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_txing tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_txing
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_last_in tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_last_in
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_last_out tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_last_out
@800022 @c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
@28 @28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0] (0)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
...@@ -3780,11 +3915,10 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0] ...@@ -3780,11 +3915,10 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(13)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0] (13)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(14)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0] (14)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(15)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0] (15)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
@1001200 @1401200
-group_end -group_end
@28 @28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_pair_0 tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_pair_0
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_pair_1
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_pair tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_pair
@c08022 @c08022
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
...@@ -3856,8 +3990,9 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_ack ...@@ -3856,8 +3990,9 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_ack
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_busy tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_busy
@1000200 @1000200
-link -link
@800200 @c00200
-phy -phy
@800200
-gtx_8x10enc -gtx_8x10enc
@28 @28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_8x10enc.inisk[1:0] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_8x10enc.inisk[1:0]
...@@ -4023,9 +4158,8 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_g ...@@ -4023,9 +4158,8 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_g
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.dataiface.wordcounter[31:0] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.dataiface.wordcounter[31:0]
@1401200 @1401200
-GTXE2_GPL -GTXE2_GPL
@1000200
-phy -phy
@800200 @c00200
-comma -comma
@22 @22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.indata[19:0] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.indata[19:0]
...@@ -4035,7 +4169,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.comma ...@@ -4035,7 +4169,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.comma
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.comma_detected tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.comma_detected
@200 @200
- -
@1000200 @1401200
-comma -comma
@c00200 @c00200
-elastic_slow -elastic_slow
...@@ -4368,7 +4502,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txreset ...@@ -4368,7 +4502,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txreset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxreset tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxreset
@1401200 @1401200
-sipo_meas -sipo_meas
@800200 @c00200
-gtx -gtx
-elastic -elastic
@22 @22
...@@ -4378,7 +4512,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.elastic1632_i.data_out[31:0 ...@@ -4378,7 +4512,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.elastic1632_i.data_out[31:0
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.elastic1632_i.dbg_diff[4:0] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.elastic1632_i.dbg_diff[4:0]
@200 @200
- -
@1000200 @1401200
-elastic -elastic
@28 @28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.drp_we tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.drp_we
...@@ -4492,7 +4626,6 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0] ...@@ -4492,7 +4626,6 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
- -
@1401200 @1401200
-gtx8x10enc -gtx8x10enc
@1000200
-gtx -gtx
@c00200 @c00200
-device -device
......
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