Commit ce85dcb3 authored by Andrey Filippov's avatar Andrey Filippov

Continue on AHCI implementation - processing received FIS

parent aa0b3a4e
...@@ -41,7 +41,7 @@ so *.editor_defines* is now just for the editor (which branches to parse). No re ...@@ -41,7 +41,7 @@ so *.editor_defines* is now just for the editor (which branches to parse). No re
# Current step in try2 branch: # Current step in try2 branch:
Not yet tested in hardware, started AHCI implementation (currently coded registers and DMA engine, that processes command table/PRD list, Not yet tested in hardware, started AHCI implementation (currently coded registers and DMA engine, that processes command table/PRD list,
Transfers data between clock domains, re-aligns between WORD size granularity, HAB 32-bit data and 64-bit AXI accesses. Transfers data between clock domains, re-aligns between WORD size granularity, HBA 32-bit data and 64-bit AXI accesses.
# Current step in main branch: # Current step in main branch:
Testing basic functionallity of a host. Testing basic functionallity of a host.
Trying out pio access. Trying out pio access.
......
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...@@ -514,7 +514,7 @@ always @ (posedge clk) ...@@ -514,7 +514,7 @@ always @ (posedge clk)
if (ll_data_val_in) if (ll_data_val_in)
begin begin
if (dword_cnt == 14'd2049) if (dword_cnt == 14'd2049)
// if too much data for a data FIS TODO handle this excpetion properly // if too much data for a data FIS TODO handle this exception properly
state <= STATE_IDLE; state <= STATE_IDLE;
else else
// continuing receiving data // continuing receiving data
......
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
, .INIT_10 (256'h0000000000000000555555555555000000000000000000005555555555500000) , .INIT_10 (256'h0000000000000000555555555555000000000000000000005555555555500000)
, .INIT_11 (256'h000000000000000055054004000001C15551400000000455AAA28000000008AA) , .INIT_11 (256'h000000000000000055054004000001C15551400000000455AAA28000000008AA)
, .INIT_12 (256'h0000000000550000000000000000000000000000000000000000000000000000) , .INIT_12 (256'h0000000000550000000000000000000000000000000000000000000000000000)
, .INIT_13 (256'h00000000AAAAAAAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF002AAAAA00AA0008) , .INIT_13 (256'h00000000AAAAAAAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF002AAAAA00AA000A)
, .INIT_14 (256'h000000000000000000000000000000000001555555555550000000000055000D) , .INIT_14 (256'h000000000000000000000000000000000001555555555550000000000055000D)
, .INIT_17 (256'h5555555555555555555555555555555555555555555555555555555555555555) , .INIT_17 (256'h5555555555555555555555555555555555555555555555555555555555555555)
, .INIT_18 (256'h00000000000055550000000000000000AA820000001000140000000000000000) , .INIT_18 (256'h00000000000055550000000000000000AA820000001000140000000000000000)
......
/******************************************************************************* /*******************************************************************************
* Module: ahci_dma * Module: ahci_dma
* Date:2016-01-01 * Date:2016-01-01
* Author: andrey * Author: Andrey Filippov
* Description: DMA R/W over 64-AXI channel for AHCI implementation * Description: DMA R/W over 64-AXI channel for AHCI implementation
* *
* Copyright (c) 2016 Elphel, Inc . * Copyright (c) 2016 Elphel, Inc .
......
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