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Elphel
x393_sata
Commits
ce85dcb3
Commit
ce85dcb3
authored
Jan 07, 2016
by
Andrey Filippov
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Continue on AHCI implementation - processing received FIS
parent
aa0b3a4e
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6 changed files
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346 additions
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45 deletions
+346
-45
README.md
README.md
+1
-1
create_ahci_registers.py
helpers/create_ahci_registers.py
+76
-41
transport.v
host/transport.v
+1
-1
ahci_types.vh
includes/ahci_types.vh
+1
-1
ahci_dma.v
utils/ahci_dma.v
+1
-1
ahci_fis_receive.v
utils/ahci_fis_receive.v
+266
-0
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README.md
View file @
ce85dcb3
...
@@ -41,7 +41,7 @@ so *.editor_defines* is now just for the editor (which branches to parse). No re
...
@@ -41,7 +41,7 @@ so *.editor_defines* is now just for the editor (which branches to parse). No re
# Current step in try2 branch:
# Current step in try2 branch:
Not yet tested in hardware, started AHCI implementation (currently coded registers and DMA engine, that processes command table/PRD list,
Not yet tested in hardware, started AHCI implementation (currently coded registers and DMA engine, that processes command table/PRD list,
Transfers data between clock domains, re-aligns between WORD size granularity, H
AB
32-bit data and 64-bit AXI accesses.
Transfers data between clock domains, re-aligns between WORD size granularity, H
BA
32-bit data and 64-bit AXI accesses.
# Current step in main branch:
# Current step in main branch:
Testing basic functionallity of a host.
Testing basic functionallity of a host.
Trying out pio access.
Trying out pio access.
...
...
helpers/create_ahci_registers.py
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ce85dcb3
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host/transport.v
View file @
ce85dcb3
...
@@ -514,7 +514,7 @@ always @ (posedge clk)
...
@@ -514,7 +514,7 @@ always @ (posedge clk)
if
(
ll_data_val_in
)
if
(
ll_data_val_in
)
begin
begin
if
(
dword_cnt
==
14'd2049
)
if
(
dword_cnt
==
14'd2049
)
// if too much data for a data FIS TODO handle this exc
pe
tion properly
// if too much data for a data FIS TODO handle this exc
ep
tion properly
state
<=
STATE_IDLE
;
state
<=
STATE_IDLE
;
else
else
// continuing receiving data
// continuing receiving data
...
...
includes/ahci_types.vh
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ce85dcb3
...
@@ -2,7 +2,7 @@
...
@@ -2,7 +2,7 @@
, .INIT_10 (256'h0000000000000000555555555555000000000000000000005555555555500000)
, .INIT_10 (256'h0000000000000000555555555555000000000000000000005555555555500000)
, .INIT_11 (256'h000000000000000055054004000001C15551400000000455AAA28000000008AA)
, .INIT_11 (256'h000000000000000055054004000001C15551400000000455AAA28000000008AA)
, .INIT_12 (256'h0000000000550000000000000000000000000000000000000000000000000000)
, .INIT_12 (256'h0000000000550000000000000000000000000000000000000000000000000000)
, .INIT_13 (256'h00000000AAAAAAAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF002AAAAA00AA000
8
)
, .INIT_13 (256'h00000000AAAAAAAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF002AAAAA00AA000
A
)
, .INIT_14 (256'h000000000000000000000000000000000001555555555550000000000055000D)
, .INIT_14 (256'h000000000000000000000000000000000001555555555550000000000055000D)
, .INIT_17 (256'h5555555555555555555555555555555555555555555555555555555555555555)
, .INIT_17 (256'h5555555555555555555555555555555555555555555555555555555555555555)
, .INIT_18 (256'h00000000000055550000000000000000AA820000001000140000000000000000)
, .INIT_18 (256'h00000000000055550000000000000000AA820000001000140000000000000000)
...
...
utils/ahci_dma.v
View file @
ce85dcb3
/*******************************************************************************
/*******************************************************************************
* Module: ahci_dma
* Module: ahci_dma
* Date:2016-01-01
* Date:2016-01-01
* Author:
andrey
* Author:
Andrey Filippov
* Description: DMA R/W over 64-AXI channel for AHCI implementation
* Description: DMA R/W over 64-AXI channel for AHCI implementation
*
*
* Copyright (c) 2016 Elphel, Inc .
* Copyright (c) 2016 Elphel, Inc .
...
...
utils/ahci_fis_receive.v
0 → 100644
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ce85dcb3
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